1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2024 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 #include <drm/drm_drv.h> 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "mes_userqueue.h" 28 #include "amdgpu_userq_fence.h" 29 30 #define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE 31 #define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE 32 33 static int 34 mes_userq_create_wptr_mapping(struct amdgpu_device *adev, 35 struct amdgpu_userq_mgr *uq_mgr, 36 struct amdgpu_usermode_queue *queue, 37 uint64_t wptr) 38 { 39 struct amdgpu_bo_va_mapping *wptr_mapping; 40 struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj; 41 struct amdgpu_bo *obj; 42 struct amdgpu_vm *vm = queue->vm; 43 struct drm_exec exec; 44 int ret; 45 46 wptr &= AMDGPU_GMC_HOLE_MASK; 47 48 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 2); 49 drm_exec_until_all_locked(&exec) { 50 ret = amdgpu_vm_lock_pd(vm, &exec, 1); 51 drm_exec_retry_on_contention(&exec); 52 if (unlikely(ret)) 53 goto fail_lock; 54 55 wptr_mapping = amdgpu_vm_bo_lookup_mapping(vm, wptr >> PAGE_SHIFT); 56 if (!wptr_mapping) { 57 ret = -EINVAL; 58 goto fail_lock; 59 } 60 61 obj = wptr_mapping->bo_va->base.bo; 62 ret = drm_exec_lock_obj(&exec, &obj->tbo.base); 63 drm_exec_retry_on_contention(&exec); 64 if (unlikely(ret)) 65 goto fail_lock; 66 } 67 68 wptr_obj->obj = amdgpu_bo_ref(wptr_mapping->bo_va->base.bo); 69 if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) { 70 ret = -EINVAL; 71 goto fail_map; 72 } 73 74 /* TODO use eviction fence instead of pinning. */ 75 ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT); 76 if (ret) { 77 DRM_ERROR("Failed to pin wptr bo. ret %d\n", ret); 78 goto fail_map; 79 } 80 81 ret = amdgpu_ttm_alloc_gart(&wptr_obj->obj->tbo); 82 if (ret) { 83 DRM_ERROR("Failed to bind bo to GART. ret %d\n", ret); 84 goto fail_alloc_gart; 85 } 86 87 queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj); 88 89 drm_exec_fini(&exec); 90 return 0; 91 92 fail_alloc_gart: 93 amdgpu_bo_unpin(wptr_obj->obj); 94 fail_map: 95 amdgpu_bo_unref(&wptr_obj->obj); 96 fail_lock: 97 drm_exec_fini(&exec); 98 return ret; 99 100 } 101 102 static int convert_to_mes_priority(int priority) 103 { 104 switch (priority) { 105 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW: 106 default: 107 return AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 108 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW: 109 return AMDGPU_MES_PRIORITY_LEVEL_LOW; 110 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH: 111 return AMDGPU_MES_PRIORITY_LEVEL_MEDIUM; 112 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH: 113 return AMDGPU_MES_PRIORITY_LEVEL_HIGH; 114 } 115 } 116 117 static int mes_userq_map(struct amdgpu_usermode_queue *queue) 118 { 119 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 120 struct amdgpu_device *adev = uq_mgr->adev; 121 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 122 struct amdgpu_mqd_prop *userq_props = queue->userq_prop; 123 struct mes_add_queue_input queue_input; 124 int r; 125 126 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input)); 127 128 queue_input.process_va_start = 0; 129 queue_input.process_va_end = adev->vm_manager.max_pfn - 1; 130 131 /* set process quantum to 10 ms and gang quantum to 1 ms as default */ 132 queue_input.process_quantum = 100000; 133 queue_input.gang_quantum = 10000; 134 queue_input.paging = false; 135 136 queue_input.process_context_addr = uq_mgr->proc_ctx_obj.gpu_addr; 137 queue_input.gang_context_addr = ctx->gpu_addr; 138 queue_input.inprocess_gang_priority = AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 139 queue_input.gang_global_priority_level = convert_to_mes_priority(queue->priority); 140 141 queue_input.process_id = queue->vm->pasid; 142 queue_input.queue_type = queue->queue_type; 143 queue_input.mqd_addr = queue->mqd.gpu_addr; 144 queue_input.wptr_addr = userq_props->wptr_gpu_addr; 145 queue_input.queue_size = userq_props->queue_size >> 2; 146 queue_input.doorbell_offset = userq_props->doorbell_index; 147 queue_input.page_table_base_addr = amdgpu_gmc_pd_addr(queue->vm->root.bo); 148 queue_input.wptr_mc_addr = queue->wptr_obj.gpu_addr; 149 150 amdgpu_mes_lock(&adev->mes); 151 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); 152 amdgpu_mes_unlock(&adev->mes); 153 if (r) { 154 DRM_ERROR("Failed to map queue in HW, err (%d)\n", r); 155 return r; 156 } 157 158 DRM_DEBUG_DRIVER("Queue (doorbell:%d) mapped successfully\n", userq_props->doorbell_index); 159 return 0; 160 } 161 162 static int mes_userq_unmap(struct amdgpu_usermode_queue *queue) 163 { 164 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 165 struct amdgpu_device *adev = uq_mgr->adev; 166 struct mes_remove_queue_input queue_input; 167 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 168 int r; 169 170 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); 171 queue_input.doorbell_offset = queue->doorbell_index; 172 queue_input.gang_context_addr = ctx->gpu_addr; 173 174 amdgpu_mes_lock(&adev->mes); 175 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input); 176 amdgpu_mes_unlock(&adev->mes); 177 if (r) 178 DRM_ERROR("Failed to unmap queue in HW, err (%d)\n", r); 179 return r; 180 } 181 182 int mes_userq_reset(struct amdgpu_usermode_queue *queue) 183 { 184 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 185 struct amdgpu_device *adev = uq_mgr->adev; 186 struct mes_reset_queue_input queue_input; 187 int r; 188 189 /* XXX: add a FW version check for SDMA per queue reset */ 190 memset(&queue_input, 0x0, sizeof(struct mes_reset_queue_input)); 191 queue_input.doorbell_offset = queue->doorbell_index; 192 queue_input.queue_type = queue->queue_type; 193 194 amdgpu_mes_lock(&adev->mes); 195 r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input); 196 amdgpu_mes_unlock(&adev->mes); 197 if (r) 198 return r; 199 return mes_userq_unmap(queue); 200 } 201 202 int mes_userq_reset_queue(struct amdgpu_device *adev, 203 struct amdgpu_usermode_queue *guilty_uq, 204 int queue_type, 205 unsigned int pipe, 206 unsigned int queue, 207 unsigned int db) 208 { 209 struct amdgpu_usermode_queue *uq; 210 bool use_mmio = adev->gfx.mec.use_mmio_for_reset; 211 unsigned long uq_id; 212 int r; 213 214 xa_for_each(&adev->userq_doorbell_xa, uq_id, uq) { 215 if (uq->queue_type == queue_type) { 216 if (uq == guilty_uq) 217 continue; 218 if (uq->doorbell_index == db) { 219 uq->state = AMDGPU_USERQ_STATE_HUNG; 220 if (use_mmio) 221 r = amdgpu_mes_reset_queue_mmio(adev, queue_type, 0, 1, pipe, queue, 0); 222 else 223 r = amdgpu_mes_reset_user_queue(adev, queue_type, db, 0); 224 if (r) 225 return r; 226 r = mes_userq_unmap(uq); 227 if (r) 228 return r; 229 atomic_inc(&adev->gpu_reset_counter); 230 amdgpu_userq_fence_driver_force_completion(uq); 231 drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, NULL); 232 break; 233 } 234 } 235 } 236 return 0; 237 } 238 239 static int mes_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr, 240 struct amdgpu_usermode_queue *queue, 241 struct drm_amdgpu_userq_in *mqd_user) 242 { 243 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 244 int r, size; 245 246 /* The FW expects at least one page space allocated for gang ctx. */ 247 size = AMDGPU_USERQ_GANG_CTX_SZ; 248 r = amdgpu_bo_create_kernel(uq_mgr->adev, size, 0, 249 AMDGPU_GEM_DOMAIN_GTT, 250 &ctx->obj, &ctx->gpu_addr, 251 &ctx->cpu_ptr); 252 if (r) { 253 DRM_ERROR("Failed to allocate ctx space bo for userqueue, err:%d\n", r); 254 return r; 255 } 256 257 memset(ctx->cpu_ptr, 0, size); 258 return 0; 259 } 260 261 static int mes_userq_create_proc_ctx_space(struct amdgpu_userq_mgr *uq_mgr) 262 { 263 int r = 0; 264 265 mutex_lock(&uq_mgr->proc_ctx_lock); 266 /* This check is a necessary because amdgpu_bo_create_kernel() 267 * calls helpers like amdgpu_bo_pin() and memset() unconditionally 268 */ 269 if (!uq_mgr->proc_ctx_obj.obj) { 270 r = amdgpu_bo_create_kernel(uq_mgr->adev, AMDGPU_USERQ_PROC_CTX_SZ, 271 0, AMDGPU_GEM_DOMAIN_GTT, 272 &uq_mgr->proc_ctx_obj.obj, 273 &uq_mgr->proc_ctx_obj.gpu_addr, 274 &uq_mgr->proc_ctx_obj.cpu_ptr); 275 276 if (!r) 277 memset(uq_mgr->proc_ctx_obj.cpu_ptr, 0, AMDGPU_USERQ_PROC_CTX_SZ); 278 } 279 280 mutex_unlock(&uq_mgr->proc_ctx_lock); 281 282 return r; 283 } 284 285 static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, 286 struct drm_amdgpu_userq_in *args_in) 287 { 288 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 289 struct amdgpu_device *adev = uq_mgr->adev; 290 struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; 291 struct drm_amdgpu_userq_in *mqd_user = args_in; 292 struct amdgpu_mqd_prop *userq_props; 293 int r; 294 295 /* Structure to initialize MQD for userqueue using generic MQD init function */ 296 userq_props = kzalloc_obj(struct amdgpu_mqd_prop); 297 if (!userq_props) { 298 DRM_ERROR("Failed to allocate memory for userq_props\n"); 299 return -ENOMEM; 300 } 301 302 r = amdgpu_bo_create_kernel(adev, 303 AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size), 304 0, AMDGPU_GEM_DOMAIN_GTT, 305 &queue->mqd.obj, &queue->mqd.gpu_addr, 306 &queue->mqd.cpu_ptr); 307 if (r) { 308 DRM_ERROR("Failed to create MQD object for userqueue\n"); 309 goto free_props; 310 } 311 312 memset(queue->mqd.cpu_ptr, 0, 313 AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size)); 314 315 /* Initialize the MQD BO with user given values */ 316 userq_props->wptr_gpu_addr = mqd_user->wptr_va; 317 userq_props->rptr_gpu_addr = mqd_user->rptr_va; 318 userq_props->queue_size = mqd_user->queue_size; 319 userq_props->hqd_base_gpu_addr = mqd_user->queue_va; 320 userq_props->mqd_gpu_addr = queue->mqd.gpu_addr; 321 userq_props->use_doorbell = true; 322 userq_props->doorbell_index = queue->doorbell_index; 323 userq_props->fence_address = queue->fence_drv->gpu_addr; 324 325 if (queue->queue_type == AMDGPU_HW_IP_COMPUTE) { 326 struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd; 327 328 if (mqd_user->mqd_size != sizeof(*compute_mqd)) { 329 DRM_ERROR("Invalid compute IP MQD size\n"); 330 r = -EINVAL; 331 goto free_mqd; 332 } 333 334 compute_mqd = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 335 if (IS_ERR(compute_mqd)) { 336 DRM_ERROR("Failed to read user MQD\n"); 337 r = -ENOMEM; 338 goto free_mqd; 339 } 340 341 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 342 if (r) { 343 kfree(compute_mqd); 344 goto free_mqd; 345 } 346 r = amdgpu_userq_input_va_validate(adev, queue, 347 compute_mqd->eop_va, 2048, 348 &queue->userq_vas.va.eop); 349 amdgpu_bo_unreserve(queue->vm->root.bo); 350 if (r) { 351 kfree(compute_mqd); 352 goto free_mqd; 353 } 354 355 userq_props->eop_gpu_addr = compute_mqd->eop_va; 356 userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL; 357 userq_props->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM; 358 userq_props->hqd_active = false; 359 userq_props->tmz_queue = 360 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; 361 kfree(compute_mqd); 362 } else if (queue->queue_type == AMDGPU_HW_IP_GFX) { 363 struct drm_amdgpu_userq_mqd_gfx11 *mqd_gfx_v11; 364 struct amdgpu_gfx_shadow_info shadow_info; 365 366 if (adev->gfx.funcs->get_gfx_shadow_info) { 367 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true); 368 } else { 369 r = -EINVAL; 370 goto free_mqd; 371 } 372 373 if (mqd_user->mqd_size != sizeof(*mqd_gfx_v11) || !mqd_user->mqd) { 374 DRM_ERROR("Invalid GFX MQD\n"); 375 r = -EINVAL; 376 goto free_mqd; 377 } 378 379 mqd_gfx_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 380 if (IS_ERR(mqd_gfx_v11)) { 381 DRM_ERROR("Failed to read user MQD\n"); 382 r = -ENOMEM; 383 goto free_mqd; 384 } 385 386 userq_props->shadow_addr = mqd_gfx_v11->shadow_va; 387 userq_props->csa_addr = mqd_gfx_v11->csa_va; 388 userq_props->tmz_queue = 389 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; 390 391 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 392 if (r) { 393 kfree(mqd_gfx_v11); 394 goto free_mqd; 395 } 396 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->shadow_va, 397 shadow_info.shadow_size, 398 &queue->userq_vas.va.shadow); 399 if (r) { 400 amdgpu_bo_unreserve(queue->vm->root.bo); 401 kfree(mqd_gfx_v11); 402 goto free_mqd; 403 } 404 405 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->csa_va, 406 shadow_info.csa_size, 407 &queue->userq_vas.va.csa); 408 amdgpu_bo_unreserve(queue->vm->root.bo); 409 if (r) { 410 kfree(mqd_gfx_v11); 411 goto free_mqd; 412 } 413 414 kfree(mqd_gfx_v11); 415 } else if (queue->queue_type == AMDGPU_HW_IP_DMA) { 416 struct drm_amdgpu_userq_mqd_sdma_gfx11 *mqd_sdma_v11; 417 418 if (mqd_user->mqd_size != sizeof(*mqd_sdma_v11) || !mqd_user->mqd) { 419 DRM_ERROR("Invalid SDMA MQD\n"); 420 r = -EINVAL; 421 goto free_mqd; 422 } 423 424 mqd_sdma_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 425 if (IS_ERR(mqd_sdma_v11)) { 426 DRM_ERROR("Failed to read sdma user MQD\n"); 427 r = -ENOMEM; 428 goto free_mqd; 429 } 430 431 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 432 if (r) { 433 kfree(mqd_sdma_v11); 434 goto free_mqd; 435 } 436 r = amdgpu_userq_input_va_validate(adev, queue, mqd_sdma_v11->csa_va, 437 32, 438 &queue->userq_vas.va.csa); 439 amdgpu_bo_unreserve(queue->vm->root.bo); 440 if (r) { 441 kfree(mqd_sdma_v11); 442 goto free_mqd; 443 } 444 445 userq_props->csa_addr = mqd_sdma_v11->csa_va; 446 kfree(mqd_sdma_v11); 447 } 448 449 queue->userq_prop = userq_props; 450 451 r = mqd_hw_default->init_mqd(adev, (void *)queue->mqd.cpu_ptr, userq_props); 452 if (r) { 453 DRM_ERROR("Failed to initialize MQD for userqueue\n"); 454 goto free_mqd; 455 } 456 457 /* Create per-process MES process context BO */ 458 r = mes_userq_create_proc_ctx_space(uq_mgr); 459 if (r) { 460 DRM_ERROR("Failed to allocate MES process context space bo, error: %d\n", r); 461 goto free_mqd; 462 } 463 464 /* Create BO of a gang for FW operations */ 465 r = mes_userq_create_ctx_space(uq_mgr, queue, mqd_user); 466 if (r) { 467 DRM_ERROR("Failed to allocate BO for userqueue (%d)", r); 468 goto free_mqd; 469 } 470 471 /* FW expects WPTR BOs to be mapped into GART */ 472 r = mes_userq_create_wptr_mapping(adev, uq_mgr, queue, userq_props->wptr_gpu_addr); 473 if (r) { 474 DRM_ERROR("Failed to create WPTR mapping\n"); 475 goto free_ctx; 476 } 477 478 return 0; 479 480 free_ctx: 481 amdgpu_bo_free_kernel(&queue->fw_obj.obj, &queue->fw_obj.gpu_addr, 482 &queue->fw_obj.cpu_ptr); 483 484 free_mqd: 485 amdgpu_bo_free_kernel(&queue->mqd.obj, &queue->mqd.gpu_addr, 486 &queue->mqd.cpu_ptr); 487 488 free_props: 489 kfree(userq_props); 490 491 return r; 492 } 493 494 static void mes_userq_mqd_destroy(struct amdgpu_usermode_queue *queue) 495 { 496 497 amdgpu_bo_free_kernel(&queue->fw_obj.obj, &queue->fw_obj.gpu_addr, 498 &queue->fw_obj.cpu_ptr); 499 kfree(queue->userq_prop); 500 amdgpu_bo_free_kernel(&queue->mqd.obj, &queue->mqd.gpu_addr, 501 &queue->mqd.cpu_ptr); 502 503 amdgpu_bo_reserve(queue->wptr_obj.obj, true); 504 amdgpu_bo_unpin(queue->wptr_obj.obj); 505 amdgpu_bo_unreserve(queue->wptr_obj.obj); 506 amdgpu_bo_unref(&queue->wptr_obj.obj); 507 } 508 509 static int mes_userq_preempt(struct amdgpu_usermode_queue *queue) 510 { 511 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 512 struct amdgpu_device *adev = uq_mgr->adev; 513 struct mes_suspend_gang_input queue_input; 514 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 515 signed long timeout = 2100000; /* 2100 ms */ 516 u64 fence_gpu_addr; 517 u32 fence_offset; 518 u64 *fence_ptr; 519 int i, r; 520 521 if (queue->state != AMDGPU_USERQ_STATE_MAPPED) 522 return 0; 523 r = amdgpu_device_wb_get(adev, &fence_offset); 524 if (r) 525 return r; 526 527 fence_gpu_addr = adev->wb.gpu_addr + (fence_offset * 4); 528 fence_ptr = (u64 *)&adev->wb.wb[fence_offset]; 529 *fence_ptr = 0; 530 531 memset(&queue_input, 0x0, sizeof(struct mes_suspend_gang_input)); 532 queue_input.gang_context_addr = ctx->gpu_addr; 533 queue_input.suspend_fence_addr = fence_gpu_addr; 534 queue_input.suspend_fence_value = 1; 535 amdgpu_mes_lock(&adev->mes); 536 r = adev->mes.funcs->suspend_gang(&adev->mes, &queue_input); 537 amdgpu_mes_unlock(&adev->mes); 538 if (r) { 539 DRM_ERROR("Failed to suspend gang: %d\n", r); 540 goto out; 541 } 542 543 for (i = 0; i < timeout; i++) { 544 if (*fence_ptr == 1) 545 goto out; 546 udelay(1); 547 } 548 r = -ETIMEDOUT; 549 550 out: 551 amdgpu_device_wb_free(adev, fence_offset); 552 return r; 553 } 554 555 static int mes_userq_restore(struct amdgpu_usermode_queue *queue) 556 { 557 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 558 struct amdgpu_device *adev = uq_mgr->adev; 559 struct mes_resume_gang_input queue_input; 560 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 561 int r; 562 563 if (queue->state == AMDGPU_USERQ_STATE_HUNG) 564 return -EINVAL; 565 if (queue->state != AMDGPU_USERQ_STATE_PREEMPTED) 566 return 0; 567 568 memset(&queue_input, 0x0, sizeof(struct mes_resume_gang_input)); 569 queue_input.gang_context_addr = ctx->gpu_addr; 570 571 amdgpu_mes_lock(&adev->mes); 572 r = adev->mes.funcs->resume_gang(&adev->mes, &queue_input); 573 amdgpu_mes_unlock(&adev->mes); 574 if (r) 575 dev_err(adev->dev, "Failed to resume queue, err (%d)\n", r); 576 return r; 577 } 578 579 const struct amdgpu_userq_funcs userq_mes_funcs = { 580 .mqd_create = mes_userq_mqd_create, 581 .mqd_destroy = mes_userq_mqd_destroy, 582 .unmap = mes_userq_unmap, 583 .map = mes_userq_map, 584 .preempt = mes_userq_preempt, 585 .restore = mes_userq_restore, 586 .reset = mes_userq_reset, 587 }; 588