1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2024 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 #include <drm/drm_drv.h> 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "mes_userqueue.h" 28 #include "amdgpu_userq_fence.h" 29 30 #define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE 31 #define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE 32 33 static int 34 mes_userq_create_wptr_mapping(struct amdgpu_device *adev, 35 struct amdgpu_userq_mgr *uq_mgr, 36 struct amdgpu_usermode_queue *queue, 37 uint64_t wptr) 38 { 39 struct amdgpu_bo_va_mapping *wptr_mapping; 40 struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj; 41 struct amdgpu_bo *obj; 42 struct amdgpu_vm *vm = queue->vm; 43 struct drm_exec exec; 44 int ret; 45 46 wptr &= AMDGPU_GMC_HOLE_MASK; 47 48 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 2); 49 drm_exec_until_all_locked(&exec) { 50 ret = amdgpu_vm_lock_pd(vm, &exec, 1); 51 drm_exec_retry_on_contention(&exec); 52 if (unlikely(ret)) 53 goto fail_lock; 54 55 wptr_mapping = amdgpu_vm_bo_lookup_mapping(vm, wptr >> PAGE_SHIFT); 56 if (!wptr_mapping) { 57 ret = -EINVAL; 58 goto fail_lock; 59 } 60 61 obj = wptr_mapping->bo_va->base.bo; 62 ret = drm_exec_lock_obj(&exec, &obj->tbo.base); 63 drm_exec_retry_on_contention(&exec); 64 if (unlikely(ret)) 65 goto fail_lock; 66 } 67 68 wptr_obj->obj = amdgpu_bo_ref(wptr_mapping->bo_va->base.bo); 69 if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) { 70 ret = -EINVAL; 71 goto fail_map; 72 } 73 74 /* TODO use eviction fence instead of pinning. */ 75 ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT); 76 if (ret) { 77 DRM_ERROR("Failed to pin wptr bo. ret %d\n", ret); 78 goto fail_map; 79 } 80 81 ret = amdgpu_ttm_alloc_gart(&wptr_obj->obj->tbo); 82 if (ret) { 83 DRM_ERROR("Failed to bind bo to GART. ret %d\n", ret); 84 goto fail_alloc_gart; 85 } 86 87 queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj); 88 89 drm_exec_fini(&exec); 90 return 0; 91 92 fail_alloc_gart: 93 amdgpu_bo_unpin(wptr_obj->obj); 94 fail_map: 95 amdgpu_bo_unref(&wptr_obj->obj); 96 fail_lock: 97 drm_exec_fini(&exec); 98 return ret; 99 100 } 101 102 static int convert_to_mes_priority(int priority) 103 { 104 switch (priority) { 105 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW: 106 default: 107 return AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 108 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW: 109 return AMDGPU_MES_PRIORITY_LEVEL_LOW; 110 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH: 111 return AMDGPU_MES_PRIORITY_LEVEL_MEDIUM; 112 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH: 113 return AMDGPU_MES_PRIORITY_LEVEL_HIGH; 114 } 115 } 116 117 static int mes_userq_map(struct amdgpu_usermode_queue *queue) 118 { 119 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 120 struct amdgpu_device *adev = uq_mgr->adev; 121 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 122 struct amdgpu_mqd_prop *userq_props = queue->userq_prop; 123 struct mes_add_queue_input queue_input; 124 struct amdgpu_mes *mes = &adev->mes; 125 int r; 126 127 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input)); 128 129 queue_input.process_va_start = 0; 130 queue_input.process_va_end = adev->vm_manager.max_pfn - 1; 131 132 /* set process quantum to 10 ms and gang quantum to 1 ms as default */ 133 queue_input.process_quantum = 100000; 134 queue_input.gang_quantum = 10000; 135 queue_input.paging = false; 136 137 queue_input.process_context_addr = uq_mgr->proc_ctx_obj.gpu_addr; 138 queue_input.gang_context_addr = ctx->gpu_addr; 139 queue_input.inprocess_gang_priority = AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 140 queue_input.gang_global_priority_level = convert_to_mes_priority(queue->priority); 141 142 queue_input.process_id = queue->vm->pasid; 143 queue_input.queue_type = queue->queue_type; 144 queue_input.mqd_addr = queue->mqd.gpu_addr; 145 queue_input.wptr_addr = userq_props->wptr_gpu_addr; 146 queue_input.queue_size = userq_props->queue_size >> 2; 147 queue_input.doorbell_offset = userq_props->doorbell_index; 148 queue_input.page_table_base_addr = amdgpu_gmc_pd_addr(queue->vm->root.bo); 149 queue_input.wptr_mc_addr = queue->wptr_obj.gpu_addr; 150 if (mes->use_rs64mem) { 151 amdgpu_mes_alloc_proc_ctx_index(mes, queue); 152 queue_input.process_context_array_index = queue->proc_ctx_array_index; 153 } 154 amdgpu_mes_lock(&adev->mes); 155 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); 156 amdgpu_mes_unlock(&adev->mes); 157 if (r) { 158 DRM_ERROR("Failed to map queue in HW, err (%d)\n", r); 159 return r; 160 } 161 162 DRM_DEBUG_DRIVER("Queue (doorbell:%d) mapped successfully\n", userq_props->doorbell_index); 163 return 0; 164 } 165 166 static int mes_userq_unmap(struct amdgpu_usermode_queue *queue) 167 { 168 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 169 struct amdgpu_device *adev = uq_mgr->adev; 170 struct mes_remove_queue_input queue_input; 171 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 172 struct amdgpu_mes *mes = &adev->mes; 173 int r; 174 175 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); 176 queue_input.doorbell_offset = queue->doorbell_index; 177 queue_input.gang_context_addr = ctx->gpu_addr; 178 queue_input.queue_type = queue->queue_type; 179 180 amdgpu_mes_lock(&adev->mes); 181 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input); 182 amdgpu_mes_unlock(&adev->mes); 183 if (mes->use_rs64mem) 184 amdgpu_mes_free_proc_ctx_index(mes, queue); 185 if (r) 186 DRM_ERROR("Failed to unmap queue in HW, err (%d)\n", r); 187 return r; 188 } 189 190 int mes_userq_reset(struct amdgpu_usermode_queue *queue) 191 { 192 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 193 struct amdgpu_device *adev = uq_mgr->adev; 194 struct mes_reset_queue_input queue_input; 195 int r; 196 197 /* XXX: add a FW version check for SDMA per queue reset */ 198 memset(&queue_input, 0x0, sizeof(struct mes_reset_queue_input)); 199 queue_input.doorbell_offset = queue->doorbell_index; 200 queue_input.queue_type = queue->queue_type; 201 202 amdgpu_mes_lock(&adev->mes); 203 r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input); 204 amdgpu_mes_unlock(&adev->mes); 205 if (r) 206 return r; 207 return mes_userq_unmap(queue); 208 } 209 210 int mes_userq_reset_queue(struct amdgpu_device *adev, 211 struct amdgpu_usermode_queue *guilty_uq, 212 int queue_type, 213 unsigned int pipe, 214 unsigned int queue, 215 unsigned int db) 216 { 217 struct amdgpu_usermode_queue *uq; 218 bool use_mmio = adev->gfx.mec.use_mmio_for_reset; 219 unsigned long uq_id; 220 int r; 221 222 xa_for_each(&adev->userq_doorbell_xa, uq_id, uq) { 223 if (uq->queue_type == queue_type) { 224 if (uq == guilty_uq) 225 continue; 226 if (uq->doorbell_index == db) { 227 uq->state = AMDGPU_USERQ_STATE_HUNG; 228 if (use_mmio) 229 r = amdgpu_mes_reset_queue_mmio(adev, queue_type, 0, 1, pipe, queue, 0); 230 else 231 r = amdgpu_mes_reset_user_queue(adev, queue_type, db, 0); 232 if (r) 233 return r; 234 r = mes_userq_unmap(uq); 235 if (r) 236 return r; 237 atomic_inc(&adev->gpu_reset_counter); 238 amdgpu_userq_fence_driver_force_completion(uq); 239 drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, NULL); 240 break; 241 } 242 } 243 } 244 return 0; 245 } 246 247 static int mes_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr, 248 struct amdgpu_usermode_queue *queue, 249 struct drm_amdgpu_userq_in *mqd_user) 250 { 251 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 252 int r, size; 253 254 /* The FW expects at least one page space allocated for gang ctx. */ 255 size = AMDGPU_USERQ_GANG_CTX_SZ; 256 r = amdgpu_bo_create_kernel(uq_mgr->adev, size, 0, 257 AMDGPU_GEM_DOMAIN_GTT, 258 &ctx->obj, &ctx->gpu_addr, 259 &ctx->cpu_ptr); 260 if (r) { 261 DRM_ERROR("Failed to allocate ctx space bo for userqueue, err:%d\n", r); 262 return r; 263 } 264 265 memset(ctx->cpu_ptr, 0, size); 266 return 0; 267 } 268 269 static int mes_userq_create_proc_ctx_space(struct amdgpu_userq_mgr *uq_mgr) 270 { 271 int r = 0; 272 273 mutex_lock(&uq_mgr->proc_ctx_lock); 274 /* This check is a necessary because amdgpu_bo_create_kernel() 275 * calls helpers like amdgpu_bo_pin() and memset() unconditionally 276 */ 277 if (!uq_mgr->proc_ctx_obj.obj) { 278 r = amdgpu_bo_create_kernel(uq_mgr->adev, AMDGPU_USERQ_PROC_CTX_SZ, 279 0, AMDGPU_GEM_DOMAIN_GTT, 280 &uq_mgr->proc_ctx_obj.obj, 281 &uq_mgr->proc_ctx_obj.gpu_addr, 282 &uq_mgr->proc_ctx_obj.cpu_ptr); 283 284 if (!r) 285 memset(uq_mgr->proc_ctx_obj.cpu_ptr, 0, AMDGPU_USERQ_PROC_CTX_SZ); 286 } 287 288 mutex_unlock(&uq_mgr->proc_ctx_lock); 289 290 return r; 291 } 292 293 static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, 294 struct drm_amdgpu_userq_in *args_in) 295 { 296 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 297 struct amdgpu_device *adev = uq_mgr->adev; 298 struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; 299 struct drm_amdgpu_userq_in *mqd_user = args_in; 300 struct amdgpu_mqd_prop *userq_props; 301 int r; 302 303 /* Structure to initialize MQD for userqueue using generic MQD init function */ 304 userq_props = kzalloc_obj(struct amdgpu_mqd_prop); 305 if (!userq_props) { 306 DRM_ERROR("Failed to allocate memory for userq_props\n"); 307 return -ENOMEM; 308 } 309 310 r = amdgpu_bo_create_kernel(adev, 311 AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size), 312 0, AMDGPU_GEM_DOMAIN_GTT, 313 &queue->mqd.obj, &queue->mqd.gpu_addr, 314 &queue->mqd.cpu_ptr); 315 if (r) { 316 DRM_ERROR("Failed to create MQD object for userqueue\n"); 317 goto free_props; 318 } 319 320 memset(queue->mqd.cpu_ptr, 0, 321 AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size)); 322 323 /* Initialize the MQD BO with user given values */ 324 userq_props->wptr_gpu_addr = mqd_user->wptr_va; 325 userq_props->rptr_gpu_addr = mqd_user->rptr_va; 326 userq_props->queue_size = mqd_user->queue_size; 327 userq_props->hqd_base_gpu_addr = mqd_user->queue_va; 328 userq_props->mqd_gpu_addr = queue->mqd.gpu_addr; 329 userq_props->use_doorbell = true; 330 userq_props->doorbell_index = queue->doorbell_index; 331 userq_props->fence_address = queue->fence_drv->gpu_addr; 332 333 if (queue->queue_type == AMDGPU_HW_IP_COMPUTE) { 334 struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd; 335 336 if (mqd_user->mqd_size != sizeof(*compute_mqd)) { 337 DRM_ERROR("Invalid compute IP MQD size\n"); 338 r = -EINVAL; 339 goto free_mqd; 340 } 341 342 compute_mqd = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 343 if (IS_ERR(compute_mqd)) { 344 DRM_ERROR("Failed to read user MQD\n"); 345 r = -ENOMEM; 346 goto free_mqd; 347 } 348 349 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 350 if (r) { 351 kfree(compute_mqd); 352 goto free_mqd; 353 } 354 r = amdgpu_userq_input_va_validate(adev, queue, 355 compute_mqd->eop_va, 2048, 356 &queue->userq_vas.va.eop); 357 amdgpu_bo_unreserve(queue->vm->root.bo); 358 if (r) { 359 kfree(compute_mqd); 360 goto free_mqd; 361 } 362 363 userq_props->eop_gpu_addr = compute_mqd->eop_va; 364 userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL; 365 userq_props->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM; 366 userq_props->hqd_active = false; 367 userq_props->tmz_queue = 368 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; 369 kfree(compute_mqd); 370 } else if (queue->queue_type == AMDGPU_HW_IP_GFX) { 371 struct drm_amdgpu_userq_mqd_gfx11 *mqd_gfx_v11; 372 struct amdgpu_gfx_shadow_info shadow_info; 373 374 if (adev->gfx.funcs->get_gfx_shadow_info) { 375 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true); 376 } else { 377 r = -EINVAL; 378 goto free_mqd; 379 } 380 381 if (mqd_user->mqd_size != sizeof(*mqd_gfx_v11) || !mqd_user->mqd) { 382 DRM_ERROR("Invalid GFX MQD\n"); 383 r = -EINVAL; 384 goto free_mqd; 385 } 386 387 mqd_gfx_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 388 if (IS_ERR(mqd_gfx_v11)) { 389 DRM_ERROR("Failed to read user MQD\n"); 390 r = -ENOMEM; 391 goto free_mqd; 392 } 393 394 userq_props->shadow_addr = mqd_gfx_v11->shadow_va; 395 userq_props->csa_addr = mqd_gfx_v11->csa_va; 396 userq_props->tmz_queue = 397 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; 398 399 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 400 if (r) { 401 kfree(mqd_gfx_v11); 402 goto free_mqd; 403 } 404 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->shadow_va, 405 shadow_info.shadow_size, 406 &queue->userq_vas.va.shadow); 407 if (r) { 408 amdgpu_bo_unreserve(queue->vm->root.bo); 409 kfree(mqd_gfx_v11); 410 goto free_mqd; 411 } 412 413 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->csa_va, 414 shadow_info.csa_size, 415 &queue->userq_vas.va.csa); 416 amdgpu_bo_unreserve(queue->vm->root.bo); 417 if (r) { 418 kfree(mqd_gfx_v11); 419 goto free_mqd; 420 } 421 422 kfree(mqd_gfx_v11); 423 } else if (queue->queue_type == AMDGPU_HW_IP_DMA) { 424 struct drm_amdgpu_userq_mqd_sdma_gfx11 *mqd_sdma_v11; 425 426 if (mqd_user->mqd_size != sizeof(*mqd_sdma_v11) || !mqd_user->mqd) { 427 DRM_ERROR("Invalid SDMA MQD\n"); 428 r = -EINVAL; 429 goto free_mqd; 430 } 431 432 mqd_sdma_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 433 if (IS_ERR(mqd_sdma_v11)) { 434 DRM_ERROR("Failed to read sdma user MQD\n"); 435 r = -ENOMEM; 436 goto free_mqd; 437 } 438 439 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 440 if (r) { 441 kfree(mqd_sdma_v11); 442 goto free_mqd; 443 } 444 r = amdgpu_userq_input_va_validate(adev, queue, mqd_sdma_v11->csa_va, 445 32, 446 &queue->userq_vas.va.csa); 447 amdgpu_bo_unreserve(queue->vm->root.bo); 448 if (r) { 449 kfree(mqd_sdma_v11); 450 goto free_mqd; 451 } 452 453 userq_props->csa_addr = mqd_sdma_v11->csa_va; 454 kfree(mqd_sdma_v11); 455 } 456 457 queue->userq_prop = userq_props; 458 459 r = mqd_hw_default->init_mqd(adev, (void *)queue->mqd.cpu_ptr, userq_props); 460 if (r) { 461 DRM_ERROR("Failed to initialize MQD for userqueue\n"); 462 goto free_mqd; 463 } 464 465 /* Create per-process MES process context BO */ 466 r = mes_userq_create_proc_ctx_space(uq_mgr); 467 if (r) { 468 DRM_ERROR("Failed to allocate MES process context space bo, error: %d\n", r); 469 goto free_mqd; 470 } 471 472 /* Create BO of a gang for FW operations */ 473 r = mes_userq_create_ctx_space(uq_mgr, queue, mqd_user); 474 if (r) { 475 DRM_ERROR("Failed to allocate BO for userqueue (%d)", r); 476 goto free_mqd; 477 } 478 479 /* FW expects WPTR BOs to be mapped into GART */ 480 r = mes_userq_create_wptr_mapping(adev, uq_mgr, queue, userq_props->wptr_gpu_addr); 481 if (r) { 482 DRM_ERROR("Failed to create WPTR mapping\n"); 483 goto free_ctx; 484 } 485 486 return 0; 487 488 free_ctx: 489 amdgpu_bo_free_kernel(&queue->fw_obj.obj, &queue->fw_obj.gpu_addr, 490 &queue->fw_obj.cpu_ptr); 491 492 free_mqd: 493 amdgpu_bo_free_kernel(&queue->mqd.obj, &queue->mqd.gpu_addr, 494 &queue->mqd.cpu_ptr); 495 496 free_props: 497 kfree(userq_props); 498 499 return r; 500 } 501 502 static void mes_userq_mqd_destroy(struct amdgpu_usermode_queue *queue) 503 { 504 505 amdgpu_bo_free_kernel(&queue->fw_obj.obj, &queue->fw_obj.gpu_addr, 506 &queue->fw_obj.cpu_ptr); 507 kfree(queue->userq_prop); 508 amdgpu_bo_free_kernel(&queue->mqd.obj, &queue->mqd.gpu_addr, 509 &queue->mqd.cpu_ptr); 510 511 amdgpu_bo_reserve(queue->wptr_obj.obj, true); 512 amdgpu_bo_unpin(queue->wptr_obj.obj); 513 amdgpu_bo_unreserve(queue->wptr_obj.obj); 514 amdgpu_bo_unref(&queue->wptr_obj.obj); 515 } 516 517 static int mes_userq_preempt(struct amdgpu_usermode_queue *queue) 518 { 519 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 520 struct amdgpu_device *adev = uq_mgr->adev; 521 struct mes_suspend_gang_input queue_input; 522 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 523 signed long timeout = 2100000; /* 2100 ms */ 524 u64 fence_gpu_addr; 525 u32 fence_offset; 526 u64 *fence_ptr; 527 int i, r; 528 529 if (queue->state != AMDGPU_USERQ_STATE_MAPPED) 530 return 0; 531 r = amdgpu_wb_get(adev, &fence_offset); 532 if (r) 533 return r; 534 535 fence_gpu_addr = adev->wb.gpu_addr + (fence_offset * 4); 536 fence_ptr = (u64 *)&adev->wb.wb[fence_offset]; 537 *fence_ptr = 0; 538 539 memset(&queue_input, 0x0, sizeof(struct mes_suspend_gang_input)); 540 queue_input.gang_context_addr = ctx->gpu_addr; 541 queue_input.suspend_fence_addr = fence_gpu_addr; 542 queue_input.suspend_fence_value = 1; 543 amdgpu_mes_lock(&adev->mes); 544 r = adev->mes.funcs->suspend_gang(&adev->mes, &queue_input); 545 amdgpu_mes_unlock(&adev->mes); 546 if (r) { 547 DRM_ERROR("Failed to suspend gang: %d\n", r); 548 goto out; 549 } 550 551 for (i = 0; i < timeout; i++) { 552 if (*fence_ptr == 1) 553 goto out; 554 udelay(1); 555 } 556 r = -ETIMEDOUT; 557 558 out: 559 amdgpu_wb_free(adev, fence_offset); 560 return r; 561 } 562 563 static int mes_userq_restore(struct amdgpu_usermode_queue *queue) 564 { 565 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 566 struct amdgpu_device *adev = uq_mgr->adev; 567 struct mes_resume_gang_input queue_input; 568 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 569 int r; 570 571 if (queue->state == AMDGPU_USERQ_STATE_HUNG) 572 return -EINVAL; 573 if (queue->state != AMDGPU_USERQ_STATE_PREEMPTED) 574 return 0; 575 576 memset(&queue_input, 0x0, sizeof(struct mes_resume_gang_input)); 577 queue_input.gang_context_addr = ctx->gpu_addr; 578 579 amdgpu_mes_lock(&adev->mes); 580 r = adev->mes.funcs->resume_gang(&adev->mes, &queue_input); 581 amdgpu_mes_unlock(&adev->mes); 582 if (r) 583 dev_err(adev->dev, "Failed to resume queue, err (%d)\n", r); 584 return r; 585 } 586 587 const struct amdgpu_userq_funcs userq_mes_funcs = { 588 .mqd_create = mes_userq_mqd_create, 589 .mqd_destroy = mes_userq_mqd_destroy, 590 .unmap = mes_userq_unmap, 591 .map = mes_userq_map, 592 .preempt = mes_userq_preempt, 593 .restore = mes_userq_restore, 594 .reset = mes_userq_reset, 595 }; 596