1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2024 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 #include <drm/drm_drv.h> 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "mes_userqueue.h" 28 #include "amdgpu_userq_fence.h" 29 30 #define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE 31 #define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE 32 33 static int 34 mes_userq_create_wptr_mapping(struct amdgpu_device *adev, 35 struct amdgpu_userq_mgr *uq_mgr, 36 struct amdgpu_usermode_queue *queue, 37 uint64_t wptr) 38 { 39 struct amdgpu_bo_va_mapping *wptr_mapping; 40 struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj; 41 struct amdgpu_bo *obj; 42 struct amdgpu_vm *vm = queue->vm; 43 struct drm_exec exec; 44 int ret; 45 46 wptr &= AMDGPU_GMC_HOLE_MASK; 47 48 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 2); 49 drm_exec_until_all_locked(&exec) { 50 ret = amdgpu_vm_lock_pd(vm, &exec, 1); 51 drm_exec_retry_on_contention(&exec); 52 if (unlikely(ret)) 53 goto fail_lock; 54 55 wptr_mapping = amdgpu_vm_bo_lookup_mapping(vm, wptr >> PAGE_SHIFT); 56 if (!wptr_mapping) { 57 ret = -EINVAL; 58 goto fail_lock; 59 } 60 61 obj = wptr_mapping->bo_va->base.bo; 62 ret = drm_exec_lock_obj(&exec, &obj->tbo.base); 63 drm_exec_retry_on_contention(&exec); 64 if (unlikely(ret)) 65 goto fail_lock; 66 } 67 68 wptr_obj->obj = amdgpu_bo_ref(wptr_mapping->bo_va->base.bo); 69 if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) { 70 ret = -EINVAL; 71 goto fail_map; 72 } 73 74 /* TODO use eviction fence instead of pinning. */ 75 ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT); 76 if (ret) { 77 DRM_ERROR("Failed to pin wptr bo. ret %d\n", ret); 78 goto fail_map; 79 } 80 81 ret = amdgpu_ttm_alloc_gart(&wptr_obj->obj->tbo); 82 if (ret) { 83 DRM_ERROR("Failed to bind bo to GART. ret %d\n", ret); 84 goto fail_alloc_gart; 85 } 86 87 queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj); 88 89 drm_exec_fini(&exec); 90 return 0; 91 92 fail_alloc_gart: 93 amdgpu_bo_unpin(wptr_obj->obj); 94 fail_map: 95 amdgpu_bo_unref(&wptr_obj->obj); 96 fail_lock: 97 drm_exec_fini(&exec); 98 return ret; 99 100 } 101 102 static int convert_to_mes_priority(int priority) 103 { 104 switch (priority) { 105 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW: 106 default: 107 return AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 108 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW: 109 return AMDGPU_MES_PRIORITY_LEVEL_LOW; 110 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH: 111 return AMDGPU_MES_PRIORITY_LEVEL_MEDIUM; 112 case AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH: 113 return AMDGPU_MES_PRIORITY_LEVEL_HIGH; 114 } 115 } 116 117 static int mes_userq_map(struct amdgpu_usermode_queue *queue) 118 { 119 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 120 struct amdgpu_device *adev = uq_mgr->adev; 121 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 122 struct amdgpu_mqd_prop *userq_props = queue->userq_prop; 123 struct mes_add_queue_input queue_input; 124 int r; 125 126 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input)); 127 128 queue_input.process_va_start = 0; 129 queue_input.process_va_end = adev->vm_manager.max_pfn - 1; 130 131 /* set process quantum to 10 ms and gang quantum to 1 ms as default */ 132 queue_input.process_quantum = 100000; 133 queue_input.gang_quantum = 10000; 134 queue_input.paging = false; 135 136 queue_input.process_context_addr = ctx->gpu_addr; 137 queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ; 138 queue_input.inprocess_gang_priority = AMDGPU_MES_PRIORITY_LEVEL_NORMAL; 139 queue_input.gang_global_priority_level = convert_to_mes_priority(queue->priority); 140 141 queue_input.process_id = queue->vm->pasid; 142 queue_input.queue_type = queue->queue_type; 143 queue_input.mqd_addr = queue->mqd.gpu_addr; 144 queue_input.wptr_addr = userq_props->wptr_gpu_addr; 145 queue_input.queue_size = userq_props->queue_size >> 2; 146 queue_input.doorbell_offset = userq_props->doorbell_index; 147 queue_input.page_table_base_addr = amdgpu_gmc_pd_addr(queue->vm->root.bo); 148 queue_input.wptr_mc_addr = queue->wptr_obj.gpu_addr; 149 150 amdgpu_mes_lock(&adev->mes); 151 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); 152 amdgpu_mes_unlock(&adev->mes); 153 if (r) { 154 DRM_ERROR("Failed to map queue in HW, err (%d)\n", r); 155 return r; 156 } 157 158 DRM_DEBUG_DRIVER("Queue (doorbell:%d) mapped successfully\n", userq_props->doorbell_index); 159 return 0; 160 } 161 162 static int mes_userq_unmap(struct amdgpu_usermode_queue *queue) 163 { 164 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 165 struct amdgpu_device *adev = uq_mgr->adev; 166 struct mes_remove_queue_input queue_input; 167 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 168 int r; 169 170 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); 171 queue_input.doorbell_offset = queue->doorbell_index; 172 queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ; 173 174 amdgpu_mes_lock(&adev->mes); 175 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input); 176 amdgpu_mes_unlock(&adev->mes); 177 if (r) 178 DRM_ERROR("Failed to unmap queue in HW, err (%d)\n", r); 179 return r; 180 } 181 182 static int mes_userq_create_ctx_space(struct amdgpu_userq_mgr *uq_mgr, 183 struct amdgpu_usermode_queue *queue, 184 struct drm_amdgpu_userq_in *mqd_user) 185 { 186 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 187 int r, size; 188 189 /* 190 * The FW expects at least one page space allocated for 191 * process ctx and gang ctx each. Create an object 192 * for the same. 193 */ 194 size = AMDGPU_USERQ_PROC_CTX_SZ + AMDGPU_USERQ_GANG_CTX_SZ; 195 r = amdgpu_userq_create_object(uq_mgr, ctx, size); 196 if (r) { 197 DRM_ERROR("Failed to allocate ctx space bo for userqueue, err:%d\n", r); 198 return r; 199 } 200 201 return 0; 202 } 203 204 static int mes_userq_detect_and_reset(struct amdgpu_device *adev, 205 int queue_type) 206 { 207 int db_array_size = amdgpu_mes_get_hung_queue_db_array_size(adev); 208 struct mes_detect_and_reset_queue_input input; 209 struct amdgpu_usermode_queue *queue; 210 unsigned int hung_db_num = 0; 211 unsigned long queue_id; 212 u32 db_array[8]; 213 bool found_hung_queue = false; 214 int r, i; 215 216 if (db_array_size > 8) { 217 dev_err(adev->dev, "DB array size (%d vs 8) too small\n", 218 db_array_size); 219 return -EINVAL; 220 } 221 222 memset(&input, 0x0, sizeof(struct mes_detect_and_reset_queue_input)); 223 224 input.queue_type = queue_type; 225 226 amdgpu_mes_lock(&adev->mes); 227 r = amdgpu_mes_detect_and_reset_hung_queues(adev, queue_type, false, 228 &hung_db_num, db_array, 0); 229 amdgpu_mes_unlock(&adev->mes); 230 if (r) { 231 dev_err(adev->dev, "Failed to detect and reset queues, err (%d)\n", r); 232 } else if (hung_db_num) { 233 xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { 234 if (queue->queue_type == queue_type) { 235 for (i = 0; i < hung_db_num; i++) { 236 if (queue->doorbell_index == db_array[i]) { 237 queue->state = AMDGPU_USERQ_STATE_HUNG; 238 found_hung_queue = true; 239 atomic_inc(&adev->gpu_reset_counter); 240 amdgpu_userq_fence_driver_force_completion(queue); 241 drm_dev_wedged_event(adev_to_drm(adev), DRM_WEDGE_RECOVERY_NONE, NULL); 242 } 243 } 244 } 245 } 246 } 247 248 if (found_hung_queue) { 249 /* Resume scheduling after hang recovery */ 250 r = amdgpu_mes_resume(adev, input.xcc_id); 251 } 252 253 return r; 254 } 255 256 static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, 257 struct drm_amdgpu_userq_in *args_in) 258 { 259 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 260 struct amdgpu_device *adev = uq_mgr->adev; 261 struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; 262 struct drm_amdgpu_userq_in *mqd_user = args_in; 263 struct amdgpu_mqd_prop *userq_props; 264 int r; 265 266 /* Structure to initialize MQD for userqueue using generic MQD init function */ 267 userq_props = kzalloc_obj(struct amdgpu_mqd_prop); 268 if (!userq_props) { 269 DRM_ERROR("Failed to allocate memory for userq_props\n"); 270 return -ENOMEM; 271 } 272 273 r = amdgpu_userq_create_object(uq_mgr, &queue->mqd, 274 AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size)); 275 if (r) { 276 DRM_ERROR("Failed to create MQD object for userqueue\n"); 277 goto free_props; 278 } 279 280 /* Initialize the MQD BO with user given values */ 281 userq_props->wptr_gpu_addr = mqd_user->wptr_va; 282 userq_props->rptr_gpu_addr = mqd_user->rptr_va; 283 userq_props->queue_size = mqd_user->queue_size; 284 userq_props->hqd_base_gpu_addr = mqd_user->queue_va; 285 userq_props->mqd_gpu_addr = queue->mqd.gpu_addr; 286 userq_props->use_doorbell = true; 287 userq_props->doorbell_index = queue->doorbell_index; 288 userq_props->fence_address = queue->fence_drv->gpu_addr; 289 290 if (queue->queue_type == AMDGPU_HW_IP_COMPUTE) { 291 struct drm_amdgpu_userq_mqd_compute_gfx11 *compute_mqd; 292 293 if (mqd_user->mqd_size != sizeof(*compute_mqd)) { 294 DRM_ERROR("Invalid compute IP MQD size\n"); 295 r = -EINVAL; 296 goto free_mqd; 297 } 298 299 compute_mqd = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 300 if (IS_ERR(compute_mqd)) { 301 DRM_ERROR("Failed to read user MQD\n"); 302 r = -ENOMEM; 303 goto free_mqd; 304 } 305 306 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 307 if (r) { 308 kfree(compute_mqd); 309 goto free_mqd; 310 } 311 r = amdgpu_userq_input_va_validate(adev, queue, compute_mqd->eop_va, 312 2048); 313 amdgpu_bo_unreserve(queue->vm->root.bo); 314 if (r) { 315 kfree(compute_mqd); 316 goto free_mqd; 317 } 318 319 userq_props->eop_gpu_addr = compute_mqd->eop_va; 320 userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL; 321 userq_props->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM; 322 userq_props->hqd_active = false; 323 userq_props->tmz_queue = 324 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; 325 kfree(compute_mqd); 326 } else if (queue->queue_type == AMDGPU_HW_IP_GFX) { 327 struct drm_amdgpu_userq_mqd_gfx11 *mqd_gfx_v11; 328 struct amdgpu_gfx_shadow_info shadow_info; 329 330 if (adev->gfx.funcs->get_gfx_shadow_info) { 331 adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow_info, true); 332 } else { 333 r = -EINVAL; 334 goto free_mqd; 335 } 336 337 if (mqd_user->mqd_size != sizeof(*mqd_gfx_v11) || !mqd_user->mqd) { 338 DRM_ERROR("Invalid GFX MQD\n"); 339 r = -EINVAL; 340 goto free_mqd; 341 } 342 343 mqd_gfx_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 344 if (IS_ERR(mqd_gfx_v11)) { 345 DRM_ERROR("Failed to read user MQD\n"); 346 r = -ENOMEM; 347 goto free_mqd; 348 } 349 350 userq_props->shadow_addr = mqd_gfx_v11->shadow_va; 351 userq_props->csa_addr = mqd_gfx_v11->csa_va; 352 userq_props->tmz_queue = 353 mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; 354 355 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 356 if (r) { 357 kfree(mqd_gfx_v11); 358 goto free_mqd; 359 } 360 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->shadow_va, 361 shadow_info.shadow_size); 362 if (r) { 363 amdgpu_bo_unreserve(queue->vm->root.bo); 364 kfree(mqd_gfx_v11); 365 goto free_mqd; 366 } 367 368 r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->csa_va, 369 shadow_info.csa_size); 370 amdgpu_bo_unreserve(queue->vm->root.bo); 371 if (r) { 372 kfree(mqd_gfx_v11); 373 goto free_mqd; 374 } 375 376 kfree(mqd_gfx_v11); 377 } else if (queue->queue_type == AMDGPU_HW_IP_DMA) { 378 struct drm_amdgpu_userq_mqd_sdma_gfx11 *mqd_sdma_v11; 379 380 if (mqd_user->mqd_size != sizeof(*mqd_sdma_v11) || !mqd_user->mqd) { 381 DRM_ERROR("Invalid SDMA MQD\n"); 382 r = -EINVAL; 383 goto free_mqd; 384 } 385 386 mqd_sdma_v11 = memdup_user(u64_to_user_ptr(mqd_user->mqd), mqd_user->mqd_size); 387 if (IS_ERR(mqd_sdma_v11)) { 388 DRM_ERROR("Failed to read sdma user MQD\n"); 389 r = -ENOMEM; 390 goto free_mqd; 391 } 392 393 r = amdgpu_bo_reserve(queue->vm->root.bo, false); 394 if (r) { 395 kfree(mqd_sdma_v11); 396 goto free_mqd; 397 } 398 r = amdgpu_userq_input_va_validate(adev, queue, mqd_sdma_v11->csa_va, 399 32); 400 amdgpu_bo_unreserve(queue->vm->root.bo); 401 if (r) { 402 kfree(mqd_sdma_v11); 403 goto free_mqd; 404 } 405 406 userq_props->csa_addr = mqd_sdma_v11->csa_va; 407 kfree(mqd_sdma_v11); 408 } 409 410 queue->userq_prop = userq_props; 411 412 r = mqd_hw_default->init_mqd(adev, (void *)queue->mqd.cpu_ptr, userq_props); 413 if (r) { 414 DRM_ERROR("Failed to initialize MQD for userqueue\n"); 415 goto free_mqd; 416 } 417 418 /* Create BO for FW operations */ 419 r = mes_userq_create_ctx_space(uq_mgr, queue, mqd_user); 420 if (r) { 421 DRM_ERROR("Failed to allocate BO for userqueue (%d)", r); 422 goto free_mqd; 423 } 424 425 /* FW expects WPTR BOs to be mapped into GART */ 426 r = mes_userq_create_wptr_mapping(adev, uq_mgr, queue, userq_props->wptr_gpu_addr); 427 if (r) { 428 DRM_ERROR("Failed to create WPTR mapping\n"); 429 goto free_ctx; 430 } 431 432 return 0; 433 434 free_ctx: 435 amdgpu_userq_destroy_object(uq_mgr, &queue->fw_obj); 436 437 free_mqd: 438 amdgpu_userq_destroy_object(uq_mgr, &queue->mqd); 439 440 free_props: 441 kfree(userq_props); 442 443 return r; 444 } 445 446 static void mes_userq_mqd_destroy(struct amdgpu_usermode_queue *queue) 447 { 448 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 449 450 amdgpu_userq_destroy_object(uq_mgr, &queue->fw_obj); 451 kfree(queue->userq_prop); 452 amdgpu_userq_destroy_object(uq_mgr, &queue->mqd); 453 } 454 455 static int mes_userq_preempt(struct amdgpu_usermode_queue *queue) 456 { 457 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 458 struct amdgpu_device *adev = uq_mgr->adev; 459 struct mes_suspend_gang_input queue_input; 460 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 461 signed long timeout = 2100000; /* 2100 ms */ 462 u64 fence_gpu_addr; 463 u32 fence_offset; 464 u64 *fence_ptr; 465 int i, r; 466 467 if (queue->state != AMDGPU_USERQ_STATE_MAPPED) 468 return 0; 469 r = amdgpu_device_wb_get(adev, &fence_offset); 470 if (r) 471 return r; 472 473 fence_gpu_addr = adev->wb.gpu_addr + (fence_offset * 4); 474 fence_ptr = (u64 *)&adev->wb.wb[fence_offset]; 475 *fence_ptr = 0; 476 477 memset(&queue_input, 0x0, sizeof(struct mes_suspend_gang_input)); 478 queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ; 479 queue_input.suspend_fence_addr = fence_gpu_addr; 480 queue_input.suspend_fence_value = 1; 481 amdgpu_mes_lock(&adev->mes); 482 r = adev->mes.funcs->suspend_gang(&adev->mes, &queue_input); 483 amdgpu_mes_unlock(&adev->mes); 484 if (r) { 485 DRM_ERROR("Failed to suspend gang: %d\n", r); 486 goto out; 487 } 488 489 for (i = 0; i < timeout; i++) { 490 if (*fence_ptr == 1) 491 goto out; 492 udelay(1); 493 } 494 r = -ETIMEDOUT; 495 496 out: 497 amdgpu_device_wb_free(adev, fence_offset); 498 return r; 499 } 500 501 static int mes_userq_restore(struct amdgpu_usermode_queue *queue) 502 { 503 struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; 504 struct amdgpu_device *adev = uq_mgr->adev; 505 struct mes_resume_gang_input queue_input; 506 struct amdgpu_userq_obj *ctx = &queue->fw_obj; 507 int r; 508 509 if (queue->state == AMDGPU_USERQ_STATE_HUNG) 510 return -EINVAL; 511 if (queue->state != AMDGPU_USERQ_STATE_PREEMPTED) 512 return 0; 513 514 memset(&queue_input, 0x0, sizeof(struct mes_resume_gang_input)); 515 queue_input.gang_context_addr = ctx->gpu_addr + AMDGPU_USERQ_PROC_CTX_SZ; 516 517 amdgpu_mes_lock(&adev->mes); 518 r = adev->mes.funcs->resume_gang(&adev->mes, &queue_input); 519 amdgpu_mes_unlock(&adev->mes); 520 if (r) 521 dev_err(adev->dev, "Failed to resume queue, err (%d)\n", r); 522 return r; 523 } 524 525 const struct amdgpu_userq_funcs userq_mes_funcs = { 526 .mqd_create = mes_userq_mqd_create, 527 .mqd_destroy = mes_userq_mqd_destroy, 528 .unmap = mes_userq_unmap, 529 .map = mes_userq_map, 530 .detect_and_reset = mes_userq_detect_and_reset, 531 .preempt = mes_userq_preempt, 532 .restore = mes_userq_restore, 533 }; 534