1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2024 Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v4_0_3.h" 30 #include "jpeg_v5_0_1.h" 31 #include "mmsch_v5_0.h" 32 33 #include "vcn/vcn_5_0_0_offset.h" 34 #include "vcn/vcn_5_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" 36 37 static int jpeg_v5_0_1_start_sriov(struct amdgpu_device *adev); 38 static void jpeg_v5_0_1_set_dec_ring_funcs(struct amdgpu_device *adev); 39 static void jpeg_v5_0_1_set_irq_funcs(struct amdgpu_device *adev); 40 static int jpeg_v5_0_1_set_powergating_state(struct amdgpu_ip_block *ip_block, 41 enum amd_powergating_state state); 42 static void jpeg_v5_0_1_set_ras_funcs(struct amdgpu_device *adev); 43 static void jpeg_v5_0_1_dec_ring_set_wptr(struct amdgpu_ring *ring); 44 45 static int amdgpu_ih_srcid_jpeg[] = { 46 VCN_5_0__SRCID__JPEG_DECODE, 47 VCN_5_0__SRCID__JPEG1_DECODE, 48 VCN_5_0__SRCID__JPEG2_DECODE, 49 VCN_5_0__SRCID__JPEG3_DECODE, 50 VCN_5_0__SRCID__JPEG4_DECODE, 51 VCN_5_0__SRCID__JPEG5_DECODE, 52 VCN_5_0__SRCID__JPEG6_DECODE, 53 VCN_5_0__SRCID__JPEG7_DECODE, 54 VCN_5_0__SRCID__JPEG8_DECODE, 55 VCN_5_0__SRCID__JPEG9_DECODE, 56 }; 57 58 static const struct amdgpu_hwip_reg_entry jpeg_reg_list_5_0_1[] = { 59 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), 60 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), 61 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR), 62 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR), 63 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS), 64 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), 65 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), 66 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), 67 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), 68 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), 69 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), 70 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR), 71 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR), 72 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS), 73 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR), 74 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR), 75 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS), 76 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR), 77 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR), 78 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS), 79 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR), 80 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR), 81 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS), 82 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR), 83 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR), 84 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS), 85 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR), 86 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR), 87 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_STATUS), 88 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR), 89 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR), 90 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS), 91 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_RPTR), 92 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_WPTR), 93 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_STATUS), 94 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_RPTR), 95 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_WPTR), 96 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_STATUS), 97 }; 98 99 static int jpeg_v5_0_1_core_reg_offset(u32 pipe) 100 { 101 if (pipe <= AMDGPU_MAX_JPEG_RINGS_4_0_3) 102 return ((0x40 * pipe) - 0xc80); 103 else 104 return ((0x40 * pipe) - 0x440); 105 } 106 107 /** 108 * jpeg_v5_0_1_early_init - set function pointers 109 * 110 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 111 * 112 * Set ring and irq function pointers 113 */ 114 static int jpeg_v5_0_1_early_init(struct amdgpu_ip_block *ip_block) 115 { 116 struct amdgpu_device *adev = ip_block->adev; 117 118 if (!adev->jpeg.num_jpeg_inst || adev->jpeg.num_jpeg_inst > AMDGPU_MAX_JPEG_INSTANCES) 119 return -ENOENT; 120 121 switch (amdgpu_user_queue) { 122 case -1: 123 case 0: 124 default: 125 adev->jpeg.disable_kq = false; 126 adev->jpeg.disable_uq = true; 127 break; 128 case 2: 129 adev->jpeg.disable_kq = true; 130 adev->jpeg.disable_uq = true; 131 break; 132 } 133 134 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS; 135 jpeg_v5_0_1_set_dec_ring_funcs(adev); 136 jpeg_v5_0_1_set_irq_funcs(adev); 137 jpeg_v5_0_1_set_ras_funcs(adev); 138 139 return 0; 140 } 141 142 /** 143 * jpeg_v5_0_1_sw_init - sw init for JPEG block 144 * 145 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 146 * 147 * Load firmware and sw initialization 148 */ 149 static int jpeg_v5_0_1_sw_init(struct amdgpu_ip_block *ip_block) 150 { 151 struct amdgpu_device *adev = ip_block->adev; 152 struct amdgpu_ring *ring; 153 int i, j, r, jpeg_inst; 154 155 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 156 /* JPEG TRAP */ 157 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 158 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); 159 if (r) 160 return r; 161 } 162 /* JPEG DJPEG POISON EVENT */ 163 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 164 VCN_5_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); 165 if (r) 166 return r; 167 168 /* JPEG EJPEG POISON EVENT */ 169 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 170 VCN_5_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); 171 if (r) 172 return r; 173 174 r = amdgpu_jpeg_sw_init(adev); 175 if (r) 176 return r; 177 178 r = amdgpu_jpeg_resume(adev); 179 if (r) 180 return r; 181 182 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 183 jpeg_inst = GET_INST(JPEG, i); 184 185 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 186 ring = &adev->jpeg.inst[i].ring_dec[j]; 187 ring->use_doorbell = true; 188 if (adev->jpeg.disable_kq) { 189 ring->no_scheduler = true; 190 ring->no_user_submission = true; 191 } 192 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); 193 if (!amdgpu_sriov_vf(adev)) { 194 ring->doorbell_index = 195 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 196 1 + j + 11 * jpeg_inst; 197 } else { 198 ring->doorbell_index = 199 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 200 2 + j + 32 * jpeg_inst; 201 } 202 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); 203 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 204 AMDGPU_RING_PRIO_DEFAULT, NULL); 205 if (r) 206 return r; 207 208 adev->jpeg.internal.jpeg_pitch[j] = 209 regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET; 210 adev->jpeg.inst[i].external.jpeg_pitch[j] = 211 SOC15_REG_OFFSET1(JPEG, jpeg_inst, regUVD_JRBC_SCRATCH0, 212 (j ? jpeg_v5_0_1_core_reg_offset(j) : 0)); 213 } 214 } 215 216 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 217 r = amdgpu_jpeg_ras_sw_init(adev); 218 if (r) { 219 dev_err(adev->dev, "Failed to initialize jpeg ras block!\n"); 220 return r; 221 } 222 } 223 224 r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0_1, ARRAY_SIZE(jpeg_reg_list_5_0_1)); 225 if (r) 226 return r; 227 228 adev->jpeg.supported_reset = 229 amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]); 230 if (!amdgpu_sriov_vf(adev)) 231 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 232 r = amdgpu_jpeg_sysfs_reset_mask_init(adev); 233 234 return r; 235 } 236 237 /** 238 * jpeg_v5_0_1_sw_fini - sw fini for JPEG block 239 * 240 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 241 * 242 * JPEG suspend and free up sw allocation 243 */ 244 static int jpeg_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block) 245 { 246 struct amdgpu_device *adev = ip_block->adev; 247 int r; 248 249 r = amdgpu_jpeg_suspend(adev); 250 if (r) 251 return r; 252 253 amdgpu_jpeg_sysfs_reset_mask_fini(adev); 254 255 r = amdgpu_jpeg_sw_fini(adev); 256 257 return r; 258 } 259 260 /** 261 * jpeg_v5_0_1_hw_init - start and test JPEG block 262 * 263 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 264 * 265 */ 266 static int jpeg_v5_0_1_hw_init(struct amdgpu_ip_block *ip_block) 267 { 268 struct amdgpu_device *adev = ip_block->adev; 269 struct amdgpu_ring *ring; 270 int i, j, r, jpeg_inst; 271 272 if (amdgpu_sriov_vf(adev)) { 273 r = jpeg_v5_0_1_start_sriov(adev); 274 if (r) 275 return r; 276 277 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 278 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 279 ring = &adev->jpeg.inst[i].ring_dec[j]; 280 ring->wptr = 0; 281 ring->wptr_old = 0; 282 jpeg_v5_0_1_dec_ring_set_wptr(ring); 283 ring->sched.ready = true; 284 } 285 } 286 return 0; 287 } 288 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) 289 adev->jpeg.caps |= AMDGPU_JPEG_CAPS(RRMT_ENABLED); 290 291 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 292 jpeg_inst = GET_INST(JPEG, i); 293 ring = adev->jpeg.inst[i].ring_dec; 294 if (ring->use_doorbell) 295 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 296 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 11 * jpeg_inst, 297 adev->jpeg.inst[i].aid_id); 298 299 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 300 ring = &adev->jpeg.inst[i].ring_dec[j]; 301 if (ring->use_doorbell) 302 WREG32_SOC15_OFFSET(VCN, GET_INST(VCN, i), regVCN_JPEG_DB_CTRL, 303 ring->pipe, 304 ring->doorbell_index << 305 VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 306 VCN_JPEG_DB_CTRL__EN_MASK); 307 r = amdgpu_ring_test_helper(ring); 308 if (r) 309 return r; 310 } 311 } 312 313 return 0; 314 } 315 316 /** 317 * jpeg_v5_0_1_hw_fini - stop the hardware block 318 * 319 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 320 * 321 * Stop the JPEG block, mark ring as not ready any more 322 */ 323 static int jpeg_v5_0_1_hw_fini(struct amdgpu_ip_block *ip_block) 324 { 325 struct amdgpu_device *adev = ip_block->adev; 326 int ret = 0; 327 328 cancel_delayed_work_sync(&adev->jpeg.idle_work); 329 330 if (!amdgpu_sriov_vf(adev)) { 331 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) 332 ret = jpeg_v5_0_1_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 333 } 334 335 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG) && !amdgpu_sriov_vf(adev)) 336 amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0); 337 338 return ret; 339 } 340 341 /** 342 * jpeg_v5_0_1_suspend - suspend JPEG block 343 * 344 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 345 * 346 * HW fini and suspend JPEG block 347 */ 348 static int jpeg_v5_0_1_suspend(struct amdgpu_ip_block *ip_block) 349 { 350 struct amdgpu_device *adev = ip_block->adev; 351 int r; 352 353 r = jpeg_v5_0_1_hw_fini(ip_block); 354 if (r) 355 return r; 356 357 r = amdgpu_jpeg_suspend(adev); 358 359 return r; 360 } 361 362 /** 363 * jpeg_v5_0_1_resume - resume JPEG block 364 * 365 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 366 * 367 * Resume firmware and hw init JPEG block 368 */ 369 static int jpeg_v5_0_1_resume(struct amdgpu_ip_block *ip_block) 370 { 371 struct amdgpu_device *adev = ip_block->adev; 372 int r; 373 374 r = amdgpu_jpeg_resume(adev); 375 if (r) 376 return r; 377 378 r = jpeg_v5_0_1_hw_init(ip_block); 379 380 return r; 381 } 382 383 static void jpeg_v5_0_1_init_inst(struct amdgpu_device *adev, int i) 384 { 385 int jpeg_inst = GET_INST(JPEG, i); 386 387 /* disable anti hang mechanism */ 388 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0, 389 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 390 391 /* keep the JPEG in static PG mode */ 392 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0, 393 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); 394 395 /* MJPEG global tiling registers */ 396 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, 397 adev->gfx.config.gb_addr_config); 398 399 /* enable JMI channel */ 400 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0, 401 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 402 } 403 404 static void jpeg_v5_0_1_deinit_inst(struct amdgpu_device *adev, int i) 405 { 406 int jpeg_inst = GET_INST(JPEG, i); 407 /* reset JMI */ 408 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 409 UVD_JMI_CNTL__SOFT_RESET_MASK, 410 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 411 412 /* enable anti hang mechanism */ 413 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 414 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 415 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 416 } 417 418 static void jpeg_v5_0_1_init_jrbc(struct amdgpu_ring *ring) 419 { 420 struct amdgpu_device *adev = ring->adev; 421 u32 reg, data, mask; 422 int jpeg_inst = GET_INST(JPEG, ring->me); 423 int reg_offset = ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0; 424 425 /* enable System Interrupt for JRBC */ 426 reg = SOC15_REG_OFFSET(JPEG, jpeg_inst, regJPEG_SYS_INT_EN); 427 if (ring->pipe < AMDGPU_MAX_JPEG_RINGS_4_0_3) { 428 data = JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe; 429 mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe); 430 WREG32_P(reg, data, mask); 431 } else { 432 data = JPEG_SYS_INT_EN__DJRBC0_MASK << (ring->pipe+12); 433 mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << (ring->pipe+12)); 434 WREG32_P(reg, data, mask); 435 } 436 437 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 438 regUVD_LMI_JRBC_RB_VMID, 439 reg_offset, 0); 440 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 441 regUVD_JRBC_RB_CNTL, 442 reg_offset, 443 (0x00000001L | 0x00000002L)); 444 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 445 regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 446 reg_offset, lower_32_bits(ring->gpu_addr)); 447 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 448 regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 449 reg_offset, upper_32_bits(ring->gpu_addr)); 450 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 451 regUVD_JRBC_RB_RPTR, 452 reg_offset, 0); 453 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 454 regUVD_JRBC_RB_WPTR, 455 reg_offset, 0); 456 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 457 regUVD_JRBC_RB_CNTL, 458 reg_offset, 0x00000002L); 459 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 460 regUVD_JRBC_RB_SIZE, 461 reg_offset, ring->ring_size / 4); 462 ring->wptr = RREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JRBC_RB_WPTR, 463 reg_offset); 464 } 465 466 static int jpeg_v5_0_1_start_sriov(struct amdgpu_device *adev) 467 { 468 struct amdgpu_ring *ring; 469 uint64_t ctx_addr; 470 uint32_t param, resp, expected; 471 uint32_t tmp, timeout; 472 473 struct amdgpu_mm_table *table = &adev->virt.mm_table; 474 uint32_t *table_loc; 475 uint32_t table_size; 476 uint32_t size, size_dw, item_offset; 477 uint32_t init_status; 478 int i, j, jpeg_inst; 479 480 struct mmsch_v5_0_cmd_direct_write 481 direct_wt = { {0} }; 482 struct mmsch_v5_0_cmd_end end = { {0} }; 483 struct mmsch_v5_0_init_header header; 484 485 direct_wt.cmd_header.command_type = 486 MMSCH_COMMAND__DIRECT_REG_WRITE; 487 end.cmd_header.command_type = 488 MMSCH_COMMAND__END; 489 490 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 491 jpeg_inst = GET_INST(JPEG, i); 492 493 memset(&header, 0, sizeof(struct mmsch_v5_0_init_header)); 494 header.version = MMSCH_VERSION; 495 header.total_size = sizeof(struct mmsch_v5_0_init_header) >> 2; 496 497 table_loc = (uint32_t *)table->cpu_addr; 498 table_loc += header.total_size; 499 500 item_offset = header.total_size; 501 502 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) { 503 ring = &adev->jpeg.inst[i].ring_dec[j]; 504 table_size = 0; 505 506 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW); 507 MMSCH_V5_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr)); 508 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH); 509 MMSCH_V5_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr)); 510 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC_RB_SIZE); 511 MMSCH_V5_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4); 512 513 if (j < 5) { 514 header.mjpegdec0[j].table_offset = item_offset; 515 header.mjpegdec0[j].init_status = 0; 516 header.mjpegdec0[j].table_size = table_size; 517 } else { 518 header.mjpegdec1[j - 5].table_offset = item_offset; 519 header.mjpegdec1[j - 5].init_status = 0; 520 header.mjpegdec1[j - 5].table_size = table_size; 521 } 522 header.total_size += table_size; 523 item_offset += table_size; 524 } 525 526 MMSCH_V5_0_INSERT_END(); 527 528 /* send init table to MMSCH */ 529 size = sizeof(struct mmsch_v5_0_init_header); 530 table_loc = (uint32_t *)table->cpu_addr; 531 memcpy((void *)table_loc, &header, size); 532 533 ctx_addr = table->gpu_addr; 534 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 535 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 536 537 tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID); 538 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 539 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 540 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp); 541 542 size = header.total_size; 543 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size); 544 545 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0); 546 547 param = 0x00000001; 548 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param); 549 tmp = 0; 550 timeout = 1000; 551 resp = 0; 552 expected = MMSCH_VF_MAILBOX_RESP__OK; 553 init_status = 554 ((struct mmsch_v5_0_init_header *)(table_loc))->mjpegdec0[i].init_status; 555 while (resp != expected) { 556 resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP); 557 558 if (resp != 0) 559 break; 560 udelay(10); 561 tmp = tmp + 10; 562 if (tmp >= timeout) { 563 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 564 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 565 "(expected=0x%08x, readback=0x%08x)\n", 566 tmp, expected, resp); 567 return -EBUSY; 568 } 569 } 570 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE && 571 init_status != MMSCH_VF_ENGINE_STATUS__PASS) 572 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", 573 resp, init_status); 574 575 } 576 return 0; 577 } 578 579 /** 580 * jpeg_v5_0_1_start - start JPEG block 581 * 582 * @adev: amdgpu_device pointer 583 * 584 * Setup and start the JPEG block 585 */ 586 static int jpeg_v5_0_1_start(struct amdgpu_device *adev) 587 { 588 struct amdgpu_ring *ring; 589 int i, j; 590 591 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 592 jpeg_v5_0_1_init_inst(adev, i); 593 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 594 ring = &adev->jpeg.inst[i].ring_dec[j]; 595 jpeg_v5_0_1_init_jrbc(ring); 596 } 597 } 598 599 return 0; 600 } 601 602 /** 603 * jpeg_v5_0_1_stop - stop JPEG block 604 * 605 * @adev: amdgpu_device pointer 606 * 607 * stop the JPEG block 608 */ 609 static int jpeg_v5_0_1_stop(struct amdgpu_device *adev) 610 { 611 int i; 612 613 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) 614 jpeg_v5_0_1_deinit_inst(adev, i); 615 616 return 0; 617 } 618 619 /** 620 * jpeg_v5_0_1_dec_ring_get_rptr - get read pointer 621 * 622 * @ring: amdgpu_ring pointer 623 * 624 * Returns the current hardware read pointer 625 */ 626 static uint64_t jpeg_v5_0_1_dec_ring_get_rptr(struct amdgpu_ring *ring) 627 { 628 struct amdgpu_device *adev = ring->adev; 629 630 return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_RPTR, 631 ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0); 632 } 633 634 /** 635 * jpeg_v5_0_1_dec_ring_get_wptr - get write pointer 636 * 637 * @ring: amdgpu_ring pointer 638 * 639 * Returns the current hardware write pointer 640 */ 641 static uint64_t jpeg_v5_0_1_dec_ring_get_wptr(struct amdgpu_ring *ring) 642 { 643 struct amdgpu_device *adev = ring->adev; 644 645 if (ring->use_doorbell) 646 return adev->wb.wb[ring->wptr_offs]; 647 648 return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_WPTR, 649 ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0); 650 } 651 652 /** 653 * jpeg_v5_0_1_dec_ring_set_wptr - set write pointer 654 * 655 * @ring: amdgpu_ring pointer 656 * 657 * Commits the write pointer to the hardware 658 */ 659 static void jpeg_v5_0_1_dec_ring_set_wptr(struct amdgpu_ring *ring) 660 { 661 struct amdgpu_device *adev = ring->adev; 662 663 if (ring->use_doorbell) { 664 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 665 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 666 } else { 667 WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), 668 regUVD_JRBC_RB_WPTR, 669 (ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0), 670 lower_32_bits(ring->wptr)); 671 } 672 } 673 674 static bool jpeg_v5_0_1_is_idle(struct amdgpu_ip_block *ip_block) 675 { 676 struct amdgpu_device *adev = ip_block->adev; 677 bool ret = true; 678 int i, j; 679 680 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 681 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 682 int reg_offset = (j ? jpeg_v5_0_1_core_reg_offset(j) : 0); 683 684 ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i), 685 regUVD_JRBC_STATUS, reg_offset) & 686 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 687 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 688 } 689 } 690 691 return ret; 692 } 693 694 static int jpeg_v5_0_1_wait_for_idle(struct amdgpu_ip_block *ip_block) 695 { 696 struct amdgpu_device *adev = ip_block->adev; 697 int ret = 0; 698 int i, j; 699 700 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 701 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 702 int reg_offset = (j ? jpeg_v5_0_1_core_reg_offset(j) : 0); 703 704 ret &= SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i), 705 regUVD_JRBC_STATUS, reg_offset, 706 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 707 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 708 } 709 } 710 return ret; 711 } 712 713 static int jpeg_v5_0_1_set_clockgating_state(struct amdgpu_ip_block *ip_block, 714 enum amd_clockgating_state state) 715 { 716 struct amdgpu_device *adev = ip_block->adev; 717 bool enable = state == AMD_CG_STATE_GATE; 718 719 int i; 720 721 if (!enable) 722 return 0; 723 724 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 725 if (!jpeg_v5_0_1_is_idle(ip_block)) 726 return -EBUSY; 727 } 728 729 return 0; 730 } 731 732 static int jpeg_v5_0_1_set_powergating_state(struct amdgpu_ip_block *ip_block, 733 enum amd_powergating_state state) 734 { 735 struct amdgpu_device *adev = ip_block->adev; 736 int ret; 737 738 if (amdgpu_sriov_vf(adev)) { 739 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; 740 return 0; 741 } 742 743 if (state == adev->jpeg.cur_state) 744 return 0; 745 746 if (state == AMD_PG_STATE_GATE) 747 ret = jpeg_v5_0_1_stop(adev); 748 else 749 ret = jpeg_v5_0_1_start(adev); 750 751 if (!ret) 752 adev->jpeg.cur_state = state; 753 754 return ret; 755 } 756 757 static int jpeg_v5_0_1_set_interrupt_state(struct amdgpu_device *adev, 758 struct amdgpu_irq_src *source, 759 unsigned int type, 760 enum amdgpu_interrupt_state state) 761 { 762 return 0; 763 } 764 765 static int jpeg_v5_0_1_set_ras_interrupt_state(struct amdgpu_device *adev, 766 struct amdgpu_irq_src *source, 767 unsigned int type, 768 enum amdgpu_interrupt_state state) 769 { 770 return 0; 771 } 772 773 774 775 int jpeg_v5_0_1_process_interrupt(struct amdgpu_device *adev, 776 struct amdgpu_irq_src *source, 777 struct amdgpu_iv_entry *entry) 778 { 779 u32 i, inst; 780 781 i = node_id_to_phys_map[entry->node_id]; 782 DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n"); 783 784 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) 785 if (adev->jpeg.inst[inst].aid_id == i) 786 break; 787 788 if (inst >= adev->jpeg.num_jpeg_inst) { 789 dev_WARN_ONCE(adev->dev, 1, 790 "Interrupt received for unknown JPEG instance %d", 791 entry->node_id); 792 return 0; 793 } 794 795 switch (entry->src_id) { 796 case VCN_5_0__SRCID__JPEG_DECODE: 797 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); 798 break; 799 case VCN_5_0__SRCID__JPEG1_DECODE: 800 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]); 801 break; 802 case VCN_5_0__SRCID__JPEG2_DECODE: 803 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]); 804 break; 805 case VCN_5_0__SRCID__JPEG3_DECODE: 806 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]); 807 break; 808 case VCN_5_0__SRCID__JPEG4_DECODE: 809 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]); 810 break; 811 case VCN_5_0__SRCID__JPEG5_DECODE: 812 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]); 813 break; 814 case VCN_5_0__SRCID__JPEG6_DECODE: 815 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]); 816 break; 817 case VCN_5_0__SRCID__JPEG7_DECODE: 818 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]); 819 break; 820 case VCN_5_0__SRCID__JPEG8_DECODE: 821 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[8]); 822 break; 823 case VCN_5_0__SRCID__JPEG9_DECODE: 824 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[9]); 825 break; 826 default: 827 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 828 entry->src_id, entry->src_data[0]); 829 break; 830 } 831 832 return 0; 833 } 834 835 static void jpeg_v5_0_1_core_stall_reset(struct amdgpu_ring *ring) 836 { 837 struct amdgpu_device *adev = ring->adev; 838 int jpeg_inst = GET_INST(JPEG, ring->me); 839 int reg_offset = ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0; 840 841 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 842 regUVD_JMI0_UVD_JMI_CLIENT_STALL, 843 reg_offset, 0x1F); 844 SOC15_WAIT_ON_RREG_OFFSET(JPEG, jpeg_inst, 845 regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS, 846 reg_offset, 0x1F, 0x1F); 847 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 848 regUVD_JMI0_JPEG_LMI_DROP, 849 reg_offset, 0x1F); 850 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 1 << ring->pipe); 851 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 852 regUVD_JMI0_UVD_JMI_CLIENT_STALL, 853 reg_offset, 0x00); 854 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 855 regUVD_JMI0_JPEG_LMI_DROP, 856 reg_offset, 0x00); 857 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 0x00); 858 } 859 860 static int jpeg_v5_0_1_ring_reset(struct amdgpu_ring *ring, 861 unsigned int vmid, 862 struct amdgpu_fence *timedout_fence) 863 { 864 struct amdgpu_device *adev = ring->adev; 865 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 866 int r; 867 868 /* take the vcn reset mutex here because resetting VCN will reset jpeg as well */ 869 mutex_lock(&vinst->engine_reset_mutex); 870 871 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 872 jpeg_v5_0_1_core_stall_reset(ring); 873 jpeg_v5_0_1_init_jrbc(ring); 874 r = amdgpu_ring_reset_helper_end(ring, timedout_fence); 875 mutex_unlock(&vinst->engine_reset_mutex); 876 return r; 877 } 878 879 static const struct amd_ip_funcs jpeg_v5_0_1_ip_funcs = { 880 .name = "jpeg_v5_0_1", 881 .early_init = jpeg_v5_0_1_early_init, 882 .late_init = NULL, 883 .sw_init = jpeg_v5_0_1_sw_init, 884 .sw_fini = jpeg_v5_0_1_sw_fini, 885 .hw_init = jpeg_v5_0_1_hw_init, 886 .hw_fini = jpeg_v5_0_1_hw_fini, 887 .suspend = jpeg_v5_0_1_suspend, 888 .resume = jpeg_v5_0_1_resume, 889 .is_idle = jpeg_v5_0_1_is_idle, 890 .wait_for_idle = jpeg_v5_0_1_wait_for_idle, 891 .soft_reset = NULL, 892 .set_clockgating_state = jpeg_v5_0_1_set_clockgating_state, 893 .set_powergating_state = jpeg_v5_0_1_set_powergating_state, 894 .dump_ip_state = amdgpu_jpeg_dump_ip_state, 895 .print_ip_state = amdgpu_jpeg_print_ip_state, 896 }; 897 898 static const struct amdgpu_ring_funcs jpeg_v5_0_1_dec_ring_vm_funcs = { 899 .type = AMDGPU_RING_TYPE_VCN_JPEG, 900 .align_mask = 0xf, 901 .no_user_fence = true, 902 .get_rptr = jpeg_v5_0_1_dec_ring_get_rptr, 903 .get_wptr = jpeg_v5_0_1_dec_ring_get_wptr, 904 .set_wptr = jpeg_v5_0_1_dec_ring_set_wptr, 905 .parse_cs = amdgpu_jpeg_dec_parse_cs, 906 .emit_frame_size = 907 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 908 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 909 8 + /* jpeg_v5_0_1_dec_ring_emit_vm_flush */ 910 22 + 22 + /* jpeg_v5_0_1_dec_ring_emit_fence x2 vm fence */ 911 8 + 16, 912 .emit_ib_size = 22, /* jpeg_v5_0_1_dec_ring_emit_ib */ 913 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, 914 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, 915 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, 916 .emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush, 917 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 918 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 919 .insert_nop = jpeg_v4_0_3_dec_ring_nop, 920 .insert_start = jpeg_v4_0_3_dec_ring_insert_start, 921 .insert_end = jpeg_v4_0_3_dec_ring_insert_end, 922 .pad_ib = amdgpu_ring_generic_pad_ib, 923 .begin_use = amdgpu_jpeg_ring_begin_use, 924 .end_use = amdgpu_jpeg_ring_end_use, 925 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, 926 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, 927 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 928 .reset = jpeg_v5_0_1_ring_reset, 929 }; 930 931 static void jpeg_v5_0_1_set_dec_ring_funcs(struct amdgpu_device *adev) 932 { 933 int i, j, jpeg_inst; 934 935 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 936 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 937 adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v5_0_1_dec_ring_vm_funcs; 938 adev->jpeg.inst[i].ring_dec[j].me = i; 939 adev->jpeg.inst[i].ring_dec[j].pipe = j; 940 } 941 jpeg_inst = GET_INST(JPEG, i); 942 adev->jpeg.inst[i].aid_id = 943 jpeg_inst / adev->jpeg.num_inst_per_aid; 944 } 945 } 946 947 static const struct amdgpu_irq_src_funcs jpeg_v5_0_1_irq_funcs = { 948 .set = jpeg_v5_0_1_set_interrupt_state, 949 .process = jpeg_v5_0_1_process_interrupt, 950 }; 951 952 static const struct amdgpu_irq_src_funcs jpeg_v5_0_1_ras_irq_funcs = { 953 .set = jpeg_v5_0_1_set_ras_interrupt_state, 954 .process = amdgpu_jpeg_process_poison_irq, 955 }; 956 957 static void jpeg_v5_0_1_set_irq_funcs(struct amdgpu_device *adev) 958 { 959 int i; 960 961 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) 962 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; 963 964 adev->jpeg.inst->irq.funcs = &jpeg_v5_0_1_irq_funcs; 965 966 adev->jpeg.inst->ras_poison_irq.num_types = 1; 967 adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v5_0_1_ras_irq_funcs; 968 969 } 970 971 const struct amdgpu_ip_block_version jpeg_v5_0_1_ip_block = { 972 .type = AMD_IP_BLOCK_TYPE_JPEG, 973 .major = 5, 974 .minor = 0, 975 .rev = 1, 976 .funcs = &jpeg_v5_0_1_ip_funcs, 977 }; 978 979 static uint32_t jpeg_v5_0_1_query_poison_by_instance(struct amdgpu_device *adev, 980 uint32_t instance, uint32_t sub_block) 981 { 982 uint32_t poison_stat = 0, reg_value = 0; 983 984 switch (sub_block) { 985 case AMDGPU_JPEG_V5_0_1_JPEG0: 986 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS); 987 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF); 988 break; 989 case AMDGPU_JPEG_V5_0_1_JPEG1: 990 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS); 991 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF); 992 break; 993 default: 994 break; 995 } 996 997 if (poison_stat) 998 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", 999 instance, sub_block); 1000 1001 return poison_stat; 1002 } 1003 1004 static bool jpeg_v5_0_1_query_ras_poison_status(struct amdgpu_device *adev) 1005 { 1006 uint32_t inst = 0, sub = 0, poison_stat = 0; 1007 1008 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) 1009 for (sub = 0; sub < AMDGPU_JPEG_V5_0_1_MAX_SUB_BLOCK; sub++) 1010 poison_stat += 1011 jpeg_v5_0_1_query_poison_by_instance(adev, inst, sub); 1012 1013 return !!poison_stat; 1014 } 1015 1016 static const struct amdgpu_ras_block_hw_ops jpeg_v5_0_1_ras_hw_ops = { 1017 .query_poison_status = jpeg_v5_0_1_query_ras_poison_status, 1018 }; 1019 1020 static int jpeg_v5_0_1_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1021 { 1022 int r; 1023 1024 r = amdgpu_ras_block_late_init(adev, ras_block); 1025 if (r) 1026 return r; 1027 1028 if (amdgpu_ras_is_supported(adev, ras_block->block) && 1029 adev->jpeg.inst->ras_poison_irq.funcs) { 1030 r = amdgpu_irq_get(adev, &adev->jpeg.inst->ras_poison_irq, 0); 1031 if (r) 1032 goto late_fini; 1033 } 1034 1035 return 0; 1036 1037 late_fini: 1038 amdgpu_ras_block_late_fini(adev, ras_block); 1039 1040 return r; 1041 } 1042 1043 static struct amdgpu_jpeg_ras jpeg_v5_0_1_ras = { 1044 .ras_block = { 1045 .hw_ops = &jpeg_v5_0_1_ras_hw_ops, 1046 .ras_late_init = jpeg_v5_0_1_ras_late_init, 1047 }, 1048 }; 1049 1050 static void jpeg_v5_0_1_set_ras_funcs(struct amdgpu_device *adev) 1051 { 1052 adev->jpeg.ras = &jpeg_v5_0_1_ras; 1053 } 1054