1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v2_0.h" 30 #include "jpeg_v4_0_3.h" 31 32 #include "vcn/vcn_5_0_0_offset.h" 33 #include "vcn/vcn_5_0_0_sh_mask.h" 34 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 35 #include "jpeg_v5_0_0.h" 36 37 static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev); 38 static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev); 39 static int jpeg_v5_0_0_set_powergating_state(void *handle, 40 enum amd_powergating_state state); 41 42 /** 43 * jpeg_v5_0_0_early_init - set function pointers 44 * 45 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 46 * 47 * Set ring and irq function pointers 48 */ 49 static int jpeg_v5_0_0_early_init(struct amdgpu_ip_block *ip_block) 50 { 51 struct amdgpu_device *adev = ip_block->adev; 52 53 adev->jpeg.num_jpeg_inst = 1; 54 adev->jpeg.num_jpeg_rings = 1; 55 56 jpeg_v5_0_0_set_dec_ring_funcs(adev); 57 jpeg_v5_0_0_set_irq_funcs(adev); 58 59 return 0; 60 } 61 62 /** 63 * jpeg_v5_0_0_sw_init - sw init for JPEG block 64 * 65 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 66 * 67 * Load firmware and sw initialization 68 */ 69 static int jpeg_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block) 70 { 71 struct amdgpu_device *adev = ip_block->adev; 72 struct amdgpu_ring *ring; 73 int r; 74 75 /* JPEG TRAP */ 76 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 77 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 78 if (r) 79 return r; 80 81 r = amdgpu_jpeg_sw_init(adev); 82 if (r) 83 return r; 84 85 r = amdgpu_jpeg_resume(adev); 86 if (r) 87 return r; 88 89 ring = adev->jpeg.inst->ring_dec; 90 ring->use_doorbell = true; 91 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 92 ring->vm_hub = AMDGPU_MMHUB0(0); 93 94 sprintf(ring->name, "jpeg_dec"); 95 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 96 AMDGPU_RING_PRIO_DEFAULT, NULL); 97 if (r) 98 return r; 99 100 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; 101 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); 102 103 return 0; 104 } 105 106 /** 107 * jpeg_v5_0_0_sw_fini - sw fini for JPEG block 108 * 109 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 110 * 111 * JPEG suspend and free up sw allocation 112 */ 113 static int jpeg_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block) 114 { 115 struct amdgpu_device *adev = ip_block->adev; 116 int r; 117 118 r = amdgpu_jpeg_suspend(adev); 119 if (r) 120 return r; 121 122 r = amdgpu_jpeg_sw_fini(adev); 123 124 return r; 125 } 126 127 /** 128 * jpeg_v5_0_0_hw_init - start and test JPEG block 129 * 130 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 131 * 132 */ 133 static int jpeg_v5_0_0_hw_init(struct amdgpu_ip_block *ip_block) 134 { 135 struct amdgpu_device *adev = ip_block->adev; 136 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 137 int r; 138 139 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 140 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 141 142 /* Skip ring test because pause DPG is not implemented. */ 143 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) 144 return 0; 145 146 r = amdgpu_ring_test_helper(ring); 147 if (r) 148 return r; 149 150 return 0; 151 } 152 153 /** 154 * jpeg_v5_0_0_hw_fini - stop the hardware block 155 * 156 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 157 * 158 * Stop the JPEG block, mark ring as not ready any more 159 */ 160 static int jpeg_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block) 161 { 162 struct amdgpu_device *adev = ip_block->adev; 163 164 cancel_delayed_work_sync(&adev->vcn.idle_work); 165 166 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 167 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS)) 168 jpeg_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 169 170 return 0; 171 } 172 173 /** 174 * jpeg_v5_0_0_suspend - suspend JPEG block 175 * 176 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 177 * 178 * HW fini and suspend JPEG block 179 */ 180 static int jpeg_v5_0_0_suspend(struct amdgpu_ip_block *ip_block) 181 { 182 int r; 183 184 r = jpeg_v5_0_0_hw_fini(ip_block); 185 if (r) 186 return r; 187 188 r = amdgpu_jpeg_suspend(ip_block->adev); 189 190 return r; 191 } 192 193 /** 194 * jpeg_v5_0_0_resume - resume JPEG block 195 * 196 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 197 * 198 * Resume firmware and hw init JPEG block 199 */ 200 static int jpeg_v5_0_0_resume(struct amdgpu_ip_block *ip_block) 201 { 202 int r; 203 204 r = amdgpu_jpeg_resume(ip_block->adev); 205 if (r) 206 return r; 207 208 r = jpeg_v5_0_0_hw_init(ip_block); 209 210 return r; 211 } 212 213 static void jpeg_v5_0_0_disable_clock_gating(struct amdgpu_device *adev) 214 { 215 uint32_t data = 0; 216 217 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 218 219 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 220 data &= ~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK 221 | JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK); 222 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 223 } 224 225 static void jpeg_v5_0_0_enable_clock_gating(struct amdgpu_device *adev) 226 { 227 uint32_t data = 0; 228 229 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 230 231 data |= 1 << JPEG_CGC_CTRL__JPEG0_DEC_MODE__SHIFT; 232 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 233 234 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 235 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK 236 |JPEG_CGC_GATE__JPEG_ENC_MASK 237 |JPEG_CGC_GATE__JMCIF_MASK 238 |JPEG_CGC_GATE__JRBBM_MASK); 239 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 240 } 241 242 static int jpeg_v5_0_0_disable_power_gating(struct amdgpu_device *adev) 243 { 244 uint32_t data = 0; 245 246 data = 1 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT; 247 WREG32_SOC15(JPEG, 0, regUVD_IPX_DLDO_CONFIG, data); 248 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, 0, 249 UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK); 250 251 /* disable anti hang mechanism */ 252 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 253 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 254 255 return 0; 256 } 257 258 static int jpeg_v5_0_0_enable_power_gating(struct amdgpu_device *adev) 259 { 260 /* enable anti hang mechanism */ 261 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 262 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 263 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 264 265 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 266 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG), 267 2 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT); 268 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, 269 1 << UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT, 270 UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK); 271 } 272 273 return 0; 274 } 275 276 static void jpeg_engine_5_0_0_dpg_clock_gating_mode(struct amdgpu_device *adev, 277 int inst_idx, uint8_t indirect) 278 { 279 uint32_t data = 0; 280 281 // JPEG disable CGC 282 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 283 data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 284 else 285 data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 286 287 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 288 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 289 290 if (indirect) { 291 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); 292 293 // Turn on All JPEG clocks 294 data = 0; 295 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); 296 } else { 297 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); 298 299 // Turn on All JPEG clocks 300 data = 0; 301 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); 302 } 303 } 304 305 /** 306 * jpeg_v5_0_0_start_dpg_mode - Jpeg start with dpg mode 307 * 308 * @adev: amdgpu_device pointer 309 * @inst_idx: instance number index 310 * @indirect: indirectly write sram 311 * 312 * Start JPEG block with dpg mode 313 */ 314 static int jpeg_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 315 { 316 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; 317 uint32_t reg_data = 0; 318 319 jpeg_v5_0_0_enable_power_gating(adev); 320 321 // enable dynamic power gating mode 322 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); 323 reg_data |= UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK; 324 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); 325 326 if (indirect) 327 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr = 328 (uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr; 329 330 jpeg_engine_5_0_0_dpg_clock_gating_mode(adev, inst_idx, indirect); 331 332 /* MJPEG global tiling registers */ 333 if (indirect) 334 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_DEC_GFX10_ADDR_CONFIG, 335 adev->gfx.config.gb_addr_config, indirect); 336 else 337 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_DEC_GFX10_ADDR_CONFIG, 338 adev->gfx.config.gb_addr_config, 1); 339 340 /* enable System Interrupt for JRBC */ 341 if (indirect) 342 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_SYS_INT_EN, 343 JPEG_SYS_INT_EN__DJRBC0_MASK, indirect); 344 else 345 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_SYS_INT_EN, 346 JPEG_SYS_INT_EN__DJRBC0_MASK, 1); 347 348 if (indirect) { 349 /* add nop to workaround PSP size check */ 350 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipUVD_NO_OP, 0, indirect); 351 352 amdgpu_jpeg_psp_update_sram(adev, inst_idx, 0); 353 } 354 355 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL, 356 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 357 VCN_JPEG_DB_CTRL__EN_MASK); 358 359 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_VMID, 0); 360 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 361 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 362 lower_32_bits(ring->gpu_addr)); 363 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 364 upper_32_bits(ring->gpu_addr)); 365 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_RPTR, 0); 366 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR, 0); 367 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, 0x00000002L); 368 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); 369 ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR); 370 371 return 0; 372 } 373 374 /** 375 * jpeg_v5_0_0_stop_dpg_mode - Jpeg stop with dpg mode 376 * 377 * @adev: amdgpu_device pointer 378 * @inst_idx: instance number index 379 * 380 * Stop JPEG block with dpg mode 381 */ 382 static void jpeg_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 383 { 384 uint32_t reg_data = 0; 385 386 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); 387 reg_data &= ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK; 388 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); 389 } 390 391 /** 392 * jpeg_v5_0_0_start - start JPEG block 393 * 394 * @adev: amdgpu_device pointer 395 * 396 * Setup and start the JPEG block 397 */ 398 static int jpeg_v5_0_0_start(struct amdgpu_device *adev) 399 { 400 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 401 int r; 402 403 if (adev->pm.dpm_enabled) 404 amdgpu_dpm_enable_jpeg(adev, true); 405 406 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) { 407 r = jpeg_v5_0_0_start_dpg_mode(adev, 0, adev->jpeg.indirect_sram); 408 return r; 409 } 410 411 /* disable power gating */ 412 r = jpeg_v5_0_0_disable_power_gating(adev); 413 if (r) 414 return r; 415 416 /* JPEG disable CGC */ 417 jpeg_v5_0_0_disable_clock_gating(adev); 418 419 /* MJPEG global tiling registers */ 420 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, 421 adev->gfx.config.gb_addr_config); 422 423 /* enable JMI channel */ 424 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0, 425 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 426 427 /* enable System Interrupt for JRBC */ 428 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN), 429 JPEG_SYS_INT_EN__DJRBC0_MASK, 430 ~JPEG_SYS_INT_EN__DJRBC0_MASK); 431 432 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL, 433 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 434 VCN_JPEG_DB_CTRL__EN_MASK); 435 436 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0); 437 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 438 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 439 lower_32_bits(ring->gpu_addr)); 440 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 441 upper_32_bits(ring->gpu_addr)); 442 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0); 443 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0); 444 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L); 445 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); 446 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 447 448 return 0; 449 } 450 451 /** 452 * jpeg_v5_0_0_stop - stop JPEG block 453 * 454 * @adev: amdgpu_device pointer 455 * 456 * stop the JPEG block 457 */ 458 static int jpeg_v5_0_0_stop(struct amdgpu_device *adev) 459 { 460 int r; 461 462 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) { 463 jpeg_v5_0_0_stop_dpg_mode(adev, 0); 464 } else { 465 466 /* reset JMI */ 467 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 468 UVD_JMI_CNTL__SOFT_RESET_MASK, 469 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 470 471 jpeg_v5_0_0_enable_clock_gating(adev); 472 473 /* enable power gating */ 474 r = jpeg_v5_0_0_enable_power_gating(adev); 475 if (r) 476 return r; 477 } 478 479 if (adev->pm.dpm_enabled) 480 amdgpu_dpm_enable_jpeg(adev, false); 481 482 return 0; 483 } 484 485 /** 486 * jpeg_v5_0_0_dec_ring_get_rptr - get read pointer 487 * 488 * @ring: amdgpu_ring pointer 489 * 490 * Returns the current hardware read pointer 491 */ 492 static uint64_t jpeg_v5_0_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 493 { 494 struct amdgpu_device *adev = ring->adev; 495 496 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR); 497 } 498 499 /** 500 * jpeg_v5_0_0_dec_ring_get_wptr - get write pointer 501 * 502 * @ring: amdgpu_ring pointer 503 * 504 * Returns the current hardware write pointer 505 */ 506 static uint64_t jpeg_v5_0_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 507 { 508 struct amdgpu_device *adev = ring->adev; 509 510 if (ring->use_doorbell) 511 return *ring->wptr_cpu_addr; 512 else 513 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 514 } 515 516 /** 517 * jpeg_v5_0_0_dec_ring_set_wptr - set write pointer 518 * 519 * @ring: amdgpu_ring pointer 520 * 521 * Commits the write pointer to the hardware 522 */ 523 static void jpeg_v5_0_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 524 { 525 struct amdgpu_device *adev = ring->adev; 526 527 if (ring->use_doorbell) { 528 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 529 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 530 } else { 531 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 532 } 533 } 534 535 static bool jpeg_v5_0_0_is_idle(void *handle) 536 { 537 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 538 int ret = 1; 539 540 ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) & 541 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 542 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 543 544 return ret; 545 } 546 547 static int jpeg_v5_0_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 548 { 549 struct amdgpu_device *adev = ip_block->adev; 550 551 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, 552 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 553 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 554 } 555 556 static int jpeg_v5_0_0_set_clockgating_state(void *handle, 557 enum amd_clockgating_state state) 558 { 559 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 560 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 561 562 if (enable) { 563 if (!jpeg_v5_0_0_is_idle(handle)) 564 return -EBUSY; 565 jpeg_v5_0_0_enable_clock_gating(adev); 566 } else { 567 jpeg_v5_0_0_disable_clock_gating(adev); 568 } 569 570 return 0; 571 } 572 573 static int jpeg_v5_0_0_set_powergating_state(void *handle, 574 enum amd_powergating_state state) 575 { 576 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 577 int ret; 578 579 if (state == adev->jpeg.cur_state) 580 return 0; 581 582 if (state == AMD_PG_STATE_GATE) 583 ret = jpeg_v5_0_0_stop(adev); 584 else 585 ret = jpeg_v5_0_0_start(adev); 586 587 if (!ret) 588 adev->jpeg.cur_state = state; 589 590 return ret; 591 } 592 593 static int jpeg_v5_0_0_set_interrupt_state(struct amdgpu_device *adev, 594 struct amdgpu_irq_src *source, 595 unsigned int type, 596 enum amdgpu_interrupt_state state) 597 { 598 return 0; 599 } 600 601 static int jpeg_v5_0_0_process_interrupt(struct amdgpu_device *adev, 602 struct amdgpu_irq_src *source, 603 struct amdgpu_iv_entry *entry) 604 { 605 DRM_DEBUG("IH: JPEG TRAP\n"); 606 607 switch (entry->src_id) { 608 case VCN_4_0__SRCID__JPEG_DECODE: 609 amdgpu_fence_process(adev->jpeg.inst->ring_dec); 610 break; 611 default: 612 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 613 entry->src_id, entry->src_data[0]); 614 break; 615 } 616 617 return 0; 618 } 619 620 static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = { 621 .name = "jpeg_v5_0_0", 622 .early_init = jpeg_v5_0_0_early_init, 623 .sw_init = jpeg_v5_0_0_sw_init, 624 .sw_fini = jpeg_v5_0_0_sw_fini, 625 .hw_init = jpeg_v5_0_0_hw_init, 626 .hw_fini = jpeg_v5_0_0_hw_fini, 627 .suspend = jpeg_v5_0_0_suspend, 628 .resume = jpeg_v5_0_0_resume, 629 .is_idle = jpeg_v5_0_0_is_idle, 630 .wait_for_idle = jpeg_v5_0_0_wait_for_idle, 631 .set_clockgating_state = jpeg_v5_0_0_set_clockgating_state, 632 .set_powergating_state = jpeg_v5_0_0_set_powergating_state, 633 }; 634 635 static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = { 636 .type = AMDGPU_RING_TYPE_VCN_JPEG, 637 .align_mask = 0xf, 638 .get_rptr = jpeg_v5_0_0_dec_ring_get_rptr, 639 .get_wptr = jpeg_v5_0_0_dec_ring_get_wptr, 640 .set_wptr = jpeg_v5_0_0_dec_ring_set_wptr, 641 .parse_cs = jpeg_v2_dec_ring_parse_cs, 642 .emit_frame_size = 643 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 644 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 645 8 + /* jpeg_v5_0_0_dec_ring_emit_vm_flush */ 646 22 + 22 + /* jpeg_v5_0_0_dec_ring_emit_fence x2 vm fence */ 647 8 + 16, 648 .emit_ib_size = 22, /* jpeg_v5_0_0_dec_ring_emit_ib */ 649 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, 650 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, 651 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, 652 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 653 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 654 .insert_nop = jpeg_v4_0_3_dec_ring_nop, 655 .insert_start = jpeg_v4_0_3_dec_ring_insert_start, 656 .insert_end = jpeg_v4_0_3_dec_ring_insert_end, 657 .pad_ib = amdgpu_ring_generic_pad_ib, 658 .begin_use = amdgpu_jpeg_ring_begin_use, 659 .end_use = amdgpu_jpeg_ring_end_use, 660 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, 661 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, 662 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 663 }; 664 665 static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev) 666 { 667 adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_0_0_dec_ring_vm_funcs; 668 } 669 670 static const struct amdgpu_irq_src_funcs jpeg_v5_0_0_irq_funcs = { 671 .set = jpeg_v5_0_0_set_interrupt_state, 672 .process = jpeg_v5_0_0_process_interrupt, 673 }; 674 675 static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev) 676 { 677 adev->jpeg.inst->irq.num_types = 1; 678 adev->jpeg.inst->irq.funcs = &jpeg_v5_0_0_irq_funcs; 679 } 680 681 const struct amdgpu_ip_block_version jpeg_v5_0_0_ip_block = { 682 .type = AMD_IP_BLOCK_TYPE_JPEG, 683 .major = 5, 684 .minor = 0, 685 .rev = 0, 686 .funcs = &jpeg_v5_0_0_ip_funcs, 687 }; 688