1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v4_0_3.h" 30 31 #include "vcn/vcn_5_0_0_offset.h" 32 #include "vcn/vcn_5_0_0_sh_mask.h" 33 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 34 35 static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev); 36 static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev); 37 static int jpeg_v5_0_0_set_powergating_state(void *handle, 38 enum amd_powergating_state state); 39 40 /** 41 * jpeg_v5_0_0_early_init - set function pointers 42 * 43 * @handle: amdgpu_device pointer 44 * 45 * Set ring and irq function pointers 46 */ 47 static int jpeg_v5_0_0_early_init(void *handle) 48 { 49 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 50 51 adev->jpeg.num_jpeg_inst = 1; 52 adev->jpeg.num_jpeg_rings = 1; 53 54 jpeg_v5_0_0_set_dec_ring_funcs(adev); 55 jpeg_v5_0_0_set_irq_funcs(adev); 56 57 return 0; 58 } 59 60 /** 61 * jpeg_v5_0_0_sw_init - sw init for JPEG block 62 * 63 * @handle: amdgpu_device pointer 64 * 65 * Load firmware and sw initialization 66 */ 67 static int jpeg_v5_0_0_sw_init(void *handle) 68 { 69 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 70 struct amdgpu_ring *ring; 71 int r; 72 73 /* JPEG TRAP */ 74 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 75 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 76 if (r) 77 return r; 78 79 r = amdgpu_jpeg_sw_init(adev); 80 if (r) 81 return r; 82 83 r = amdgpu_jpeg_resume(adev); 84 if (r) 85 return r; 86 87 ring = adev->jpeg.inst->ring_dec; 88 ring->use_doorbell = true; 89 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 90 ring->vm_hub = AMDGPU_MMHUB0(0); 91 92 sprintf(ring->name, "jpeg_dec"); 93 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 94 AMDGPU_RING_PRIO_DEFAULT, NULL); 95 if (r) 96 return r; 97 98 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; 99 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); 100 101 return 0; 102 } 103 104 /** 105 * jpeg_v5_0_0_sw_fini - sw fini for JPEG block 106 * 107 * @handle: amdgpu_device pointer 108 * 109 * JPEG suspend and free up sw allocation 110 */ 111 static int jpeg_v5_0_0_sw_fini(void *handle) 112 { 113 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 114 int r; 115 116 r = amdgpu_jpeg_suspend(adev); 117 if (r) 118 return r; 119 120 r = amdgpu_jpeg_sw_fini(adev); 121 122 return r; 123 } 124 125 /** 126 * jpeg_v5_0_0_hw_init - start and test JPEG block 127 * 128 * @handle: amdgpu_device pointer 129 * 130 */ 131 static int jpeg_v5_0_0_hw_init(void *handle) 132 { 133 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 134 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 135 int r; 136 137 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 138 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 139 140 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL, 141 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 142 VCN_JPEG_DB_CTRL__EN_MASK); 143 144 r = amdgpu_ring_test_helper(ring); 145 if (r) 146 return r; 147 148 return 0; 149 } 150 151 /** 152 * jpeg_v5_0_0_hw_fini - stop the hardware block 153 * 154 * @handle: amdgpu_device pointer 155 * 156 * Stop the JPEG block, mark ring as not ready any more 157 */ 158 static int jpeg_v5_0_0_hw_fini(void *handle) 159 { 160 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 161 162 cancel_delayed_work_sync(&adev->vcn.idle_work); 163 164 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 165 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS)) 166 jpeg_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 167 168 return 0; 169 } 170 171 /** 172 * jpeg_v5_0_0_suspend - suspend JPEG block 173 * 174 * @handle: amdgpu_device pointer 175 * 176 * HW fini and suspend JPEG block 177 */ 178 static int jpeg_v5_0_0_suspend(void *handle) 179 { 180 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 181 int r; 182 183 r = jpeg_v5_0_0_hw_fini(adev); 184 if (r) 185 return r; 186 187 r = amdgpu_jpeg_suspend(adev); 188 189 return r; 190 } 191 192 /** 193 * jpeg_v5_0_0_resume - resume JPEG block 194 * 195 * @handle: amdgpu_device pointer 196 * 197 * Resume firmware and hw init JPEG block 198 */ 199 static int jpeg_v5_0_0_resume(void *handle) 200 { 201 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 202 int r; 203 204 r = amdgpu_jpeg_resume(adev); 205 if (r) 206 return r; 207 208 r = jpeg_v5_0_0_hw_init(adev); 209 210 return r; 211 } 212 213 static void jpeg_v5_0_0_disable_clock_gating(struct amdgpu_device *adev) 214 { 215 uint32_t data = 0; 216 217 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 218 219 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 220 data &= ~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK 221 | JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK); 222 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 223 } 224 225 static void jpeg_v5_0_0_enable_clock_gating(struct amdgpu_device *adev) 226 { 227 uint32_t data = 0; 228 229 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 230 231 data |= 1 << JPEG_CGC_CTRL__JPEG0_DEC_MODE__SHIFT; 232 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 233 234 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 235 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK 236 |JPEG_CGC_GATE__JPEG_ENC_MASK 237 |JPEG_CGC_GATE__JMCIF_MASK 238 |JPEG_CGC_GATE__JRBBM_MASK); 239 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 240 } 241 242 static int jpeg_v5_0_0_disable_static_power_gating(struct amdgpu_device *adev) 243 { 244 uint32_t data = 0; 245 246 data = 1 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT; 247 WREG32_SOC15(JPEG, 0, regUVD_IPX_DLDO_CONFIG, data); 248 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, 0, 249 UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK); 250 251 /* disable anti hang mechanism */ 252 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 253 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 254 255 /* keep the JPEG in static PG mode */ 256 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 257 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); 258 259 return 0; 260 } 261 262 static int jpeg_v5_0_0_enable_static_power_gating(struct amdgpu_device *adev) 263 { 264 /* enable anti hang mechanism */ 265 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 266 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 267 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 268 269 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 270 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG), 271 2 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT); 272 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, 273 1 << UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT, 274 UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK); 275 } 276 277 return 0; 278 } 279 280 /** 281 * jpeg_v5_0_0_start - start JPEG block 282 * 283 * @adev: amdgpu_device pointer 284 * 285 * Setup and start the JPEG block 286 */ 287 static int jpeg_v5_0_0_start(struct amdgpu_device *adev) 288 { 289 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 290 int r; 291 292 if (adev->pm.dpm_enabled) 293 amdgpu_dpm_enable_jpeg(adev, true); 294 295 /* disable power gating */ 296 r = jpeg_v5_0_0_disable_static_power_gating(adev); 297 if (r) 298 return r; 299 300 /* JPEG disable CGC */ 301 jpeg_v5_0_0_disable_clock_gating(adev); 302 303 /* MJPEG global tiling registers */ 304 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, 305 adev->gfx.config.gb_addr_config); 306 307 308 /* enable JMI channel */ 309 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0, 310 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 311 312 /* enable System Interrupt for JRBC */ 313 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN), 314 JPEG_SYS_INT_EN__DJRBC0_MASK, 315 ~JPEG_SYS_INT_EN__DJRBC0_MASK); 316 317 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0); 318 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 319 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 320 lower_32_bits(ring->gpu_addr)); 321 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 322 upper_32_bits(ring->gpu_addr)); 323 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0); 324 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0); 325 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L); 326 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); 327 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 328 329 return 0; 330 } 331 332 /** 333 * jpeg_v5_0_0_stop - stop JPEG block 334 * 335 * @adev: amdgpu_device pointer 336 * 337 * stop the JPEG block 338 */ 339 static int jpeg_v5_0_0_stop(struct amdgpu_device *adev) 340 { 341 int r; 342 343 /* reset JMI */ 344 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 345 UVD_JMI_CNTL__SOFT_RESET_MASK, 346 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 347 348 jpeg_v5_0_0_enable_clock_gating(adev); 349 350 /* enable power gating */ 351 r = jpeg_v5_0_0_enable_static_power_gating(adev); 352 if (r) 353 return r; 354 355 if (adev->pm.dpm_enabled) 356 amdgpu_dpm_enable_jpeg(adev, false); 357 358 return 0; 359 } 360 361 /** 362 * jpeg_v5_0_0_dec_ring_get_rptr - get read pointer 363 * 364 * @ring: amdgpu_ring pointer 365 * 366 * Returns the current hardware read pointer 367 */ 368 static uint64_t jpeg_v5_0_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 369 { 370 struct amdgpu_device *adev = ring->adev; 371 372 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR); 373 } 374 375 /** 376 * jpeg_v5_0_0_dec_ring_get_wptr - get write pointer 377 * 378 * @ring: amdgpu_ring pointer 379 * 380 * Returns the current hardware write pointer 381 */ 382 static uint64_t jpeg_v5_0_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 383 { 384 struct amdgpu_device *adev = ring->adev; 385 386 if (ring->use_doorbell) 387 return *ring->wptr_cpu_addr; 388 else 389 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 390 } 391 392 /** 393 * jpeg_v5_0_0_dec_ring_set_wptr - set write pointer 394 * 395 * @ring: amdgpu_ring pointer 396 * 397 * Commits the write pointer to the hardware 398 */ 399 static void jpeg_v5_0_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 400 { 401 struct amdgpu_device *adev = ring->adev; 402 403 if (ring->use_doorbell) { 404 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 405 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 406 } else { 407 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 408 } 409 } 410 411 static bool jpeg_v5_0_0_is_idle(void *handle) 412 { 413 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 414 int ret = 1; 415 416 ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) & 417 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 418 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 419 420 return ret; 421 } 422 423 static int jpeg_v5_0_0_wait_for_idle(void *handle) 424 { 425 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 426 427 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, 428 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 429 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 430 } 431 432 static int jpeg_v5_0_0_set_clockgating_state(void *handle, 433 enum amd_clockgating_state state) 434 { 435 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 436 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 437 438 if (enable) { 439 if (!jpeg_v5_0_0_is_idle(handle)) 440 return -EBUSY; 441 jpeg_v5_0_0_enable_clock_gating(adev); 442 } else { 443 jpeg_v5_0_0_disable_clock_gating(adev); 444 } 445 446 return 0; 447 } 448 449 static int jpeg_v5_0_0_set_powergating_state(void *handle, 450 enum amd_powergating_state state) 451 { 452 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 453 int ret; 454 455 if (state == adev->jpeg.cur_state) 456 return 0; 457 458 if (state == AMD_PG_STATE_GATE) 459 ret = jpeg_v5_0_0_stop(adev); 460 else 461 ret = jpeg_v5_0_0_start(adev); 462 463 if (!ret) 464 adev->jpeg.cur_state = state; 465 466 return ret; 467 } 468 469 static int jpeg_v5_0_0_set_interrupt_state(struct amdgpu_device *adev, 470 struct amdgpu_irq_src *source, 471 unsigned int type, 472 enum amdgpu_interrupt_state state) 473 { 474 return 0; 475 } 476 477 static int jpeg_v5_0_0_process_interrupt(struct amdgpu_device *adev, 478 struct amdgpu_irq_src *source, 479 struct amdgpu_iv_entry *entry) 480 { 481 DRM_DEBUG("IH: JPEG TRAP\n"); 482 483 switch (entry->src_id) { 484 case VCN_4_0__SRCID__JPEG_DECODE: 485 amdgpu_fence_process(adev->jpeg.inst->ring_dec); 486 break; 487 default: 488 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 489 entry->src_id, entry->src_data[0]); 490 break; 491 } 492 493 return 0; 494 } 495 496 static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = { 497 .name = "jpeg_v5_0_0", 498 .early_init = jpeg_v5_0_0_early_init, 499 .late_init = NULL, 500 .sw_init = jpeg_v5_0_0_sw_init, 501 .sw_fini = jpeg_v5_0_0_sw_fini, 502 .hw_init = jpeg_v5_0_0_hw_init, 503 .hw_fini = jpeg_v5_0_0_hw_fini, 504 .suspend = jpeg_v5_0_0_suspend, 505 .resume = jpeg_v5_0_0_resume, 506 .is_idle = jpeg_v5_0_0_is_idle, 507 .wait_for_idle = jpeg_v5_0_0_wait_for_idle, 508 .check_soft_reset = NULL, 509 .pre_soft_reset = NULL, 510 .soft_reset = NULL, 511 .post_soft_reset = NULL, 512 .set_clockgating_state = jpeg_v5_0_0_set_clockgating_state, 513 .set_powergating_state = jpeg_v5_0_0_set_powergating_state, 514 .dump_ip_state = NULL, 515 .print_ip_state = NULL, 516 }; 517 518 static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = { 519 .type = AMDGPU_RING_TYPE_VCN_JPEG, 520 .align_mask = 0xf, 521 .get_rptr = jpeg_v5_0_0_dec_ring_get_rptr, 522 .get_wptr = jpeg_v5_0_0_dec_ring_get_wptr, 523 .set_wptr = jpeg_v5_0_0_dec_ring_set_wptr, 524 .emit_frame_size = 525 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 526 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 527 8 + /* jpeg_v5_0_0_dec_ring_emit_vm_flush */ 528 22 + 22 + /* jpeg_v5_0_0_dec_ring_emit_fence x2 vm fence */ 529 8 + 16, 530 .emit_ib_size = 22, /* jpeg_v5_0_0_dec_ring_emit_ib */ 531 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, 532 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, 533 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, 534 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 535 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 536 .insert_nop = jpeg_v4_0_3_dec_ring_nop, 537 .insert_start = jpeg_v4_0_3_dec_ring_insert_start, 538 .insert_end = jpeg_v4_0_3_dec_ring_insert_end, 539 .pad_ib = amdgpu_ring_generic_pad_ib, 540 .begin_use = amdgpu_jpeg_ring_begin_use, 541 .end_use = amdgpu_jpeg_ring_end_use, 542 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, 543 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, 544 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 545 }; 546 547 static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev) 548 { 549 adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_0_0_dec_ring_vm_funcs; 550 } 551 552 static const struct amdgpu_irq_src_funcs jpeg_v5_0_0_irq_funcs = { 553 .set = jpeg_v5_0_0_set_interrupt_state, 554 .process = jpeg_v5_0_0_process_interrupt, 555 }; 556 557 static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev) 558 { 559 adev->jpeg.inst->irq.num_types = 1; 560 adev->jpeg.inst->irq.funcs = &jpeg_v5_0_0_irq_funcs; 561 } 562 563 const struct amdgpu_ip_block_version jpeg_v5_0_0_ip_block = { 564 .type = AMD_IP_BLOCK_TYPE_JPEG, 565 .major = 5, 566 .minor = 0, 567 .rev = 0, 568 .funcs = &jpeg_v5_0_0_ip_funcs, 569 }; 570