1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v2_0.h" 30 #include "jpeg_v4_0_5.h" 31 #include "mmsch_v4_0.h" 32 33 #include "vcn/vcn_4_0_5_offset.h" 34 #include "vcn/vcn_4_0_5_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 36 37 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 38 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 39 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 40 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 41 42 #define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 43 #define regJPEG_DEC_GFX10_ADDR_CONFIG_INTERNAL_OFFSET 0x4026 44 #define regJPEG_SYS_INT_EN_INTERNAL_OFFSET 0x4141 45 #define regJPEG_CGC_CTRL_INTERNAL_OFFSET 0x4161 46 #define regJPEG_CGC_GATE_INTERNAL_OFFSET 0x4160 47 #define regUVD_NO_OP_INTERNAL_OFFSET 0x0029 48 49 static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev); 50 static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev); 51 static int jpeg_v4_0_5_set_powergating_state(void *handle, 52 enum amd_powergating_state state); 53 54 static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring); 55 56 static int amdgpu_ih_clientid_jpeg[] = { 57 SOC15_IH_CLIENTID_VCN, 58 SOC15_IH_CLIENTID_VCN1 59 }; 60 61 /** 62 * jpeg_v4_0_5_early_init - set function pointers 63 * 64 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 65 * 66 * Set ring and irq function pointers 67 */ 68 static int jpeg_v4_0_5_early_init(struct amdgpu_ip_block *ip_block) 69 { 70 struct amdgpu_device *adev = ip_block->adev; 71 72 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 73 case IP_VERSION(4, 0, 5): 74 adev->jpeg.num_jpeg_inst = 1; 75 break; 76 case IP_VERSION(4, 0, 6): 77 adev->jpeg.num_jpeg_inst = 2; 78 break; 79 default: 80 DRM_DEV_ERROR(adev->dev, 81 "Failed to init vcn ip block(UVD_HWIP:0x%x)\n", 82 amdgpu_ip_version(adev, UVD_HWIP, 0)); 83 return -EINVAL; 84 } 85 86 adev->jpeg.num_jpeg_rings = 1; 87 88 jpeg_v4_0_5_set_dec_ring_funcs(adev); 89 jpeg_v4_0_5_set_irq_funcs(adev); 90 91 return 0; 92 } 93 94 /** 95 * jpeg_v4_0_5_sw_init - sw init for JPEG block 96 * 97 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 98 * 99 * Load firmware and sw initialization 100 */ 101 static int jpeg_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) 102 { 103 struct amdgpu_device *adev = ip_block->adev; 104 struct amdgpu_ring *ring; 105 int r, i; 106 107 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 108 if (adev->jpeg.harvest_config & (1 << i)) 109 continue; 110 111 /* JPEG TRAP */ 112 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i], 113 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq); 114 if (r) 115 return r; 116 117 /* JPEG DJPEG POISON EVENT */ 118 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i], 119 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].irq); 120 if (r) 121 return r; 122 123 /* JPEG EJPEG POISON EVENT */ 124 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i], 125 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].irq); 126 if (r) 127 return r; 128 } 129 130 r = amdgpu_jpeg_sw_init(adev); 131 if (r) 132 return r; 133 134 r = amdgpu_jpeg_resume(adev); 135 if (r) 136 return r; 137 138 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 139 if (adev->jpeg.harvest_config & (1 << i)) 140 continue; 141 142 ring = adev->jpeg.inst[i].ring_dec; 143 ring->use_doorbell = true; 144 ring->vm_hub = AMDGPU_MMHUB0(0); 145 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i; 146 sprintf(ring->name, "jpeg_dec_%d", i); 147 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, 148 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 149 if (r) 150 return r; 151 152 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; 153 adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, regUVD_JPEG_PITCH); 154 } 155 156 return 0; 157 } 158 159 /** 160 * jpeg_v4_0_5_sw_fini - sw fini for JPEG block 161 * 162 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 163 * 164 * JPEG suspend and free up sw allocation 165 */ 166 static int jpeg_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block) 167 { 168 struct amdgpu_device *adev = ip_block->adev; 169 int r; 170 171 r = amdgpu_jpeg_suspend(adev); 172 if (r) 173 return r; 174 175 r = amdgpu_jpeg_sw_fini(adev); 176 177 return r; 178 } 179 180 /** 181 * jpeg_v4_0_5_hw_init - start and test JPEG block 182 * 183 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 184 * 185 */ 186 static int jpeg_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block) 187 { 188 struct amdgpu_device *adev = ip_block->adev; 189 struct amdgpu_ring *ring; 190 int i, r = 0; 191 192 // TODO: Enable ring test with DPG support 193 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) { 194 return 0; 195 } 196 197 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 198 if (adev->jpeg.harvest_config & (1 << i)) 199 continue; 200 201 ring = adev->jpeg.inst[i].ring_dec; 202 r = amdgpu_ring_test_helper(ring); 203 if (r) 204 return r; 205 } 206 207 return 0; 208 } 209 210 /** 211 * jpeg_v4_0_5_hw_fini - stop the hardware block 212 * 213 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 214 * 215 * Stop the JPEG block, mark ring as not ready any more 216 */ 217 static int jpeg_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block) 218 { 219 struct amdgpu_device *adev = ip_block->adev; 220 int i; 221 222 cancel_delayed_work_sync(&adev->vcn.idle_work); 223 224 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 225 if (adev->jpeg.harvest_config & (1 << i)) 226 continue; 227 228 if (!amdgpu_sriov_vf(adev)) { 229 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 230 RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS)) 231 jpeg_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE); 232 } 233 } 234 return 0; 235 } 236 237 /** 238 * jpeg_v4_0_5_suspend - suspend JPEG block 239 * 240 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 241 * 242 * HW fini and suspend JPEG block 243 */ 244 static int jpeg_v4_0_5_suspend(struct amdgpu_ip_block *ip_block) 245 { 246 int r; 247 248 r = jpeg_v4_0_5_hw_fini(ip_block); 249 if (r) 250 return r; 251 252 r = amdgpu_jpeg_suspend(ip_block->adev); 253 254 return r; 255 } 256 257 /** 258 * jpeg_v4_0_5_resume - resume JPEG block 259 * 260 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 261 * 262 * Resume firmware and hw init JPEG block 263 */ 264 static int jpeg_v4_0_5_resume(struct amdgpu_ip_block *ip_block) 265 { 266 int r; 267 268 r = amdgpu_jpeg_resume(ip_block->adev); 269 if (r) 270 return r; 271 272 r = jpeg_v4_0_5_hw_init(ip_block); 273 274 return r; 275 } 276 277 static void jpeg_v4_0_5_disable_clock_gating(struct amdgpu_device *adev, int inst) 278 { 279 uint32_t data = 0; 280 281 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL); 282 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 283 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 284 data &= (~JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK); 285 } else { 286 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 287 } 288 289 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 290 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 291 WREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL, data); 292 293 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE); 294 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 295 | JPEG_CGC_GATE__JPEG2_DEC_MASK 296 | JPEG_CGC_GATE__JMCIF_MASK 297 | JPEG_CGC_GATE__JRBBM_MASK); 298 WREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE, data); 299 } 300 301 static void jpeg_v4_0_5_enable_clock_gating(struct amdgpu_device *adev, int inst) 302 { 303 uint32_t data = 0; 304 305 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL); 306 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 307 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 308 data |= JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK; 309 } else { 310 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 311 } 312 313 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 314 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 315 WREG32_SOC15(JPEG, inst, regJPEG_CGC_CTRL, data); 316 317 data = RREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE); 318 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 319 |JPEG_CGC_GATE__JPEG2_DEC_MASK 320 |JPEG_CGC_GATE__JMCIF_MASK 321 |JPEG_CGC_GATE__JRBBM_MASK); 322 WREG32_SOC15(JPEG, inst, regJPEG_CGC_GATE, data); 323 } 324 325 static void jpeg_engine_4_0_5_dpg_clock_gating_mode(struct amdgpu_device *adev, 326 int inst_idx, uint8_t indirect) 327 { 328 uint32_t data = 0; 329 330 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 331 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 332 else 333 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 334 335 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 336 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 337 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_CGC_CTRL_INTERNAL_OFFSET, data, indirect); 338 339 data = 0; 340 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_CGC_GATE_INTERNAL_OFFSET, 341 data, indirect); 342 } 343 344 static int jpeg_v4_0_5_disable_static_power_gating(struct amdgpu_device *adev, int inst) 345 { 346 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 347 WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG), 348 1 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT); 349 SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS, 350 0, UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK); 351 } 352 353 /* disable anti hang mechanism */ 354 WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0, 355 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 356 357 /* keep the JPEG in static PG mode */ 358 WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 0, 359 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); 360 361 return 0; 362 } 363 364 static int jpeg_v4_0_5_enable_static_power_gating(struct amdgpu_device *adev, int inst) 365 { 366 /* enable anti hang mechanism */ 367 WREG32_P(SOC15_REG_OFFSET(JPEG, inst, regUVD_JPEG_POWER_STATUS), 368 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 369 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 370 371 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 372 WREG32(SOC15_REG_OFFSET(JPEG, inst, regUVD_IPX_DLDO_CONFIG), 373 2 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT); 374 SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS, 375 1 << UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT, 376 UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK); 377 } 378 379 return 0; 380 } 381 382 /** 383 * jpeg_v4_0_5_start_dpg_mode - Jpeg start with dpg mode 384 * 385 * @adev: amdgpu_device pointer 386 * @inst_idx: instance number index 387 * @indirect: indirectly write sram 388 * 389 * Start JPEG block with dpg mode 390 */ 391 static void jpeg_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 392 { 393 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; 394 uint32_t reg_data = 0; 395 396 /* enable anti hang mechanism */ 397 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); 398 reg_data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK; 399 reg_data |= 0x1; 400 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); 401 402 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 403 WREG32(SOC15_REG_OFFSET(JPEG, inst_idx, regUVD_IPX_DLDO_CONFIG), 404 2 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT); 405 SOC15_WAIT_ON_RREG(JPEG, inst_idx, regUVD_IPX_DLDO_STATUS, 406 1 << UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT, 407 UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK); 408 } 409 410 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); 411 reg_data |= UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK; 412 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); 413 414 if (indirect) 415 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr = 416 (uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr; 417 418 jpeg_engine_4_0_5_dpg_clock_gating_mode(adev, inst_idx, indirect); 419 420 /* MJPEG global tiling registers */ 421 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_DEC_GFX10_ADDR_CONFIG_INTERNAL_OFFSET, 422 adev->gfx.config.gb_addr_config, indirect); 423 /* enable System Interrupt for JRBC */ 424 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_SYS_INT_EN_INTERNAL_OFFSET, 425 JPEG_SYS_INT_EN__DJRBC_MASK, indirect); 426 427 /* add nop to workaround PSP size check */ 428 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regUVD_NO_OP_INTERNAL_OFFSET, 0, indirect); 429 430 if (indirect) 431 amdgpu_jpeg_psp_update_sram(adev, inst_idx, 0); 432 433 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_VMID, 0); 434 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 435 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 436 lower_32_bits(ring->gpu_addr)); 437 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 438 upper_32_bits(ring->gpu_addr)); 439 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_RPTR, 0); 440 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR, 0); 441 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, 0x00000002L); 442 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); 443 ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR); 444 } 445 446 /** 447 * jpeg_v4_0_5_stop_dpg_mode - Jpeg stop with dpg mode 448 * 449 * @adev: amdgpu_device pointer 450 * @inst_idx: instance number index 451 * 452 * Stop JPEG block with dpg mode 453 */ 454 static void jpeg_v4_0_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 455 { 456 uint32_t reg_data = 0; 457 458 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); 459 reg_data &= ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK; 460 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); 461 462 } 463 464 /** 465 * jpeg_v4_0_5_start - start JPEG block 466 * 467 * @adev: amdgpu_device pointer 468 * 469 * Setup and start the JPEG block 470 */ 471 static int jpeg_v4_0_5_start(struct amdgpu_device *adev) 472 { 473 struct amdgpu_ring *ring; 474 int r, i; 475 476 if (adev->pm.dpm_enabled) 477 amdgpu_dpm_enable_jpeg(adev, true); 478 479 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 480 if (adev->jpeg.harvest_config & (1 << i)) 481 continue; 482 483 ring = adev->jpeg.inst[i].ring_dec; 484 /* doorbell programming is done for every playback */ 485 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 486 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i); 487 488 WREG32_SOC15(VCN, i, regVCN_JPEG_DB_CTRL, 489 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 490 VCN_JPEG_DB_CTRL__EN_MASK); 491 492 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) { 493 jpeg_v4_0_5_start_dpg_mode(adev, i, adev->jpeg.indirect_sram); 494 continue; 495 } 496 497 /* disable power gating */ 498 r = jpeg_v4_0_5_disable_static_power_gating(adev, i); 499 if (r) 500 return r; 501 502 /* JPEG disable CGC */ 503 jpeg_v4_0_5_disable_clock_gating(adev, i); 504 505 /* MJPEG global tiling registers */ 506 WREG32_SOC15(JPEG, i, regJPEG_DEC_GFX10_ADDR_CONFIG, 507 adev->gfx.config.gb_addr_config); 508 509 /* enable JMI channel */ 510 WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL), 0, 511 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 512 513 /* enable System Interrupt for JRBC */ 514 WREG32_P(SOC15_REG_OFFSET(JPEG, i, regJPEG_SYS_INT_EN), 515 JPEG_SYS_INT_EN__DJRBC_MASK, 516 ~JPEG_SYS_INT_EN__DJRBC_MASK); 517 518 WREG32_SOC15(JPEG, i, regUVD_LMI_JRBC_RB_VMID, 0); 519 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 520 WREG32_SOC15(JPEG, i, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 521 lower_32_bits(ring->gpu_addr)); 522 WREG32_SOC15(JPEG, i, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 523 upper_32_bits(ring->gpu_addr)); 524 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_RPTR, 0); 525 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR, 0); 526 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_CNTL, 0x00000002L); 527 WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); 528 ring->wptr = RREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR); 529 } 530 531 return 0; 532 } 533 534 /** 535 * jpeg_v4_0_5_stop - stop JPEG block 536 * 537 * @adev: amdgpu_device pointer 538 * 539 * stop the JPEG block 540 */ 541 static int jpeg_v4_0_5_stop(struct amdgpu_device *adev) 542 { 543 int r, i; 544 545 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 546 if (adev->jpeg.harvest_config & (1 << i)) 547 continue; 548 549 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) { 550 jpeg_v4_0_5_stop_dpg_mode(adev, i); 551 continue; 552 } 553 554 /* reset JMI */ 555 WREG32_P(SOC15_REG_OFFSET(JPEG, i, regUVD_JMI_CNTL), 556 UVD_JMI_CNTL__SOFT_RESET_MASK, 557 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 558 559 jpeg_v4_0_5_enable_clock_gating(adev, i); 560 561 /* enable power gating */ 562 r = jpeg_v4_0_5_enable_static_power_gating(adev, i); 563 if (r) 564 return r; 565 } 566 if (adev->pm.dpm_enabled) 567 amdgpu_dpm_enable_jpeg(adev, false); 568 569 return 0; 570 } 571 572 /** 573 * jpeg_v4_0_5_dec_ring_get_rptr - get read pointer 574 * 575 * @ring: amdgpu_ring pointer 576 * 577 * Returns the current hardware read pointer 578 */ 579 static uint64_t jpeg_v4_0_5_dec_ring_get_rptr(struct amdgpu_ring *ring) 580 { 581 struct amdgpu_device *adev = ring->adev; 582 583 return RREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_RPTR); 584 } 585 586 /** 587 * jpeg_v4_0_5_dec_ring_get_wptr - get write pointer 588 * 589 * @ring: amdgpu_ring pointer 590 * 591 * Returns the current hardware write pointer 592 */ 593 static uint64_t jpeg_v4_0_5_dec_ring_get_wptr(struct amdgpu_ring *ring) 594 { 595 struct amdgpu_device *adev = ring->adev; 596 597 if (ring->use_doorbell) 598 return *ring->wptr_cpu_addr; 599 else 600 return RREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_WPTR); 601 } 602 603 /** 604 * jpeg_v4_0_5_dec_ring_set_wptr - set write pointer 605 * 606 * @ring: amdgpu_ring pointer 607 * 608 * Commits the write pointer to the hardware 609 */ 610 static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring) 611 { 612 struct amdgpu_device *adev = ring->adev; 613 614 if (ring->use_doorbell) { 615 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 616 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 617 } else { 618 WREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 619 } 620 } 621 622 static bool jpeg_v4_0_5_is_idle(void *handle) 623 { 624 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 625 int i, ret = 1; 626 627 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 628 if (adev->jpeg.harvest_config & (1 << i)) 629 continue; 630 631 ret &= (((RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS) & 632 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 633 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 634 } 635 return ret; 636 } 637 638 static int jpeg_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block) 639 { 640 struct amdgpu_device *adev = ip_block->adev; 641 int i; 642 643 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 644 if (adev->jpeg.harvest_config & (1 << i)) 645 continue; 646 647 return SOC15_WAIT_ON_RREG(JPEG, i, regUVD_JRBC_STATUS, 648 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 649 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 650 } 651 652 return 0; 653 } 654 655 static int jpeg_v4_0_5_set_clockgating_state(void *handle, 656 enum amd_clockgating_state state) 657 { 658 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 659 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 660 int i; 661 662 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 663 if (adev->jpeg.harvest_config & (1 << i)) 664 continue; 665 666 if (enable) { 667 if (!jpeg_v4_0_5_is_idle(handle)) 668 return -EBUSY; 669 670 jpeg_v4_0_5_enable_clock_gating(adev, i); 671 } else { 672 jpeg_v4_0_5_disable_clock_gating(adev, i); 673 } 674 } 675 676 return 0; 677 } 678 679 static int jpeg_v4_0_5_set_powergating_state(void *handle, 680 enum amd_powergating_state state) 681 { 682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 683 int ret; 684 685 if (amdgpu_sriov_vf(adev)) { 686 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; 687 return 0; 688 } 689 690 if (state == adev->jpeg.cur_state) 691 return 0; 692 693 if (state == AMD_PG_STATE_GATE) 694 ret = jpeg_v4_0_5_stop(adev); 695 else 696 ret = jpeg_v4_0_5_start(adev); 697 698 if (!ret) 699 adev->jpeg.cur_state = state; 700 701 return ret; 702 } 703 704 static int jpeg_v4_0_5_process_interrupt(struct amdgpu_device *adev, 705 struct amdgpu_irq_src *source, 706 struct amdgpu_iv_entry *entry) 707 { 708 uint32_t ip_instance; 709 710 DRM_DEBUG("IH: JPEG TRAP\n"); 711 712 switch (entry->client_id) { 713 case SOC15_IH_CLIENTID_VCN: 714 ip_instance = 0; 715 break; 716 case SOC15_IH_CLIENTID_VCN1: 717 ip_instance = 1; 718 break; 719 default: 720 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 721 return 0; 722 } 723 724 switch (entry->src_id) { 725 case VCN_4_0__SRCID__JPEG_DECODE: 726 amdgpu_fence_process(adev->jpeg.inst[ip_instance].ring_dec); 727 break; 728 case VCN_4_0__SRCID_DJPEG0_POISON: 729 case VCN_4_0__SRCID_EJPEG0_POISON: 730 amdgpu_jpeg_process_poison_irq(adev, source, entry); 731 break; 732 default: 733 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 734 entry->src_id, entry->src_data[0]); 735 break; 736 } 737 738 return 0; 739 } 740 741 static const struct amd_ip_funcs jpeg_v4_0_5_ip_funcs = { 742 .name = "jpeg_v4_0_5", 743 .early_init = jpeg_v4_0_5_early_init, 744 .sw_init = jpeg_v4_0_5_sw_init, 745 .sw_fini = jpeg_v4_0_5_sw_fini, 746 .hw_init = jpeg_v4_0_5_hw_init, 747 .hw_fini = jpeg_v4_0_5_hw_fini, 748 .suspend = jpeg_v4_0_5_suspend, 749 .resume = jpeg_v4_0_5_resume, 750 .is_idle = jpeg_v4_0_5_is_idle, 751 .wait_for_idle = jpeg_v4_0_5_wait_for_idle, 752 .set_clockgating_state = jpeg_v4_0_5_set_clockgating_state, 753 .set_powergating_state = jpeg_v4_0_5_set_powergating_state, 754 }; 755 756 static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = { 757 .type = AMDGPU_RING_TYPE_VCN_JPEG, 758 .align_mask = 0xf, 759 .get_rptr = jpeg_v4_0_5_dec_ring_get_rptr, 760 .get_wptr = jpeg_v4_0_5_dec_ring_get_wptr, 761 .set_wptr = jpeg_v4_0_5_dec_ring_set_wptr, 762 .parse_cs = jpeg_v2_dec_ring_parse_cs, 763 .emit_frame_size = 764 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 765 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 766 8 + /* jpeg_v4_0_5_dec_ring_emit_vm_flush */ 767 18 + 18 + /* jpeg_v4_0_5_dec_ring_emit_fence x2 vm fence */ 768 8 + 16, 769 .emit_ib_size = 22, /* jpeg_v4_0_5_dec_ring_emit_ib */ 770 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 771 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 772 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 773 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 774 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 775 .insert_nop = jpeg_v2_0_dec_ring_nop, 776 .insert_start = jpeg_v2_0_dec_ring_insert_start, 777 .insert_end = jpeg_v2_0_dec_ring_insert_end, 778 .pad_ib = amdgpu_ring_generic_pad_ib, 779 .begin_use = amdgpu_jpeg_ring_begin_use, 780 .end_use = amdgpu_jpeg_ring_end_use, 781 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 782 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 783 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 784 }; 785 786 static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev) 787 { 788 int i; 789 790 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 791 if (adev->jpeg.harvest_config & (1 << i)) 792 continue; 793 794 adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v4_0_5_dec_ring_vm_funcs; 795 adev->jpeg.inst[i].ring_dec->me = i; 796 } 797 } 798 799 static const struct amdgpu_irq_src_funcs jpeg_v4_0_5_irq_funcs = { 800 .process = jpeg_v4_0_5_process_interrupt, 801 }; 802 803 static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev) 804 { 805 int i; 806 807 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 808 if (adev->jpeg.harvest_config & (1 << i)) 809 continue; 810 811 adev->jpeg.inst[i].irq.num_types = 1; 812 adev->jpeg.inst[i].irq.funcs = &jpeg_v4_0_5_irq_funcs; 813 } 814 } 815 816 const struct amdgpu_ip_block_version jpeg_v4_0_5_ip_block = { 817 .type = AMD_IP_BLOCK_TYPE_JPEG, 818 .major = 4, 819 .minor = 0, 820 .rev = 5, 821 .funcs = &jpeg_v4_0_5_ip_funcs, 822 }; 823 824