1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "soc15.h" 27 #include "soc15d.h" 28 #include "jpeg_v4_0_3.h" 29 #include "mmsch_v4_0_3.h" 30 31 #include "vcn/vcn_4_0_3_offset.h" 32 #include "vcn/vcn_4_0_3_sh_mask.h" 33 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 34 35 #define NORMALIZE_JPEG_REG_OFFSET(offset) \ 36 (offset & 0x1FFFF) 37 38 enum jpeg_engin_status { 39 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0, 40 UVD_PGFSM_STATUS__UVDJ_PWR_OFF = 2, 41 }; 42 43 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev); 44 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 45 static int jpeg_v4_0_3_set_powergating_state(void *handle, 46 enum amd_powergating_state state); 47 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 48 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring); 49 50 static int amdgpu_ih_srcid_jpeg[] = { 51 VCN_4_0__SRCID__JPEG_DECODE, 52 VCN_4_0__SRCID__JPEG1_DECODE, 53 VCN_4_0__SRCID__JPEG2_DECODE, 54 VCN_4_0__SRCID__JPEG3_DECODE, 55 VCN_4_0__SRCID__JPEG4_DECODE, 56 VCN_4_0__SRCID__JPEG5_DECODE, 57 VCN_4_0__SRCID__JPEG6_DECODE, 58 VCN_4_0__SRCID__JPEG7_DECODE 59 }; 60 61 /** 62 * jpeg_v4_0_3_early_init - set function pointers 63 * 64 * @handle: amdgpu_device pointer 65 * 66 * Set ring and irq function pointers 67 */ 68 static int jpeg_v4_0_3_early_init(void *handle) 69 { 70 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 71 72 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS; 73 74 jpeg_v4_0_3_set_dec_ring_funcs(adev); 75 jpeg_v4_0_3_set_irq_funcs(adev); 76 jpeg_v4_0_3_set_ras_funcs(adev); 77 78 return 0; 79 } 80 81 /** 82 * jpeg_v4_0_3_sw_init - sw init for JPEG block 83 * 84 * @handle: amdgpu_device pointer 85 * 86 * Load firmware and sw initialization 87 */ 88 static int jpeg_v4_0_3_sw_init(void *handle) 89 { 90 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 91 struct amdgpu_ring *ring; 92 int i, j, r, jpeg_inst; 93 94 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 95 /* JPEG TRAP */ 96 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 97 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); 98 if (r) 99 return r; 100 } 101 102 r = amdgpu_jpeg_sw_init(adev); 103 if (r) 104 return r; 105 106 r = amdgpu_jpeg_resume(adev); 107 if (r) 108 return r; 109 110 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 111 jpeg_inst = GET_INST(JPEG, i); 112 113 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 114 ring = &adev->jpeg.inst[i].ring_dec[j]; 115 ring->use_doorbell = true; 116 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); 117 if (!amdgpu_sriov_vf(adev)) { 118 ring->doorbell_index = 119 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 120 1 + j + 9 * jpeg_inst; 121 } else { 122 if (j < 4) 123 ring->doorbell_index = 124 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 125 4 + j + 32 * jpeg_inst; 126 else 127 ring->doorbell_index = 128 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 129 8 + j + 32 * jpeg_inst; 130 } 131 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); 132 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 133 AMDGPU_RING_PRIO_DEFAULT, NULL); 134 if (r) 135 return r; 136 137 adev->jpeg.internal.jpeg_pitch[j] = 138 regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET; 139 adev->jpeg.inst[i].external.jpeg_pitch[j] = 140 SOC15_REG_OFFSET1( 141 JPEG, jpeg_inst, 142 regUVD_JRBC0_UVD_JRBC_SCRATCH0, 143 (j ? (0x40 * j - 0xc80) : 0)); 144 } 145 } 146 147 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 148 r = amdgpu_jpeg_ras_sw_init(adev); 149 if (r) { 150 dev_err(adev->dev, "Failed to initialize jpeg ras block!\n"); 151 return r; 152 } 153 } 154 155 return 0; 156 } 157 158 /** 159 * jpeg_v4_0_3_sw_fini - sw fini for JPEG block 160 * 161 * @handle: amdgpu_device pointer 162 * 163 * JPEG suspend and free up sw allocation 164 */ 165 static int jpeg_v4_0_3_sw_fini(void *handle) 166 { 167 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 168 int r; 169 170 r = amdgpu_jpeg_suspend(adev); 171 if (r) 172 return r; 173 174 r = amdgpu_jpeg_sw_fini(adev); 175 176 return r; 177 } 178 179 static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev) 180 { 181 struct amdgpu_ring *ring; 182 uint64_t ctx_addr; 183 uint32_t param, resp, expected; 184 uint32_t tmp, timeout; 185 186 struct amdgpu_mm_table *table = &adev->virt.mm_table; 187 uint32_t *table_loc; 188 uint32_t table_size; 189 uint32_t size, size_dw, item_offset; 190 uint32_t init_status; 191 int i, j, jpeg_inst; 192 193 struct mmsch_v4_0_cmd_direct_write 194 direct_wt = { {0} }; 195 struct mmsch_v4_0_cmd_end end = { {0} }; 196 struct mmsch_v4_0_3_init_header header; 197 198 direct_wt.cmd_header.command_type = 199 MMSCH_COMMAND__DIRECT_REG_WRITE; 200 end.cmd_header.command_type = 201 MMSCH_COMMAND__END; 202 203 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 204 jpeg_inst = GET_INST(JPEG, i); 205 206 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 207 header.version = MMSCH_VERSION; 208 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 209 210 table_loc = (uint32_t *)table->cpu_addr; 211 table_loc += header.total_size; 212 213 item_offset = header.total_size; 214 215 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) { 216 ring = &adev->jpeg.inst[i].ring_dec[j]; 217 table_size = 0; 218 219 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW); 220 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr)); 221 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH); 222 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr)); 223 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE); 224 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4); 225 226 if (j <= 3) { 227 header.mjpegdec0[j].table_offset = item_offset; 228 header.mjpegdec0[j].init_status = 0; 229 header.mjpegdec0[j].table_size = table_size; 230 } else { 231 header.mjpegdec1[j - 4].table_offset = item_offset; 232 header.mjpegdec1[j - 4].init_status = 0; 233 header.mjpegdec1[j - 4].table_size = table_size; 234 } 235 header.total_size += table_size; 236 item_offset += table_size; 237 } 238 239 MMSCH_V4_0_INSERT_END(); 240 241 /* send init table to MMSCH */ 242 size = sizeof(struct mmsch_v4_0_3_init_header); 243 table_loc = (uint32_t *)table->cpu_addr; 244 memcpy((void *)table_loc, &header, size); 245 246 ctx_addr = table->gpu_addr; 247 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 248 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 249 250 tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID); 251 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 252 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 253 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp); 254 255 size = header.total_size; 256 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size); 257 258 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0); 259 260 param = 0x00000001; 261 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param); 262 tmp = 0; 263 timeout = 1000; 264 resp = 0; 265 expected = MMSCH_VF_MAILBOX_RESP__OK; 266 init_status = 267 ((struct mmsch_v4_0_3_init_header *)(table_loc))->mjpegdec0[i].init_status; 268 while (resp != expected) { 269 resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP); 270 271 if (resp != 0) 272 break; 273 udelay(10); 274 tmp = tmp + 10; 275 if (tmp >= timeout) { 276 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 277 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 278 "(expected=0x%08x, readback=0x%08x)\n", 279 tmp, expected, resp); 280 return -EBUSY; 281 } 282 } 283 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE && 284 init_status != MMSCH_VF_ENGINE_STATUS__PASS) 285 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", 286 resp, init_status); 287 288 } 289 return 0; 290 } 291 292 /** 293 * jpeg_v4_0_3_hw_init - start and test JPEG block 294 * 295 * @handle: amdgpu_device pointer 296 * 297 */ 298 static int jpeg_v4_0_3_hw_init(void *handle) 299 { 300 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 301 struct amdgpu_ring *ring; 302 int i, j, r, jpeg_inst; 303 304 if (amdgpu_sriov_vf(adev)) { 305 r = jpeg_v4_0_3_start_sriov(adev); 306 if (r) 307 return r; 308 309 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 310 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 311 ring = &adev->jpeg.inst[i].ring_dec[j]; 312 ring->wptr = 0; 313 ring->wptr_old = 0; 314 jpeg_v4_0_3_dec_ring_set_wptr(ring); 315 ring->sched.ready = true; 316 } 317 } 318 } else { 319 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 320 jpeg_inst = GET_INST(JPEG, i); 321 322 ring = adev->jpeg.inst[i].ring_dec; 323 324 if (ring->use_doorbell) 325 adev->nbio.funcs->vcn_doorbell_range( 326 adev, ring->use_doorbell, 327 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 328 9 * jpeg_inst, 329 adev->jpeg.inst[i].aid_id); 330 331 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 332 ring = &adev->jpeg.inst[i].ring_dec[j]; 333 if (ring->use_doorbell) 334 WREG32_SOC15_OFFSET( 335 VCN, GET_INST(VCN, i), 336 regVCN_JPEG_DB_CTRL, 337 (ring->pipe ? (ring->pipe - 0x15) : 0), 338 ring->doorbell_index 339 << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 340 VCN_JPEG_DB_CTRL__EN_MASK); 341 r = amdgpu_ring_test_helper(ring); 342 if (r) 343 return r; 344 } 345 } 346 } 347 348 return 0; 349 } 350 351 /** 352 * jpeg_v4_0_3_hw_fini - stop the hardware block 353 * 354 * @handle: amdgpu_device pointer 355 * 356 * Stop the JPEG block, mark ring as not ready any more 357 */ 358 static int jpeg_v4_0_3_hw_fini(void *handle) 359 { 360 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 361 int ret = 0; 362 363 cancel_delayed_work_sync(&adev->jpeg.idle_work); 364 365 if (!amdgpu_sriov_vf(adev)) { 366 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) 367 ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE); 368 } 369 370 return ret; 371 } 372 373 /** 374 * jpeg_v4_0_3_suspend - suspend JPEG block 375 * 376 * @handle: amdgpu_device pointer 377 * 378 * HW fini and suspend JPEG block 379 */ 380 static int jpeg_v4_0_3_suspend(void *handle) 381 { 382 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 383 int r; 384 385 r = jpeg_v4_0_3_hw_fini(adev); 386 if (r) 387 return r; 388 389 r = amdgpu_jpeg_suspend(adev); 390 391 return r; 392 } 393 394 /** 395 * jpeg_v4_0_3_resume - resume JPEG block 396 * 397 * @handle: amdgpu_device pointer 398 * 399 * Resume firmware and hw init JPEG block 400 */ 401 static int jpeg_v4_0_3_resume(void *handle) 402 { 403 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 404 int r; 405 406 r = amdgpu_jpeg_resume(adev); 407 if (r) 408 return r; 409 410 r = jpeg_v4_0_3_hw_init(adev); 411 412 return r; 413 } 414 415 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) 416 { 417 int i, jpeg_inst; 418 uint32_t data; 419 420 jpeg_inst = GET_INST(JPEG, inst_idx); 421 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 422 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 423 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 424 data &= (~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1)); 425 } else { 426 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 427 } 428 429 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 430 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 431 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 432 433 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 434 data &= ~(JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 435 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 436 data &= ~(JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 437 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 438 } 439 440 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) 441 { 442 int i, jpeg_inst; 443 uint32_t data; 444 445 jpeg_inst = GET_INST(JPEG, inst_idx); 446 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 447 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 448 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 449 data |= (JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1); 450 } else { 451 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 452 } 453 454 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 455 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 456 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 457 458 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 459 data |= (JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 460 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 461 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 462 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 463 } 464 465 /** 466 * jpeg_v4_0_3_start - start JPEG block 467 * 468 * @adev: amdgpu_device pointer 469 * 470 * Setup and start the JPEG block 471 */ 472 static int jpeg_v4_0_3_start(struct amdgpu_device *adev) 473 { 474 struct amdgpu_ring *ring; 475 int i, j, jpeg_inst; 476 477 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 478 jpeg_inst = GET_INST(JPEG, i); 479 480 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 481 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 482 SOC15_WAIT_ON_RREG( 483 JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 484 UVD_PGFSM_STATUS__UVDJ_PWR_ON 485 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 486 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 487 488 /* disable anti hang mechanism */ 489 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 490 regUVD_JPEG_POWER_STATUS), 491 0, ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 492 493 /* JPEG disable CGC */ 494 jpeg_v4_0_3_disable_clock_gating(adev, i); 495 496 /* MJPEG global tiling registers */ 497 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX8_ADDR_CONFIG, 498 adev->gfx.config.gb_addr_config); 499 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX10_ADDR_CONFIG, 500 adev->gfx.config.gb_addr_config); 501 502 /* enable JMI channel */ 503 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0, 504 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 505 506 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 507 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 508 509 ring = &adev->jpeg.inst[i].ring_dec[j]; 510 511 /* enable System Interrupt for JRBC */ 512 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 513 regJPEG_SYS_INT_EN), 514 JPEG_SYS_INT_EN__DJRBC0_MASK << j, 515 ~(JPEG_SYS_INT_EN__DJRBC0_MASK << j)); 516 517 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 518 regUVD_JMI0_UVD_LMI_JRBC_RB_VMID, 519 reg_offset, 0); 520 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 521 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 522 reg_offset, 523 (0x00000001L | 0x00000002L)); 524 WREG32_SOC15_OFFSET( 525 JPEG, jpeg_inst, 526 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW, 527 reg_offset, lower_32_bits(ring->gpu_addr)); 528 WREG32_SOC15_OFFSET( 529 JPEG, jpeg_inst, 530 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 531 reg_offset, upper_32_bits(ring->gpu_addr)); 532 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 533 regUVD_JRBC0_UVD_JRBC_RB_RPTR, 534 reg_offset, 0); 535 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 536 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 537 reg_offset, 0); 538 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 539 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 540 reg_offset, 0x00000002L); 541 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 542 regUVD_JRBC0_UVD_JRBC_RB_SIZE, 543 reg_offset, ring->ring_size / 4); 544 ring->wptr = RREG32_SOC15_OFFSET( 545 JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_RB_WPTR, 546 reg_offset); 547 } 548 } 549 550 return 0; 551 } 552 553 /** 554 * jpeg_v4_0_3_stop - stop JPEG block 555 * 556 * @adev: amdgpu_device pointer 557 * 558 * stop the JPEG block 559 */ 560 static int jpeg_v4_0_3_stop(struct amdgpu_device *adev) 561 { 562 int i, jpeg_inst; 563 564 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 565 jpeg_inst = GET_INST(JPEG, i); 566 /* reset JMI */ 567 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 568 UVD_JMI_CNTL__SOFT_RESET_MASK, 569 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 570 571 jpeg_v4_0_3_enable_clock_gating(adev, i); 572 573 /* enable anti hang mechanism */ 574 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 575 regUVD_JPEG_POWER_STATUS), 576 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 577 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 578 579 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 580 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 581 SOC15_WAIT_ON_RREG( 582 JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 583 UVD_PGFSM_STATUS__UVDJ_PWR_OFF 584 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 585 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 586 } 587 588 return 0; 589 } 590 591 /** 592 * jpeg_v4_0_3_dec_ring_get_rptr - get read pointer 593 * 594 * @ring: amdgpu_ring pointer 595 * 596 * Returns the current hardware read pointer 597 */ 598 static uint64_t jpeg_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring *ring) 599 { 600 struct amdgpu_device *adev = ring->adev; 601 602 return RREG32_SOC15_OFFSET( 603 JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR, 604 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); 605 } 606 607 /** 608 * jpeg_v4_0_3_dec_ring_get_wptr - get write pointer 609 * 610 * @ring: amdgpu_ring pointer 611 * 612 * Returns the current hardware write pointer 613 */ 614 static uint64_t jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring) 615 { 616 struct amdgpu_device *adev = ring->adev; 617 618 if (ring->use_doorbell) 619 return adev->wb.wb[ring->wptr_offs]; 620 else 621 return RREG32_SOC15_OFFSET( 622 JPEG, GET_INST(JPEG, ring->me), 623 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 624 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); 625 } 626 627 static void jpeg_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 628 { 629 /* JPEG engine access for HDP flush doesn't work when RRMT is enabled. 630 * This is a workaround to avoid any HDP flush through JPEG ring. 631 */ 632 } 633 634 /** 635 * jpeg_v4_0_3_dec_ring_set_wptr - set write pointer 636 * 637 * @ring: amdgpu_ring pointer 638 * 639 * Commits the write pointer to the hardware 640 */ 641 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring) 642 { 643 struct amdgpu_device *adev = ring->adev; 644 645 if (ring->use_doorbell) { 646 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 647 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 648 } else { 649 WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), 650 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 651 (ring->pipe ? (0x40 * ring->pipe - 0xc80) : 652 0), 653 lower_32_bits(ring->wptr)); 654 } 655 } 656 657 /** 658 * jpeg_v4_0_3_dec_ring_insert_start - insert a start command 659 * 660 * @ring: amdgpu_ring pointer 661 * 662 * Write a start command to the ring. 663 */ 664 void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring) 665 { 666 if (!amdgpu_sriov_vf(ring->adev)) { 667 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 668 0, 0, PACKETJ_TYPE0)); 669 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 670 } 671 672 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 673 0, 0, PACKETJ_TYPE0)); 674 amdgpu_ring_write(ring, 0x80004000); 675 } 676 677 /** 678 * jpeg_v4_0_3_dec_ring_insert_end - insert a end command 679 * 680 * @ring: amdgpu_ring pointer 681 * 682 * Write a end command to the ring. 683 */ 684 void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring) 685 { 686 if (!amdgpu_sriov_vf(ring->adev)) { 687 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 688 0, 0, PACKETJ_TYPE0)); 689 amdgpu_ring_write(ring, 0x62a04); 690 } 691 692 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 693 0, 0, PACKETJ_TYPE0)); 694 amdgpu_ring_write(ring, 0x00004000); 695 } 696 697 /** 698 * jpeg_v4_0_3_dec_ring_emit_fence - emit an fence & trap command 699 * 700 * @ring: amdgpu_ring pointer 701 * @addr: address 702 * @seq: sequence number 703 * @flags: fence related flags 704 * 705 * Write a fence and a trap command to the ring. 706 */ 707 void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 708 unsigned int flags) 709 { 710 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 711 712 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 713 0, 0, PACKETJ_TYPE0)); 714 amdgpu_ring_write(ring, seq); 715 716 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 717 0, 0, PACKETJ_TYPE0)); 718 amdgpu_ring_write(ring, seq); 719 720 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 721 0, 0, PACKETJ_TYPE0)); 722 amdgpu_ring_write(ring, lower_32_bits(addr)); 723 724 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 725 0, 0, PACKETJ_TYPE0)); 726 amdgpu_ring_write(ring, upper_32_bits(addr)); 727 728 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 729 0, 0, PACKETJ_TYPE0)); 730 amdgpu_ring_write(ring, 0x8); 731 732 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 733 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 734 amdgpu_ring_write(ring, 0); 735 736 if (ring->adev->jpeg.inst[ring->me].aid_id) { 737 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET, 738 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0)); 739 amdgpu_ring_write(ring, 0x4); 740 } else { 741 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 742 amdgpu_ring_write(ring, 0); 743 } 744 745 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 746 0, 0, PACKETJ_TYPE0)); 747 amdgpu_ring_write(ring, 0x3fbc); 748 749 if (ring->adev->jpeg.inst[ring->me].aid_id) { 750 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET, 751 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0)); 752 amdgpu_ring_write(ring, 0x0); 753 } else { 754 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 755 amdgpu_ring_write(ring, 0); 756 } 757 758 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 759 0, 0, PACKETJ_TYPE0)); 760 amdgpu_ring_write(ring, 0x1); 761 762 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 763 amdgpu_ring_write(ring, 0); 764 } 765 766 /** 767 * jpeg_v4_0_3_dec_ring_emit_ib - execute indirect buffer 768 * 769 * @ring: amdgpu_ring pointer 770 * @job: job to retrieve vmid from 771 * @ib: indirect buffer to execute 772 * @flags: unused 773 * 774 * Write ring commands to execute the indirect buffer. 775 */ 776 void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring, 777 struct amdgpu_job *job, 778 struct amdgpu_ib *ib, 779 uint32_t flags) 780 { 781 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 782 783 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 784 0, 0, PACKETJ_TYPE0)); 785 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 786 787 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 788 0, 0, PACKETJ_TYPE0)); 789 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 790 791 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 792 0, 0, PACKETJ_TYPE0)); 793 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 794 795 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 796 0, 0, PACKETJ_TYPE0)); 797 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 798 799 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 800 0, 0, PACKETJ_TYPE0)); 801 amdgpu_ring_write(ring, ib->length_dw); 802 803 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 804 0, 0, PACKETJ_TYPE0)); 805 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 806 807 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 808 0, 0, PACKETJ_TYPE0)); 809 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 810 811 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 812 amdgpu_ring_write(ring, 0); 813 814 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 815 0, 0, PACKETJ_TYPE0)); 816 amdgpu_ring_write(ring, 0x01400200); 817 818 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 819 0, 0, PACKETJ_TYPE0)); 820 amdgpu_ring_write(ring, 0x2); 821 822 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_STATUS_INTERNAL_OFFSET, 823 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 824 amdgpu_ring_write(ring, 0x2); 825 } 826 827 void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 828 uint32_t val, uint32_t mask) 829 { 830 uint32_t reg_offset; 831 832 /* For VF, only local offsets should be used */ 833 if (amdgpu_sriov_vf(ring->adev)) 834 reg = NORMALIZE_JPEG_REG_OFFSET(reg); 835 836 reg_offset = (reg << 2); 837 838 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 839 0, 0, PACKETJ_TYPE0)); 840 amdgpu_ring_write(ring, 0x01400200); 841 842 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 843 0, 0, PACKETJ_TYPE0)); 844 amdgpu_ring_write(ring, val); 845 846 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 847 0, 0, PACKETJ_TYPE0)); 848 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 849 amdgpu_ring_write(ring, 0); 850 amdgpu_ring_write(ring, 851 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 852 } else { 853 amdgpu_ring_write(ring, reg_offset); 854 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 855 0, 0, PACKETJ_TYPE3)); 856 } 857 amdgpu_ring_write(ring, mask); 858 } 859 860 void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 861 unsigned int vmid, uint64_t pd_addr) 862 { 863 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 864 uint32_t data0, data1, mask; 865 866 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 867 868 /* wait for register write */ 869 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 870 data1 = lower_32_bits(pd_addr); 871 mask = 0xffffffff; 872 jpeg_v4_0_3_dec_ring_emit_reg_wait(ring, data0, data1, mask); 873 } 874 875 void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 876 { 877 uint32_t reg_offset; 878 879 /* For VF, only local offsets should be used */ 880 if (amdgpu_sriov_vf(ring->adev)) 881 reg = NORMALIZE_JPEG_REG_OFFSET(reg); 882 883 reg_offset = (reg << 2); 884 885 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 886 0, 0, PACKETJ_TYPE0)); 887 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 888 amdgpu_ring_write(ring, 0); 889 amdgpu_ring_write(ring, 890 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 891 } else { 892 amdgpu_ring_write(ring, reg_offset); 893 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 894 0, 0, PACKETJ_TYPE0)); 895 } 896 amdgpu_ring_write(ring, val); 897 } 898 899 void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) 900 { 901 int i; 902 903 WARN_ON(ring->wptr % 2 || count % 2); 904 905 for (i = 0; i < count / 2; i++) { 906 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 907 amdgpu_ring_write(ring, 0); 908 } 909 } 910 911 static bool jpeg_v4_0_3_is_idle(void *handle) 912 { 913 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 914 bool ret = false; 915 int i, j; 916 917 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 918 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 919 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 920 921 ret &= ((RREG32_SOC15_OFFSET( 922 JPEG, GET_INST(JPEG, i), 923 regUVD_JRBC0_UVD_JRBC_STATUS, 924 reg_offset) & 925 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 926 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 927 } 928 } 929 930 return ret; 931 } 932 933 static int jpeg_v4_0_3_wait_for_idle(void *handle) 934 { 935 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 936 int ret = 0; 937 int i, j; 938 939 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 940 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 941 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 942 943 ret &= SOC15_WAIT_ON_RREG_OFFSET( 944 JPEG, GET_INST(JPEG, i), 945 regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset, 946 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 947 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 948 } 949 } 950 return ret; 951 } 952 953 static int jpeg_v4_0_3_set_clockgating_state(void *handle, 954 enum amd_clockgating_state state) 955 { 956 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 957 bool enable = state == AMD_CG_STATE_GATE; 958 int i; 959 960 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 961 if (enable) { 962 if (!jpeg_v4_0_3_is_idle(handle)) 963 return -EBUSY; 964 jpeg_v4_0_3_enable_clock_gating(adev, i); 965 } else { 966 jpeg_v4_0_3_disable_clock_gating(adev, i); 967 } 968 } 969 return 0; 970 } 971 972 static int jpeg_v4_0_3_set_powergating_state(void *handle, 973 enum amd_powergating_state state) 974 { 975 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 976 int ret; 977 978 if (amdgpu_sriov_vf(adev)) { 979 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; 980 return 0; 981 } 982 983 if (state == adev->jpeg.cur_state) 984 return 0; 985 986 if (state == AMD_PG_STATE_GATE) 987 ret = jpeg_v4_0_3_stop(adev); 988 else 989 ret = jpeg_v4_0_3_start(adev); 990 991 if (!ret) 992 adev->jpeg.cur_state = state; 993 994 return ret; 995 } 996 997 static int jpeg_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 998 struct amdgpu_irq_src *source, 999 unsigned int type, 1000 enum amdgpu_interrupt_state state) 1001 { 1002 return 0; 1003 } 1004 1005 static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1006 struct amdgpu_irq_src *source, 1007 struct amdgpu_iv_entry *entry) 1008 { 1009 uint32_t i, inst; 1010 1011 i = node_id_to_phys_map[entry->node_id]; 1012 DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n"); 1013 1014 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) 1015 if (adev->jpeg.inst[inst].aid_id == i) 1016 break; 1017 1018 if (inst >= adev->jpeg.num_jpeg_inst) { 1019 dev_WARN_ONCE(adev->dev, 1, 1020 "Interrupt received for unknown JPEG instance %d", 1021 entry->node_id); 1022 return 0; 1023 } 1024 1025 switch (entry->src_id) { 1026 case VCN_4_0__SRCID__JPEG_DECODE: 1027 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); 1028 break; 1029 case VCN_4_0__SRCID__JPEG1_DECODE: 1030 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]); 1031 break; 1032 case VCN_4_0__SRCID__JPEG2_DECODE: 1033 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]); 1034 break; 1035 case VCN_4_0__SRCID__JPEG3_DECODE: 1036 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]); 1037 break; 1038 case VCN_4_0__SRCID__JPEG4_DECODE: 1039 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]); 1040 break; 1041 case VCN_4_0__SRCID__JPEG5_DECODE: 1042 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]); 1043 break; 1044 case VCN_4_0__SRCID__JPEG6_DECODE: 1045 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]); 1046 break; 1047 case VCN_4_0__SRCID__JPEG7_DECODE: 1048 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]); 1049 break; 1050 default: 1051 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1052 entry->src_id, entry->src_data[0]); 1053 break; 1054 } 1055 1056 return 0; 1057 } 1058 1059 static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = { 1060 .name = "jpeg_v4_0_3", 1061 .early_init = jpeg_v4_0_3_early_init, 1062 .late_init = NULL, 1063 .sw_init = jpeg_v4_0_3_sw_init, 1064 .sw_fini = jpeg_v4_0_3_sw_fini, 1065 .hw_init = jpeg_v4_0_3_hw_init, 1066 .hw_fini = jpeg_v4_0_3_hw_fini, 1067 .suspend = jpeg_v4_0_3_suspend, 1068 .resume = jpeg_v4_0_3_resume, 1069 .is_idle = jpeg_v4_0_3_is_idle, 1070 .wait_for_idle = jpeg_v4_0_3_wait_for_idle, 1071 .check_soft_reset = NULL, 1072 .pre_soft_reset = NULL, 1073 .soft_reset = NULL, 1074 .post_soft_reset = NULL, 1075 .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state, 1076 .set_powergating_state = jpeg_v4_0_3_set_powergating_state, 1077 .dump_ip_state = NULL, 1078 .print_ip_state = NULL, 1079 }; 1080 1081 static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { 1082 .type = AMDGPU_RING_TYPE_VCN_JPEG, 1083 .align_mask = 0xf, 1084 .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr, 1085 .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr, 1086 .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr, 1087 .emit_frame_size = 1088 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1089 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1090 8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */ 1091 22 + 22 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */ 1092 8 + 16, 1093 .emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */ 1094 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, 1095 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, 1096 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, 1097 .emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush, 1098 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 1099 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 1100 .insert_nop = jpeg_v4_0_3_dec_ring_nop, 1101 .insert_start = jpeg_v4_0_3_dec_ring_insert_start, 1102 .insert_end = jpeg_v4_0_3_dec_ring_insert_end, 1103 .pad_ib = amdgpu_ring_generic_pad_ib, 1104 .begin_use = amdgpu_jpeg_ring_begin_use, 1105 .end_use = amdgpu_jpeg_ring_end_use, 1106 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, 1107 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, 1108 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1109 }; 1110 1111 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev) 1112 { 1113 int i, j, jpeg_inst; 1114 1115 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1116 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 1117 adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs; 1118 adev->jpeg.inst[i].ring_dec[j].me = i; 1119 adev->jpeg.inst[i].ring_dec[j].pipe = j; 1120 } 1121 jpeg_inst = GET_INST(JPEG, i); 1122 adev->jpeg.inst[i].aid_id = 1123 jpeg_inst / adev->jpeg.num_inst_per_aid; 1124 } 1125 } 1126 1127 static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = { 1128 .set = jpeg_v4_0_3_set_interrupt_state, 1129 .process = jpeg_v4_0_3_process_interrupt, 1130 }; 1131 1132 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1133 { 1134 int i; 1135 1136 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1137 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; 1138 } 1139 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs; 1140 } 1141 1142 const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block = { 1143 .type = AMD_IP_BLOCK_TYPE_JPEG, 1144 .major = 4, 1145 .minor = 0, 1146 .rev = 3, 1147 .funcs = &jpeg_v4_0_3_ip_funcs, 1148 }; 1149 1150 static const struct amdgpu_ras_err_status_reg_entry jpeg_v4_0_3_ue_reg_list[] = { 1151 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0S, regVCN_UE_ERR_STATUS_HI_JPEG0S), 1152 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0S"}, 1153 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0D, regVCN_UE_ERR_STATUS_HI_JPEG0D), 1154 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0D"}, 1155 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1S, regVCN_UE_ERR_STATUS_HI_JPEG1S), 1156 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1S"}, 1157 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1D, regVCN_UE_ERR_STATUS_HI_JPEG1D), 1158 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1D"}, 1159 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2S, regVCN_UE_ERR_STATUS_HI_JPEG2S), 1160 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2S"}, 1161 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2D, regVCN_UE_ERR_STATUS_HI_JPEG2D), 1162 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2D"}, 1163 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3S, regVCN_UE_ERR_STATUS_HI_JPEG3S), 1164 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3S"}, 1165 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3D, regVCN_UE_ERR_STATUS_HI_JPEG3D), 1166 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3D"}, 1167 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4S, regVCN_UE_ERR_STATUS_HI_JPEG4S), 1168 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4S"}, 1169 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4D, regVCN_UE_ERR_STATUS_HI_JPEG4D), 1170 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4D"}, 1171 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5S, regVCN_UE_ERR_STATUS_HI_JPEG5S), 1172 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5S"}, 1173 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5D, regVCN_UE_ERR_STATUS_HI_JPEG5D), 1174 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5D"}, 1175 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6S, regVCN_UE_ERR_STATUS_HI_JPEG6S), 1176 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6S"}, 1177 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6D, regVCN_UE_ERR_STATUS_HI_JPEG6D), 1178 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6D"}, 1179 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7S, regVCN_UE_ERR_STATUS_HI_JPEG7S), 1180 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7S"}, 1181 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7D, regVCN_UE_ERR_STATUS_HI_JPEG7D), 1182 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7D"}, 1183 }; 1184 1185 static void jpeg_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1186 uint32_t jpeg_inst, 1187 void *ras_err_status) 1188 { 1189 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1190 1191 /* jpeg v4_0_3 only support uncorrectable errors */ 1192 amdgpu_ras_inst_query_ras_error_count(adev, 1193 jpeg_v4_0_3_ue_reg_list, 1194 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1195 NULL, 0, GET_INST(VCN, jpeg_inst), 1196 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1197 &err_data->ue_count); 1198 } 1199 1200 static void jpeg_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1201 void *ras_err_status) 1202 { 1203 uint32_t i; 1204 1205 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1206 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1207 return; 1208 } 1209 1210 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1211 jpeg_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1212 } 1213 1214 static void jpeg_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1215 uint32_t jpeg_inst) 1216 { 1217 amdgpu_ras_inst_reset_ras_error_count(adev, 1218 jpeg_v4_0_3_ue_reg_list, 1219 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1220 GET_INST(VCN, jpeg_inst)); 1221 } 1222 1223 static void jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1224 { 1225 uint32_t i; 1226 1227 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1228 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1229 return; 1230 } 1231 1232 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1233 jpeg_v4_0_3_inst_reset_ras_error_count(adev, i); 1234 } 1235 1236 static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = { 1237 .query_ras_error_count = jpeg_v4_0_3_query_ras_error_count, 1238 .reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count, 1239 }; 1240 1241 static struct amdgpu_jpeg_ras jpeg_v4_0_3_ras = { 1242 .ras_block = { 1243 .hw_ops = &jpeg_v4_0_3_ras_hw_ops, 1244 }, 1245 }; 1246 1247 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 1248 { 1249 adev->jpeg.ras = &jpeg_v4_0_3_ras; 1250 } 1251