1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "soc15.h" 27 #include "soc15d.h" 28 #include "jpeg_v2_0.h" 29 #include "jpeg_v4_0_3.h" 30 #include "mmsch_v4_0_3.h" 31 32 #include "vcn/vcn_4_0_3_offset.h" 33 #include "vcn/vcn_4_0_3_sh_mask.h" 34 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 35 36 #define NORMALIZE_JPEG_REG_OFFSET(offset) \ 37 (offset & 0x1FFFF) 38 39 enum jpeg_engin_status { 40 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0, 41 UVD_PGFSM_STATUS__UVDJ_PWR_OFF = 2, 42 }; 43 44 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev); 45 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 46 static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 47 enum amd_powergating_state state); 48 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 49 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring); 50 51 static int amdgpu_ih_srcid_jpeg[] = { 52 VCN_4_0__SRCID__JPEG_DECODE, 53 VCN_4_0__SRCID__JPEG1_DECODE, 54 VCN_4_0__SRCID__JPEG2_DECODE, 55 VCN_4_0__SRCID__JPEG3_DECODE, 56 VCN_4_0__SRCID__JPEG4_DECODE, 57 VCN_4_0__SRCID__JPEG5_DECODE, 58 VCN_4_0__SRCID__JPEG6_DECODE, 59 VCN_4_0__SRCID__JPEG7_DECODE 60 }; 61 62 static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) 63 { 64 return (adev->jpeg.caps & AMDGPU_JPEG_CAPS(RRMT_ENABLED)) == 0; 65 } 66 67 /** 68 * jpeg_v4_0_3_early_init - set function pointers 69 * 70 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 71 * 72 * Set ring and irq function pointers 73 */ 74 static int jpeg_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) 75 { 76 struct amdgpu_device *adev = ip_block->adev; 77 78 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3; 79 80 jpeg_v4_0_3_set_dec_ring_funcs(adev); 81 jpeg_v4_0_3_set_irq_funcs(adev); 82 jpeg_v4_0_3_set_ras_funcs(adev); 83 84 return 0; 85 } 86 87 /** 88 * jpeg_v4_0_3_sw_init - sw init for JPEG block 89 * 90 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 91 * 92 * Load firmware and sw initialization 93 */ 94 static int jpeg_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 95 { 96 struct amdgpu_device *adev = ip_block->adev; 97 struct amdgpu_ring *ring; 98 int i, j, r, jpeg_inst; 99 100 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 101 /* JPEG TRAP */ 102 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 103 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); 104 if (r) 105 return r; 106 } 107 108 r = amdgpu_jpeg_sw_init(adev); 109 if (r) 110 return r; 111 112 r = amdgpu_jpeg_resume(adev); 113 if (r) 114 return r; 115 116 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 117 jpeg_inst = GET_INST(JPEG, i); 118 119 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 120 ring = &adev->jpeg.inst[i].ring_dec[j]; 121 ring->use_doorbell = true; 122 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); 123 if (!amdgpu_sriov_vf(adev)) { 124 ring->doorbell_index = 125 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 126 1 + j + 9 * jpeg_inst; 127 } else { 128 if (j < 4) 129 ring->doorbell_index = 130 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 131 4 + j + 32 * jpeg_inst; 132 else 133 ring->doorbell_index = 134 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 135 8 + j + 32 * jpeg_inst; 136 } 137 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); 138 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 139 AMDGPU_RING_PRIO_DEFAULT, NULL); 140 if (r) 141 return r; 142 143 adev->jpeg.internal.jpeg_pitch[j] = 144 regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET; 145 adev->jpeg.inst[i].external.jpeg_pitch[j] = 146 SOC15_REG_OFFSET1( 147 JPEG, jpeg_inst, 148 regUVD_JRBC0_UVD_JRBC_SCRATCH0, 149 (j ? (0x40 * j - 0xc80) : 0)); 150 } 151 } 152 153 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 154 r = amdgpu_jpeg_ras_sw_init(adev); 155 if (r) { 156 dev_err(adev->dev, "Failed to initialize jpeg ras block!\n"); 157 return r; 158 } 159 } 160 161 /* TODO: Add queue reset mask when FW fully supports it */ 162 adev->jpeg.supported_reset = 163 amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]); 164 r = amdgpu_jpeg_sysfs_reset_mask_init(adev); 165 if (r) 166 return r; 167 168 return 0; 169 } 170 171 /** 172 * jpeg_v4_0_3_sw_fini - sw fini for JPEG block 173 * 174 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 175 * 176 * JPEG suspend and free up sw allocation 177 */ 178 static int jpeg_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) 179 { 180 struct amdgpu_device *adev = ip_block->adev; 181 int r; 182 183 r = amdgpu_jpeg_suspend(adev); 184 if (r) 185 return r; 186 187 amdgpu_jpeg_sysfs_reset_mask_fini(adev); 188 r = amdgpu_jpeg_sw_fini(adev); 189 190 return r; 191 } 192 193 static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev) 194 { 195 struct amdgpu_ring *ring; 196 uint64_t ctx_addr; 197 uint32_t param, resp, expected; 198 uint32_t tmp, timeout; 199 200 struct amdgpu_mm_table *table = &adev->virt.mm_table; 201 uint32_t *table_loc; 202 uint32_t table_size; 203 uint32_t size, size_dw, item_offset; 204 uint32_t init_status; 205 int i, j, jpeg_inst; 206 207 struct mmsch_v4_0_cmd_direct_write 208 direct_wt = { {0} }; 209 struct mmsch_v4_0_cmd_end end = { {0} }; 210 struct mmsch_v4_0_3_init_header header; 211 212 direct_wt.cmd_header.command_type = 213 MMSCH_COMMAND__DIRECT_REG_WRITE; 214 end.cmd_header.command_type = 215 MMSCH_COMMAND__END; 216 217 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 218 jpeg_inst = GET_INST(JPEG, i); 219 220 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 221 header.version = MMSCH_VERSION; 222 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 223 224 table_loc = (uint32_t *)table->cpu_addr; 225 table_loc += header.total_size; 226 227 item_offset = header.total_size; 228 229 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) { 230 ring = &adev->jpeg.inst[i].ring_dec[j]; 231 table_size = 0; 232 233 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW); 234 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr)); 235 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH); 236 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr)); 237 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE); 238 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4); 239 240 if (j <= 3) { 241 header.mjpegdec0[j].table_offset = item_offset; 242 header.mjpegdec0[j].init_status = 0; 243 header.mjpegdec0[j].table_size = table_size; 244 } else { 245 header.mjpegdec1[j - 4].table_offset = item_offset; 246 header.mjpegdec1[j - 4].init_status = 0; 247 header.mjpegdec1[j - 4].table_size = table_size; 248 } 249 header.total_size += table_size; 250 item_offset += table_size; 251 } 252 253 MMSCH_V4_0_INSERT_END(); 254 255 /* send init table to MMSCH */ 256 size = sizeof(struct mmsch_v4_0_3_init_header); 257 table_loc = (uint32_t *)table->cpu_addr; 258 memcpy((void *)table_loc, &header, size); 259 260 ctx_addr = table->gpu_addr; 261 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 262 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 263 264 tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID); 265 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 266 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 267 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp); 268 269 size = header.total_size; 270 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size); 271 272 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0); 273 274 param = 0x00000001; 275 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param); 276 tmp = 0; 277 timeout = 1000; 278 resp = 0; 279 expected = MMSCH_VF_MAILBOX_RESP__OK; 280 init_status = 281 ((struct mmsch_v4_0_3_init_header *)(table_loc))->mjpegdec0[i].init_status; 282 while (resp != expected) { 283 resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP); 284 285 if (resp != 0) 286 break; 287 udelay(10); 288 tmp = tmp + 10; 289 if (tmp >= timeout) { 290 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 291 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 292 "(expected=0x%08x, readback=0x%08x)\n", 293 tmp, expected, resp); 294 return -EBUSY; 295 } 296 } 297 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE && 298 init_status != MMSCH_VF_ENGINE_STATUS__PASS) 299 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", 300 resp, init_status); 301 302 } 303 return 0; 304 } 305 306 /** 307 * jpeg_v4_0_3_hw_init - start and test JPEG block 308 * 309 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 310 * 311 */ 312 static int jpeg_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) 313 { 314 struct amdgpu_device *adev = ip_block->adev; 315 struct amdgpu_ring *ring; 316 int i, j, r, jpeg_inst; 317 318 if (amdgpu_sriov_vf(adev)) { 319 r = jpeg_v4_0_3_start_sriov(adev); 320 if (r) 321 return r; 322 323 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 324 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 325 ring = &adev->jpeg.inst[i].ring_dec[j]; 326 ring->wptr = 0; 327 ring->wptr_old = 0; 328 jpeg_v4_0_3_dec_ring_set_wptr(ring); 329 ring->sched.ready = true; 330 } 331 } 332 } else { 333 /* This flag is not set for VF, assumed to be disabled always */ 334 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 335 0x100) 336 adev->jpeg.caps |= AMDGPU_JPEG_CAPS(RRMT_ENABLED); 337 338 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 339 jpeg_inst = GET_INST(JPEG, i); 340 341 ring = adev->jpeg.inst[i].ring_dec; 342 343 if (ring->use_doorbell) 344 adev->nbio.funcs->vcn_doorbell_range( 345 adev, ring->use_doorbell, 346 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 347 9 * jpeg_inst, 348 adev->jpeg.inst[i].aid_id); 349 350 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 351 ring = &adev->jpeg.inst[i].ring_dec[j]; 352 if (ring->use_doorbell) 353 WREG32_SOC15_OFFSET( 354 VCN, GET_INST(VCN, i), 355 regVCN_JPEG_DB_CTRL, 356 (ring->pipe ? (ring->pipe - 0x15) : 0), 357 ring->doorbell_index 358 << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 359 VCN_JPEG_DB_CTRL__EN_MASK); 360 r = amdgpu_ring_test_helper(ring); 361 if (r) 362 return r; 363 } 364 } 365 } 366 367 return 0; 368 } 369 370 /** 371 * jpeg_v4_0_3_hw_fini - stop the hardware block 372 * 373 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 374 * 375 * Stop the JPEG block, mark ring as not ready any more 376 */ 377 static int jpeg_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) 378 { 379 struct amdgpu_device *adev = ip_block->adev; 380 int ret = 0; 381 382 cancel_delayed_work_sync(&adev->jpeg.idle_work); 383 384 if (!amdgpu_sriov_vf(adev)) { 385 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) 386 ret = jpeg_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 387 } 388 389 return ret; 390 } 391 392 /** 393 * jpeg_v4_0_3_suspend - suspend JPEG block 394 * 395 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 396 * 397 * HW fini and suspend JPEG block 398 */ 399 static int jpeg_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) 400 { 401 int r; 402 403 r = jpeg_v4_0_3_hw_fini(ip_block); 404 if (r) 405 return r; 406 407 r = amdgpu_jpeg_suspend(ip_block->adev); 408 409 return r; 410 } 411 412 /** 413 * jpeg_v4_0_3_resume - resume JPEG block 414 * 415 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 416 * 417 * Resume firmware and hw init JPEG block 418 */ 419 static int jpeg_v4_0_3_resume(struct amdgpu_ip_block *ip_block) 420 { 421 int r; 422 423 r = amdgpu_jpeg_resume(ip_block->adev); 424 if (r) 425 return r; 426 427 r = jpeg_v4_0_3_hw_init(ip_block); 428 429 return r; 430 } 431 432 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) 433 { 434 int i, jpeg_inst; 435 uint32_t data; 436 437 jpeg_inst = GET_INST(JPEG, inst_idx); 438 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 439 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 440 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 441 data &= (~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1)); 442 } else { 443 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 444 } 445 446 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 447 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 448 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 449 450 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 451 data &= ~(JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 452 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 453 data &= ~(JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 454 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 455 } 456 457 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) 458 { 459 int i, jpeg_inst; 460 uint32_t data; 461 462 jpeg_inst = GET_INST(JPEG, inst_idx); 463 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 464 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 465 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 466 data |= (JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1); 467 } else { 468 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 469 } 470 471 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 472 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 473 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 474 475 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 476 data |= (JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 477 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 478 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 479 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 480 } 481 482 /** 483 * jpeg_v4_0_3_start - start JPEG block 484 * 485 * @adev: amdgpu_device pointer 486 * 487 * Setup and start the JPEG block 488 */ 489 static int jpeg_v4_0_3_start(struct amdgpu_device *adev) 490 { 491 struct amdgpu_ring *ring; 492 int i, j, jpeg_inst; 493 494 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 495 jpeg_inst = GET_INST(JPEG, i); 496 497 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 498 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 499 SOC15_WAIT_ON_RREG( 500 JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 501 UVD_PGFSM_STATUS__UVDJ_PWR_ON 502 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 503 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 504 505 /* disable anti hang mechanism */ 506 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 507 regUVD_JPEG_POWER_STATUS), 508 0, ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 509 510 /* JPEG disable CGC */ 511 jpeg_v4_0_3_disable_clock_gating(adev, i); 512 513 /* MJPEG global tiling registers */ 514 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX8_ADDR_CONFIG, 515 adev->gfx.config.gb_addr_config); 516 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX10_ADDR_CONFIG, 517 adev->gfx.config.gb_addr_config); 518 519 /* enable JMI channel */ 520 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0, 521 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 522 523 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 524 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 525 526 ring = &adev->jpeg.inst[i].ring_dec[j]; 527 528 /* enable System Interrupt for JRBC */ 529 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 530 regJPEG_SYS_INT_EN), 531 JPEG_SYS_INT_EN__DJRBC0_MASK << j, 532 ~(JPEG_SYS_INT_EN__DJRBC0_MASK << j)); 533 534 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 535 regUVD_JMI0_UVD_LMI_JRBC_RB_VMID, 536 reg_offset, 0); 537 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 538 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 539 reg_offset, 540 (0x00000001L | 0x00000002L)); 541 WREG32_SOC15_OFFSET( 542 JPEG, jpeg_inst, 543 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW, 544 reg_offset, lower_32_bits(ring->gpu_addr)); 545 WREG32_SOC15_OFFSET( 546 JPEG, jpeg_inst, 547 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 548 reg_offset, upper_32_bits(ring->gpu_addr)); 549 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 550 regUVD_JRBC0_UVD_JRBC_RB_RPTR, 551 reg_offset, 0); 552 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 553 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 554 reg_offset, 0); 555 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 556 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 557 reg_offset, 0x00000002L); 558 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 559 regUVD_JRBC0_UVD_JRBC_RB_SIZE, 560 reg_offset, ring->ring_size / 4); 561 ring->wptr = RREG32_SOC15_OFFSET( 562 JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_RB_WPTR, 563 reg_offset); 564 } 565 } 566 567 return 0; 568 } 569 570 /** 571 * jpeg_v4_0_3_stop - stop JPEG block 572 * 573 * @adev: amdgpu_device pointer 574 * 575 * stop the JPEG block 576 */ 577 static int jpeg_v4_0_3_stop(struct amdgpu_device *adev) 578 { 579 int i, jpeg_inst; 580 581 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 582 jpeg_inst = GET_INST(JPEG, i); 583 /* reset JMI */ 584 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 585 UVD_JMI_CNTL__SOFT_RESET_MASK, 586 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 587 588 jpeg_v4_0_3_enable_clock_gating(adev, i); 589 590 /* enable anti hang mechanism */ 591 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 592 regUVD_JPEG_POWER_STATUS), 593 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 594 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 595 596 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 597 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 598 SOC15_WAIT_ON_RREG( 599 JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 600 UVD_PGFSM_STATUS__UVDJ_PWR_OFF 601 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 602 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 603 } 604 605 return 0; 606 } 607 608 /** 609 * jpeg_v4_0_3_dec_ring_get_rptr - get read pointer 610 * 611 * @ring: amdgpu_ring pointer 612 * 613 * Returns the current hardware read pointer 614 */ 615 static uint64_t jpeg_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring *ring) 616 { 617 struct amdgpu_device *adev = ring->adev; 618 619 return RREG32_SOC15_OFFSET( 620 JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR, 621 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); 622 } 623 624 /** 625 * jpeg_v4_0_3_dec_ring_get_wptr - get write pointer 626 * 627 * @ring: amdgpu_ring pointer 628 * 629 * Returns the current hardware write pointer 630 */ 631 static uint64_t jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring) 632 { 633 struct amdgpu_device *adev = ring->adev; 634 635 if (ring->use_doorbell) 636 return adev->wb.wb[ring->wptr_offs]; 637 else 638 return RREG32_SOC15_OFFSET( 639 JPEG, GET_INST(JPEG, ring->me), 640 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 641 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); 642 } 643 644 static void jpeg_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 645 { 646 /* JPEG engine access for HDP flush doesn't work when RRMT is enabled. 647 * This is a workaround to avoid any HDP flush through JPEG ring. 648 */ 649 } 650 651 /** 652 * jpeg_v4_0_3_dec_ring_set_wptr - set write pointer 653 * 654 * @ring: amdgpu_ring pointer 655 * 656 * Commits the write pointer to the hardware 657 */ 658 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring) 659 { 660 struct amdgpu_device *adev = ring->adev; 661 662 if (ring->use_doorbell) { 663 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 664 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 665 } else { 666 WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), 667 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 668 (ring->pipe ? (0x40 * ring->pipe - 0xc80) : 669 0), 670 lower_32_bits(ring->wptr)); 671 } 672 } 673 674 /** 675 * jpeg_v4_0_3_dec_ring_insert_start - insert a start command 676 * 677 * @ring: amdgpu_ring pointer 678 * 679 * Write a start command to the ring. 680 */ 681 void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring) 682 { 683 if (!amdgpu_sriov_vf(ring->adev)) { 684 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 685 0, 0, PACKETJ_TYPE0)); 686 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 687 688 amdgpu_ring_write(ring, 689 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, 690 0, PACKETJ_TYPE0)); 691 amdgpu_ring_write(ring, 0x80004000); 692 } 693 } 694 695 /** 696 * jpeg_v4_0_3_dec_ring_insert_end - insert a end command 697 * 698 * @ring: amdgpu_ring pointer 699 * 700 * Write a end command to the ring. 701 */ 702 void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring) 703 { 704 if (!amdgpu_sriov_vf(ring->adev)) { 705 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 706 0, 0, PACKETJ_TYPE0)); 707 amdgpu_ring_write(ring, 0x62a04); 708 709 amdgpu_ring_write(ring, 710 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, 711 0, PACKETJ_TYPE0)); 712 amdgpu_ring_write(ring, 0x00004000); 713 } 714 } 715 716 /** 717 * jpeg_v4_0_3_dec_ring_emit_fence - emit an fence & trap command 718 * 719 * @ring: amdgpu_ring pointer 720 * @addr: address 721 * @seq: sequence number 722 * @flags: fence related flags 723 * 724 * Write a fence and a trap command to the ring. 725 */ 726 void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 727 unsigned int flags) 728 { 729 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 730 731 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 732 0, 0, PACKETJ_TYPE0)); 733 amdgpu_ring_write(ring, seq); 734 735 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 736 0, 0, PACKETJ_TYPE0)); 737 amdgpu_ring_write(ring, seq); 738 739 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 740 0, 0, PACKETJ_TYPE0)); 741 amdgpu_ring_write(ring, lower_32_bits(addr)); 742 743 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 744 0, 0, PACKETJ_TYPE0)); 745 amdgpu_ring_write(ring, upper_32_bits(addr)); 746 747 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 748 0, 0, PACKETJ_TYPE0)); 749 amdgpu_ring_write(ring, 0x8); 750 751 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 752 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 753 amdgpu_ring_write(ring, 0); 754 755 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 756 amdgpu_ring_write(ring, 0); 757 758 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 759 amdgpu_ring_write(ring, 0); 760 761 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 762 amdgpu_ring_write(ring, 0); 763 } 764 765 /** 766 * jpeg_v4_0_3_dec_ring_emit_ib - execute indirect buffer 767 * 768 * @ring: amdgpu_ring pointer 769 * @job: job to retrieve vmid from 770 * @ib: indirect buffer to execute 771 * @flags: unused 772 * 773 * Write ring commands to execute the indirect buffer. 774 */ 775 void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring, 776 struct amdgpu_job *job, 777 struct amdgpu_ib *ib, 778 uint32_t flags) 779 { 780 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 781 782 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 783 0, 0, PACKETJ_TYPE0)); 784 785 if (ring->funcs->parse_cs) 786 amdgpu_ring_write(ring, 0); 787 else 788 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 789 790 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 791 0, 0, PACKETJ_TYPE0)); 792 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 793 794 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 795 0, 0, PACKETJ_TYPE0)); 796 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 797 798 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 799 0, 0, PACKETJ_TYPE0)); 800 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 801 802 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 803 0, 0, PACKETJ_TYPE0)); 804 amdgpu_ring_write(ring, ib->length_dw); 805 806 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 807 0, 0, PACKETJ_TYPE0)); 808 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 809 810 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 811 0, 0, PACKETJ_TYPE0)); 812 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 813 814 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 815 amdgpu_ring_write(ring, 0); 816 817 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 818 0, 0, PACKETJ_TYPE0)); 819 amdgpu_ring_write(ring, 0x01400200); 820 821 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 822 0, 0, PACKETJ_TYPE0)); 823 amdgpu_ring_write(ring, 0x2); 824 825 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_STATUS_INTERNAL_OFFSET, 826 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 827 amdgpu_ring_write(ring, 0x2); 828 } 829 830 void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 831 uint32_t val, uint32_t mask) 832 { 833 uint32_t reg_offset; 834 835 /* Use normalized offsets if required */ 836 if (jpeg_v4_0_3_normalizn_reqd(ring->adev)) 837 reg = NORMALIZE_JPEG_REG_OFFSET(reg); 838 839 reg_offset = (reg << 2); 840 841 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 842 0, 0, PACKETJ_TYPE0)); 843 amdgpu_ring_write(ring, 0x01400200); 844 845 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 846 0, 0, PACKETJ_TYPE0)); 847 amdgpu_ring_write(ring, val); 848 849 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 850 0, 0, PACKETJ_TYPE0)); 851 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 852 amdgpu_ring_write(ring, 0); 853 amdgpu_ring_write(ring, 854 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 855 } else { 856 amdgpu_ring_write(ring, reg_offset); 857 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 858 0, 0, PACKETJ_TYPE3)); 859 } 860 amdgpu_ring_write(ring, mask); 861 } 862 863 void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 864 unsigned int vmid, uint64_t pd_addr) 865 { 866 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 867 uint32_t data0, data1, mask; 868 869 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 870 871 /* wait for register write */ 872 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 873 data1 = lower_32_bits(pd_addr); 874 mask = 0xffffffff; 875 jpeg_v4_0_3_dec_ring_emit_reg_wait(ring, data0, data1, mask); 876 } 877 878 void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 879 { 880 uint32_t reg_offset; 881 882 /* Use normalized offsets if required */ 883 if (jpeg_v4_0_3_normalizn_reqd(ring->adev)) 884 reg = NORMALIZE_JPEG_REG_OFFSET(reg); 885 886 reg_offset = (reg << 2); 887 888 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 889 0, 0, PACKETJ_TYPE0)); 890 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 891 amdgpu_ring_write(ring, 0); 892 amdgpu_ring_write(ring, 893 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 894 } else { 895 amdgpu_ring_write(ring, reg_offset); 896 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 897 0, 0, PACKETJ_TYPE0)); 898 } 899 amdgpu_ring_write(ring, val); 900 } 901 902 void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) 903 { 904 int i; 905 906 WARN_ON(ring->wptr % 2 || count % 2); 907 908 for (i = 0; i < count / 2; i++) { 909 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 910 amdgpu_ring_write(ring, 0); 911 } 912 } 913 914 static bool jpeg_v4_0_3_is_idle(void *handle) 915 { 916 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 917 bool ret = false; 918 int i, j; 919 920 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 921 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 922 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 923 924 ret &= ((RREG32_SOC15_OFFSET( 925 JPEG, GET_INST(JPEG, i), 926 regUVD_JRBC0_UVD_JRBC_STATUS, 927 reg_offset) & 928 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 929 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 930 } 931 } 932 933 return ret; 934 } 935 936 static int jpeg_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 937 { 938 struct amdgpu_device *adev = ip_block->adev; 939 int ret = 0; 940 int i, j; 941 942 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 943 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 944 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 945 946 ret &= SOC15_WAIT_ON_RREG_OFFSET( 947 JPEG, GET_INST(JPEG, i), 948 regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset, 949 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 950 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 951 } 952 } 953 return ret; 954 } 955 956 static int jpeg_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 957 enum amd_clockgating_state state) 958 { 959 struct amdgpu_device *adev = ip_block->adev; 960 bool enable = state == AMD_CG_STATE_GATE; 961 int i; 962 963 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 964 if (enable) { 965 if (!jpeg_v4_0_3_is_idle(adev)) 966 return -EBUSY; 967 jpeg_v4_0_3_enable_clock_gating(adev, i); 968 } else { 969 jpeg_v4_0_3_disable_clock_gating(adev, i); 970 } 971 } 972 return 0; 973 } 974 975 static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 976 enum amd_powergating_state state) 977 { 978 struct amdgpu_device *adev = ip_block->adev; 979 int ret; 980 981 if (amdgpu_sriov_vf(adev)) { 982 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; 983 return 0; 984 } 985 986 if (state == adev->jpeg.cur_state) 987 return 0; 988 989 if (state == AMD_PG_STATE_GATE) 990 ret = jpeg_v4_0_3_stop(adev); 991 else 992 ret = jpeg_v4_0_3_start(adev); 993 994 if (!ret) 995 adev->jpeg.cur_state = state; 996 997 return ret; 998 } 999 1000 static int jpeg_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 1001 struct amdgpu_irq_src *source, 1002 unsigned int type, 1003 enum amdgpu_interrupt_state state) 1004 { 1005 return 0; 1006 } 1007 1008 static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1009 struct amdgpu_irq_src *source, 1010 struct amdgpu_iv_entry *entry) 1011 { 1012 uint32_t i, inst; 1013 1014 i = node_id_to_phys_map[entry->node_id]; 1015 DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n"); 1016 1017 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) 1018 if (adev->jpeg.inst[inst].aid_id == i) 1019 break; 1020 1021 if (inst >= adev->jpeg.num_jpeg_inst) { 1022 dev_WARN_ONCE(adev->dev, 1, 1023 "Interrupt received for unknown JPEG instance %d", 1024 entry->node_id); 1025 return 0; 1026 } 1027 1028 switch (entry->src_id) { 1029 case VCN_4_0__SRCID__JPEG_DECODE: 1030 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); 1031 break; 1032 case VCN_4_0__SRCID__JPEG1_DECODE: 1033 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]); 1034 break; 1035 case VCN_4_0__SRCID__JPEG2_DECODE: 1036 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]); 1037 break; 1038 case VCN_4_0__SRCID__JPEG3_DECODE: 1039 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]); 1040 break; 1041 case VCN_4_0__SRCID__JPEG4_DECODE: 1042 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]); 1043 break; 1044 case VCN_4_0__SRCID__JPEG5_DECODE: 1045 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]); 1046 break; 1047 case VCN_4_0__SRCID__JPEG6_DECODE: 1048 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]); 1049 break; 1050 case VCN_4_0__SRCID__JPEG7_DECODE: 1051 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]); 1052 break; 1053 default: 1054 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1055 entry->src_id, entry->src_data[0]); 1056 break; 1057 } 1058 1059 return 0; 1060 } 1061 1062 static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = { 1063 .name = "jpeg_v4_0_3", 1064 .early_init = jpeg_v4_0_3_early_init, 1065 .sw_init = jpeg_v4_0_3_sw_init, 1066 .sw_fini = jpeg_v4_0_3_sw_fini, 1067 .hw_init = jpeg_v4_0_3_hw_init, 1068 .hw_fini = jpeg_v4_0_3_hw_fini, 1069 .suspend = jpeg_v4_0_3_suspend, 1070 .resume = jpeg_v4_0_3_resume, 1071 .is_idle = jpeg_v4_0_3_is_idle, 1072 .wait_for_idle = jpeg_v4_0_3_wait_for_idle, 1073 .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state, 1074 .set_powergating_state = jpeg_v4_0_3_set_powergating_state, 1075 }; 1076 1077 static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { 1078 .type = AMDGPU_RING_TYPE_VCN_JPEG, 1079 .align_mask = 0xf, 1080 .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr, 1081 .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr, 1082 .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr, 1083 .parse_cs = jpeg_v2_dec_ring_parse_cs, 1084 .emit_frame_size = 1085 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1086 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1087 8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */ 1088 18 + 18 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */ 1089 8 + 16, 1090 .emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */ 1091 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, 1092 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, 1093 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, 1094 .emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush, 1095 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 1096 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 1097 .insert_nop = jpeg_v4_0_3_dec_ring_nop, 1098 .insert_start = jpeg_v4_0_3_dec_ring_insert_start, 1099 .insert_end = jpeg_v4_0_3_dec_ring_insert_end, 1100 .pad_ib = amdgpu_ring_generic_pad_ib, 1101 .begin_use = amdgpu_jpeg_ring_begin_use, 1102 .end_use = amdgpu_jpeg_ring_end_use, 1103 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, 1104 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, 1105 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1106 }; 1107 1108 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev) 1109 { 1110 int i, j, jpeg_inst; 1111 1112 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1113 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 1114 adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs; 1115 adev->jpeg.inst[i].ring_dec[j].me = i; 1116 adev->jpeg.inst[i].ring_dec[j].pipe = j; 1117 } 1118 jpeg_inst = GET_INST(JPEG, i); 1119 adev->jpeg.inst[i].aid_id = 1120 jpeg_inst / adev->jpeg.num_inst_per_aid; 1121 } 1122 } 1123 1124 static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = { 1125 .set = jpeg_v4_0_3_set_interrupt_state, 1126 .process = jpeg_v4_0_3_process_interrupt, 1127 }; 1128 1129 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1130 { 1131 int i; 1132 1133 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1134 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; 1135 } 1136 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs; 1137 } 1138 1139 const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block = { 1140 .type = AMD_IP_BLOCK_TYPE_JPEG, 1141 .major = 4, 1142 .minor = 0, 1143 .rev = 3, 1144 .funcs = &jpeg_v4_0_3_ip_funcs, 1145 }; 1146 1147 static const struct amdgpu_ras_err_status_reg_entry jpeg_v4_0_3_ue_reg_list[] = { 1148 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0S, regVCN_UE_ERR_STATUS_HI_JPEG0S), 1149 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0S"}, 1150 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0D, regVCN_UE_ERR_STATUS_HI_JPEG0D), 1151 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0D"}, 1152 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1S, regVCN_UE_ERR_STATUS_HI_JPEG1S), 1153 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1S"}, 1154 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1D, regVCN_UE_ERR_STATUS_HI_JPEG1D), 1155 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1D"}, 1156 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2S, regVCN_UE_ERR_STATUS_HI_JPEG2S), 1157 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2S"}, 1158 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2D, regVCN_UE_ERR_STATUS_HI_JPEG2D), 1159 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2D"}, 1160 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3S, regVCN_UE_ERR_STATUS_HI_JPEG3S), 1161 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3S"}, 1162 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3D, regVCN_UE_ERR_STATUS_HI_JPEG3D), 1163 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3D"}, 1164 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4S, regVCN_UE_ERR_STATUS_HI_JPEG4S), 1165 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4S"}, 1166 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4D, regVCN_UE_ERR_STATUS_HI_JPEG4D), 1167 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4D"}, 1168 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5S, regVCN_UE_ERR_STATUS_HI_JPEG5S), 1169 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5S"}, 1170 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5D, regVCN_UE_ERR_STATUS_HI_JPEG5D), 1171 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5D"}, 1172 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6S, regVCN_UE_ERR_STATUS_HI_JPEG6S), 1173 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6S"}, 1174 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6D, regVCN_UE_ERR_STATUS_HI_JPEG6D), 1175 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6D"}, 1176 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7S, regVCN_UE_ERR_STATUS_HI_JPEG7S), 1177 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7S"}, 1178 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7D, regVCN_UE_ERR_STATUS_HI_JPEG7D), 1179 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7D"}, 1180 }; 1181 1182 static void jpeg_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1183 uint32_t jpeg_inst, 1184 void *ras_err_status) 1185 { 1186 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1187 1188 /* jpeg v4_0_3 only support uncorrectable errors */ 1189 amdgpu_ras_inst_query_ras_error_count(adev, 1190 jpeg_v4_0_3_ue_reg_list, 1191 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1192 NULL, 0, GET_INST(VCN, jpeg_inst), 1193 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1194 &err_data->ue_count); 1195 } 1196 1197 static void jpeg_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1198 void *ras_err_status) 1199 { 1200 uint32_t i; 1201 1202 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1203 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1204 return; 1205 } 1206 1207 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1208 jpeg_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1209 } 1210 1211 static void jpeg_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1212 uint32_t jpeg_inst) 1213 { 1214 amdgpu_ras_inst_reset_ras_error_count(adev, 1215 jpeg_v4_0_3_ue_reg_list, 1216 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1217 GET_INST(VCN, jpeg_inst)); 1218 } 1219 1220 static void jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1221 { 1222 uint32_t i; 1223 1224 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1225 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1226 return; 1227 } 1228 1229 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1230 jpeg_v4_0_3_inst_reset_ras_error_count(adev, i); 1231 } 1232 1233 static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = { 1234 .query_ras_error_count = jpeg_v4_0_3_query_ras_error_count, 1235 .reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count, 1236 }; 1237 1238 static int jpeg_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 1239 enum aca_smu_type type, void *data) 1240 { 1241 struct aca_bank_info info; 1242 u64 misc0; 1243 int ret; 1244 1245 ret = aca_bank_info_decode(bank, &info); 1246 if (ret) 1247 return ret; 1248 1249 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 1250 switch (type) { 1251 case ACA_SMU_TYPE_UE: 1252 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 1253 1ULL); 1254 break; 1255 case ACA_SMU_TYPE_CE: 1256 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_CE, 1257 ACA_REG__MISC0__ERRCNT(misc0)); 1258 break; 1259 default: 1260 return -EINVAL; 1261 } 1262 1263 return ret; 1264 } 1265 1266 /* reference to smu driver if header file */ 1267 static int jpeg_v4_0_3_err_codes[] = { 1268 16, 17, 18, 19, 20, 21, 22, 23, /* JPEG[0-7][S|D] */ 1269 24, 25, 26, 27, 28, 29, 30, 31 1270 }; 1271 1272 static bool jpeg_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 1273 enum aca_smu_type type, void *data) 1274 { 1275 u32 instlo; 1276 1277 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 1278 instlo &= GENMASK(31, 1); 1279 1280 if (instlo != mmSMNAID_AID0_MCA_SMU) 1281 return false; 1282 1283 if (aca_bank_check_error_codes(handle->adev, bank, 1284 jpeg_v4_0_3_err_codes, 1285 ARRAY_SIZE(jpeg_v4_0_3_err_codes))) 1286 return false; 1287 1288 return true; 1289 } 1290 1291 static const struct aca_bank_ops jpeg_v4_0_3_aca_bank_ops = { 1292 .aca_bank_parser = jpeg_v4_0_3_aca_bank_parser, 1293 .aca_bank_is_valid = jpeg_v4_0_3_aca_bank_is_valid, 1294 }; 1295 1296 static const struct aca_info jpeg_v4_0_3_aca_info = { 1297 .hwip = ACA_HWIP_TYPE_SMU, 1298 .mask = ACA_ERROR_UE_MASK, 1299 .bank_ops = &jpeg_v4_0_3_aca_bank_ops, 1300 }; 1301 1302 static int jpeg_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1303 { 1304 int r; 1305 1306 r = amdgpu_ras_block_late_init(adev, ras_block); 1307 if (r) 1308 return r; 1309 1310 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__JPEG, 1311 &jpeg_v4_0_3_aca_info, NULL); 1312 if (r) 1313 goto late_fini; 1314 1315 return 0; 1316 1317 late_fini: 1318 amdgpu_ras_block_late_fini(adev, ras_block); 1319 1320 return r; 1321 } 1322 1323 static struct amdgpu_jpeg_ras jpeg_v4_0_3_ras = { 1324 .ras_block = { 1325 .hw_ops = &jpeg_v4_0_3_ras_hw_ops, 1326 .ras_late_init = jpeg_v4_0_3_ras_late_init, 1327 }, 1328 }; 1329 1330 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 1331 { 1332 adev->jpeg.ras = &jpeg_v4_0_3_ras; 1333 } 1334