1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "soc15.h" 27 #include "soc15d.h" 28 #include "jpeg_v2_0.h" 29 #include "jpeg_v4_0_3.h" 30 #include "mmsch_v4_0_3.h" 31 32 #include "vcn/vcn_4_0_3_offset.h" 33 #include "vcn/vcn_4_0_3_sh_mask.h" 34 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 35 36 #define NORMALIZE_JPEG_REG_OFFSET(offset) \ 37 (offset & 0x1FFFF) 38 39 enum jpeg_engin_status { 40 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0, 41 UVD_PGFSM_STATUS__UVDJ_PWR_OFF = 2, 42 }; 43 44 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev); 45 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 46 static int jpeg_v4_0_3_set_powergating_state(void *handle, 47 enum amd_powergating_state state); 48 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 49 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring); 50 51 static int amdgpu_ih_srcid_jpeg[] = { 52 VCN_4_0__SRCID__JPEG_DECODE, 53 VCN_4_0__SRCID__JPEG1_DECODE, 54 VCN_4_0__SRCID__JPEG2_DECODE, 55 VCN_4_0__SRCID__JPEG3_DECODE, 56 VCN_4_0__SRCID__JPEG4_DECODE, 57 VCN_4_0__SRCID__JPEG5_DECODE, 58 VCN_4_0__SRCID__JPEG6_DECODE, 59 VCN_4_0__SRCID__JPEG7_DECODE 60 }; 61 62 static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) 63 { 64 return amdgpu_sriov_vf(adev) || 65 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)); 66 } 67 68 /** 69 * jpeg_v4_0_3_early_init - set function pointers 70 * 71 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 72 * 73 * Set ring and irq function pointers 74 */ 75 static int jpeg_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) 76 { 77 struct amdgpu_device *adev = ip_block->adev; 78 79 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS; 80 81 jpeg_v4_0_3_set_dec_ring_funcs(adev); 82 jpeg_v4_0_3_set_irq_funcs(adev); 83 jpeg_v4_0_3_set_ras_funcs(adev); 84 85 return 0; 86 } 87 88 /** 89 * jpeg_v4_0_3_sw_init - sw init for JPEG block 90 * 91 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 92 * 93 * Load firmware and sw initialization 94 */ 95 static int jpeg_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 96 { 97 struct amdgpu_device *adev = ip_block->adev; 98 struct amdgpu_ring *ring; 99 int i, j, r, jpeg_inst; 100 101 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 102 /* JPEG TRAP */ 103 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 104 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); 105 if (r) 106 return r; 107 } 108 109 r = amdgpu_jpeg_sw_init(adev); 110 if (r) 111 return r; 112 113 r = amdgpu_jpeg_resume(adev); 114 if (r) 115 return r; 116 117 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 118 jpeg_inst = GET_INST(JPEG, i); 119 120 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 121 ring = &adev->jpeg.inst[i].ring_dec[j]; 122 ring->use_doorbell = true; 123 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); 124 if (!amdgpu_sriov_vf(adev)) { 125 ring->doorbell_index = 126 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 127 1 + j + 9 * jpeg_inst; 128 } else { 129 if (j < 4) 130 ring->doorbell_index = 131 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 132 4 + j + 32 * jpeg_inst; 133 else 134 ring->doorbell_index = 135 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 136 8 + j + 32 * jpeg_inst; 137 } 138 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); 139 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 140 AMDGPU_RING_PRIO_DEFAULT, NULL); 141 if (r) 142 return r; 143 144 adev->jpeg.internal.jpeg_pitch[j] = 145 regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET; 146 adev->jpeg.inst[i].external.jpeg_pitch[j] = 147 SOC15_REG_OFFSET1( 148 JPEG, jpeg_inst, 149 regUVD_JRBC0_UVD_JRBC_SCRATCH0, 150 (j ? (0x40 * j - 0xc80) : 0)); 151 } 152 } 153 154 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 155 r = amdgpu_jpeg_ras_sw_init(adev); 156 if (r) { 157 dev_err(adev->dev, "Failed to initialize jpeg ras block!\n"); 158 return r; 159 } 160 } 161 162 return 0; 163 } 164 165 /** 166 * jpeg_v4_0_3_sw_fini - sw fini for JPEG block 167 * 168 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 169 * 170 * JPEG suspend and free up sw allocation 171 */ 172 static int jpeg_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) 173 { 174 struct amdgpu_device *adev = ip_block->adev; 175 int r; 176 177 r = amdgpu_jpeg_suspend(adev); 178 if (r) 179 return r; 180 181 r = amdgpu_jpeg_sw_fini(adev); 182 183 return r; 184 } 185 186 static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev) 187 { 188 struct amdgpu_ring *ring; 189 uint64_t ctx_addr; 190 uint32_t param, resp, expected; 191 uint32_t tmp, timeout; 192 193 struct amdgpu_mm_table *table = &adev->virt.mm_table; 194 uint32_t *table_loc; 195 uint32_t table_size; 196 uint32_t size, size_dw, item_offset; 197 uint32_t init_status; 198 int i, j, jpeg_inst; 199 200 struct mmsch_v4_0_cmd_direct_write 201 direct_wt = { {0} }; 202 struct mmsch_v4_0_cmd_end end = { {0} }; 203 struct mmsch_v4_0_3_init_header header; 204 205 direct_wt.cmd_header.command_type = 206 MMSCH_COMMAND__DIRECT_REG_WRITE; 207 end.cmd_header.command_type = 208 MMSCH_COMMAND__END; 209 210 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 211 jpeg_inst = GET_INST(JPEG, i); 212 213 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 214 header.version = MMSCH_VERSION; 215 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 216 217 table_loc = (uint32_t *)table->cpu_addr; 218 table_loc += header.total_size; 219 220 item_offset = header.total_size; 221 222 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) { 223 ring = &adev->jpeg.inst[i].ring_dec[j]; 224 table_size = 0; 225 226 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW); 227 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr)); 228 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH); 229 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr)); 230 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE); 231 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4); 232 233 if (j <= 3) { 234 header.mjpegdec0[j].table_offset = item_offset; 235 header.mjpegdec0[j].init_status = 0; 236 header.mjpegdec0[j].table_size = table_size; 237 } else { 238 header.mjpegdec1[j - 4].table_offset = item_offset; 239 header.mjpegdec1[j - 4].init_status = 0; 240 header.mjpegdec1[j - 4].table_size = table_size; 241 } 242 header.total_size += table_size; 243 item_offset += table_size; 244 } 245 246 MMSCH_V4_0_INSERT_END(); 247 248 /* send init table to MMSCH */ 249 size = sizeof(struct mmsch_v4_0_3_init_header); 250 table_loc = (uint32_t *)table->cpu_addr; 251 memcpy((void *)table_loc, &header, size); 252 253 ctx_addr = table->gpu_addr; 254 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 255 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 256 257 tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID); 258 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 259 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 260 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp); 261 262 size = header.total_size; 263 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size); 264 265 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0); 266 267 param = 0x00000001; 268 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param); 269 tmp = 0; 270 timeout = 1000; 271 resp = 0; 272 expected = MMSCH_VF_MAILBOX_RESP__OK; 273 init_status = 274 ((struct mmsch_v4_0_3_init_header *)(table_loc))->mjpegdec0[i].init_status; 275 while (resp != expected) { 276 resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP); 277 278 if (resp != 0) 279 break; 280 udelay(10); 281 tmp = tmp + 10; 282 if (tmp >= timeout) { 283 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 284 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 285 "(expected=0x%08x, readback=0x%08x)\n", 286 tmp, expected, resp); 287 return -EBUSY; 288 } 289 } 290 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE && 291 init_status != MMSCH_VF_ENGINE_STATUS__PASS) 292 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", 293 resp, init_status); 294 295 } 296 return 0; 297 } 298 299 /** 300 * jpeg_v4_0_3_hw_init - start and test JPEG block 301 * 302 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 303 * 304 */ 305 static int jpeg_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) 306 { 307 struct amdgpu_device *adev = ip_block->adev; 308 struct amdgpu_ring *ring; 309 int i, j, r, jpeg_inst; 310 311 if (amdgpu_sriov_vf(adev)) { 312 r = jpeg_v4_0_3_start_sriov(adev); 313 if (r) 314 return r; 315 316 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 317 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 318 ring = &adev->jpeg.inst[i].ring_dec[j]; 319 ring->wptr = 0; 320 ring->wptr_old = 0; 321 jpeg_v4_0_3_dec_ring_set_wptr(ring); 322 ring->sched.ready = true; 323 } 324 } 325 } else { 326 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 327 jpeg_inst = GET_INST(JPEG, i); 328 329 ring = adev->jpeg.inst[i].ring_dec; 330 331 if (ring->use_doorbell) 332 adev->nbio.funcs->vcn_doorbell_range( 333 adev, ring->use_doorbell, 334 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 335 9 * jpeg_inst, 336 adev->jpeg.inst[i].aid_id); 337 338 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 339 ring = &adev->jpeg.inst[i].ring_dec[j]; 340 if (ring->use_doorbell) 341 WREG32_SOC15_OFFSET( 342 VCN, GET_INST(VCN, i), 343 regVCN_JPEG_DB_CTRL, 344 (ring->pipe ? (ring->pipe - 0x15) : 0), 345 ring->doorbell_index 346 << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 347 VCN_JPEG_DB_CTRL__EN_MASK); 348 r = amdgpu_ring_test_helper(ring); 349 if (r) 350 return r; 351 } 352 } 353 } 354 355 return 0; 356 } 357 358 /** 359 * jpeg_v4_0_3_hw_fini - stop the hardware block 360 * 361 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 362 * 363 * Stop the JPEG block, mark ring as not ready any more 364 */ 365 static int jpeg_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) 366 { 367 struct amdgpu_device *adev = ip_block->adev; 368 int ret = 0; 369 370 cancel_delayed_work_sync(&adev->jpeg.idle_work); 371 372 if (!amdgpu_sriov_vf(adev)) { 373 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) 374 ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE); 375 } 376 377 return ret; 378 } 379 380 /** 381 * jpeg_v4_0_3_suspend - suspend JPEG block 382 * 383 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 384 * 385 * HW fini and suspend JPEG block 386 */ 387 static int jpeg_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) 388 { 389 int r; 390 391 r = jpeg_v4_0_3_hw_fini(ip_block); 392 if (r) 393 return r; 394 395 r = amdgpu_jpeg_suspend(ip_block->adev); 396 397 return r; 398 } 399 400 /** 401 * jpeg_v4_0_3_resume - resume JPEG block 402 * 403 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 404 * 405 * Resume firmware and hw init JPEG block 406 */ 407 static int jpeg_v4_0_3_resume(struct amdgpu_ip_block *ip_block) 408 { 409 int r; 410 411 r = amdgpu_jpeg_resume(ip_block->adev); 412 if (r) 413 return r; 414 415 r = jpeg_v4_0_3_hw_init(ip_block); 416 417 return r; 418 } 419 420 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) 421 { 422 int i, jpeg_inst; 423 uint32_t data; 424 425 jpeg_inst = GET_INST(JPEG, inst_idx); 426 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 427 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 428 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 429 data &= (~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1)); 430 } else { 431 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 432 } 433 434 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 435 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 436 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 437 438 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 439 data &= ~(JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 440 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 441 data &= ~(JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 442 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 443 } 444 445 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) 446 { 447 int i, jpeg_inst; 448 uint32_t data; 449 450 jpeg_inst = GET_INST(JPEG, inst_idx); 451 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 452 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 453 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 454 data |= (JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1); 455 } else { 456 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 457 } 458 459 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 460 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 461 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 462 463 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 464 data |= (JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 465 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 466 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 467 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 468 } 469 470 /** 471 * jpeg_v4_0_3_start - start JPEG block 472 * 473 * @adev: amdgpu_device pointer 474 * 475 * Setup and start the JPEG block 476 */ 477 static int jpeg_v4_0_3_start(struct amdgpu_device *adev) 478 { 479 struct amdgpu_ring *ring; 480 int i, j, jpeg_inst; 481 482 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 483 jpeg_inst = GET_INST(JPEG, i); 484 485 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 486 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 487 SOC15_WAIT_ON_RREG( 488 JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 489 UVD_PGFSM_STATUS__UVDJ_PWR_ON 490 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 491 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 492 493 /* disable anti hang mechanism */ 494 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 495 regUVD_JPEG_POWER_STATUS), 496 0, ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 497 498 /* JPEG disable CGC */ 499 jpeg_v4_0_3_disable_clock_gating(adev, i); 500 501 /* MJPEG global tiling registers */ 502 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX8_ADDR_CONFIG, 503 adev->gfx.config.gb_addr_config); 504 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX10_ADDR_CONFIG, 505 adev->gfx.config.gb_addr_config); 506 507 /* enable JMI channel */ 508 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0, 509 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 510 511 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 512 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 513 514 ring = &adev->jpeg.inst[i].ring_dec[j]; 515 516 /* enable System Interrupt for JRBC */ 517 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 518 regJPEG_SYS_INT_EN), 519 JPEG_SYS_INT_EN__DJRBC0_MASK << j, 520 ~(JPEG_SYS_INT_EN__DJRBC0_MASK << j)); 521 522 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 523 regUVD_JMI0_UVD_LMI_JRBC_RB_VMID, 524 reg_offset, 0); 525 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 526 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 527 reg_offset, 528 (0x00000001L | 0x00000002L)); 529 WREG32_SOC15_OFFSET( 530 JPEG, jpeg_inst, 531 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW, 532 reg_offset, lower_32_bits(ring->gpu_addr)); 533 WREG32_SOC15_OFFSET( 534 JPEG, jpeg_inst, 535 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 536 reg_offset, upper_32_bits(ring->gpu_addr)); 537 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 538 regUVD_JRBC0_UVD_JRBC_RB_RPTR, 539 reg_offset, 0); 540 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 541 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 542 reg_offset, 0); 543 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 544 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 545 reg_offset, 0x00000002L); 546 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 547 regUVD_JRBC0_UVD_JRBC_RB_SIZE, 548 reg_offset, ring->ring_size / 4); 549 ring->wptr = RREG32_SOC15_OFFSET( 550 JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_RB_WPTR, 551 reg_offset); 552 } 553 } 554 555 return 0; 556 } 557 558 /** 559 * jpeg_v4_0_3_stop - stop JPEG block 560 * 561 * @adev: amdgpu_device pointer 562 * 563 * stop the JPEG block 564 */ 565 static int jpeg_v4_0_3_stop(struct amdgpu_device *adev) 566 { 567 int i, jpeg_inst; 568 569 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 570 jpeg_inst = GET_INST(JPEG, i); 571 /* reset JMI */ 572 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 573 UVD_JMI_CNTL__SOFT_RESET_MASK, 574 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 575 576 jpeg_v4_0_3_enable_clock_gating(adev, i); 577 578 /* enable anti hang mechanism */ 579 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 580 regUVD_JPEG_POWER_STATUS), 581 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 582 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 583 584 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 585 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 586 SOC15_WAIT_ON_RREG( 587 JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 588 UVD_PGFSM_STATUS__UVDJ_PWR_OFF 589 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 590 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 591 } 592 593 return 0; 594 } 595 596 /** 597 * jpeg_v4_0_3_dec_ring_get_rptr - get read pointer 598 * 599 * @ring: amdgpu_ring pointer 600 * 601 * Returns the current hardware read pointer 602 */ 603 static uint64_t jpeg_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring *ring) 604 { 605 struct amdgpu_device *adev = ring->adev; 606 607 return RREG32_SOC15_OFFSET( 608 JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR, 609 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); 610 } 611 612 /** 613 * jpeg_v4_0_3_dec_ring_get_wptr - get write pointer 614 * 615 * @ring: amdgpu_ring pointer 616 * 617 * Returns the current hardware write pointer 618 */ 619 static uint64_t jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring) 620 { 621 struct amdgpu_device *adev = ring->adev; 622 623 if (ring->use_doorbell) 624 return adev->wb.wb[ring->wptr_offs]; 625 else 626 return RREG32_SOC15_OFFSET( 627 JPEG, GET_INST(JPEG, ring->me), 628 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 629 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); 630 } 631 632 static void jpeg_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 633 { 634 /* JPEG engine access for HDP flush doesn't work when RRMT is enabled. 635 * This is a workaround to avoid any HDP flush through JPEG ring. 636 */ 637 } 638 639 /** 640 * jpeg_v4_0_3_dec_ring_set_wptr - set write pointer 641 * 642 * @ring: amdgpu_ring pointer 643 * 644 * Commits the write pointer to the hardware 645 */ 646 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring) 647 { 648 struct amdgpu_device *adev = ring->adev; 649 650 if (ring->use_doorbell) { 651 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 652 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 653 } else { 654 WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), 655 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 656 (ring->pipe ? (0x40 * ring->pipe - 0xc80) : 657 0), 658 lower_32_bits(ring->wptr)); 659 } 660 } 661 662 /** 663 * jpeg_v4_0_3_dec_ring_insert_start - insert a start command 664 * 665 * @ring: amdgpu_ring pointer 666 * 667 * Write a start command to the ring. 668 */ 669 void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring) 670 { 671 if (!amdgpu_sriov_vf(ring->adev)) { 672 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 673 0, 0, PACKETJ_TYPE0)); 674 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 675 676 amdgpu_ring_write(ring, 677 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, 678 0, PACKETJ_TYPE0)); 679 amdgpu_ring_write(ring, 0x80004000); 680 } 681 } 682 683 /** 684 * jpeg_v4_0_3_dec_ring_insert_end - insert a end command 685 * 686 * @ring: amdgpu_ring pointer 687 * 688 * Write a end command to the ring. 689 */ 690 void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring) 691 { 692 if (!amdgpu_sriov_vf(ring->adev)) { 693 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 694 0, 0, PACKETJ_TYPE0)); 695 amdgpu_ring_write(ring, 0x62a04); 696 697 amdgpu_ring_write(ring, 698 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, 699 0, PACKETJ_TYPE0)); 700 amdgpu_ring_write(ring, 0x00004000); 701 } 702 } 703 704 /** 705 * jpeg_v4_0_3_dec_ring_emit_fence - emit an fence & trap command 706 * 707 * @ring: amdgpu_ring pointer 708 * @addr: address 709 * @seq: sequence number 710 * @flags: fence related flags 711 * 712 * Write a fence and a trap command to the ring. 713 */ 714 void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 715 unsigned int flags) 716 { 717 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 718 719 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 720 0, 0, PACKETJ_TYPE0)); 721 amdgpu_ring_write(ring, seq); 722 723 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 724 0, 0, PACKETJ_TYPE0)); 725 amdgpu_ring_write(ring, seq); 726 727 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 728 0, 0, PACKETJ_TYPE0)); 729 amdgpu_ring_write(ring, lower_32_bits(addr)); 730 731 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 732 0, 0, PACKETJ_TYPE0)); 733 amdgpu_ring_write(ring, upper_32_bits(addr)); 734 735 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 736 0, 0, PACKETJ_TYPE0)); 737 amdgpu_ring_write(ring, 0x8); 738 739 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 740 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 741 amdgpu_ring_write(ring, 0); 742 743 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 744 amdgpu_ring_write(ring, 0); 745 746 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 747 amdgpu_ring_write(ring, 0); 748 749 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 750 amdgpu_ring_write(ring, 0); 751 } 752 753 /** 754 * jpeg_v4_0_3_dec_ring_emit_ib - execute indirect buffer 755 * 756 * @ring: amdgpu_ring pointer 757 * @job: job to retrieve vmid from 758 * @ib: indirect buffer to execute 759 * @flags: unused 760 * 761 * Write ring commands to execute the indirect buffer. 762 */ 763 void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring, 764 struct amdgpu_job *job, 765 struct amdgpu_ib *ib, 766 uint32_t flags) 767 { 768 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 769 770 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 771 0, 0, PACKETJ_TYPE0)); 772 773 if (ring->funcs->parse_cs) 774 amdgpu_ring_write(ring, 0); 775 else 776 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 777 778 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 779 0, 0, PACKETJ_TYPE0)); 780 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 781 782 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 783 0, 0, PACKETJ_TYPE0)); 784 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 785 786 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 787 0, 0, PACKETJ_TYPE0)); 788 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 789 790 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 791 0, 0, PACKETJ_TYPE0)); 792 amdgpu_ring_write(ring, ib->length_dw); 793 794 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 795 0, 0, PACKETJ_TYPE0)); 796 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 797 798 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 799 0, 0, PACKETJ_TYPE0)); 800 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 801 802 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 803 amdgpu_ring_write(ring, 0); 804 805 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 806 0, 0, PACKETJ_TYPE0)); 807 amdgpu_ring_write(ring, 0x01400200); 808 809 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 810 0, 0, PACKETJ_TYPE0)); 811 amdgpu_ring_write(ring, 0x2); 812 813 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_STATUS_INTERNAL_OFFSET, 814 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 815 amdgpu_ring_write(ring, 0x2); 816 } 817 818 void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 819 uint32_t val, uint32_t mask) 820 { 821 uint32_t reg_offset; 822 823 /* Use normalized offsets if required */ 824 if (jpeg_v4_0_3_normalizn_reqd(ring->adev)) 825 reg = NORMALIZE_JPEG_REG_OFFSET(reg); 826 827 reg_offset = (reg << 2); 828 829 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 830 0, 0, PACKETJ_TYPE0)); 831 amdgpu_ring_write(ring, 0x01400200); 832 833 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 834 0, 0, PACKETJ_TYPE0)); 835 amdgpu_ring_write(ring, val); 836 837 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 838 0, 0, PACKETJ_TYPE0)); 839 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 840 amdgpu_ring_write(ring, 0); 841 amdgpu_ring_write(ring, 842 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 843 } else { 844 amdgpu_ring_write(ring, reg_offset); 845 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 846 0, 0, PACKETJ_TYPE3)); 847 } 848 amdgpu_ring_write(ring, mask); 849 } 850 851 void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 852 unsigned int vmid, uint64_t pd_addr) 853 { 854 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 855 uint32_t data0, data1, mask; 856 857 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 858 859 /* wait for register write */ 860 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 861 data1 = lower_32_bits(pd_addr); 862 mask = 0xffffffff; 863 jpeg_v4_0_3_dec_ring_emit_reg_wait(ring, data0, data1, mask); 864 } 865 866 void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 867 { 868 uint32_t reg_offset; 869 870 /* Use normalized offsets if required */ 871 if (jpeg_v4_0_3_normalizn_reqd(ring->adev)) 872 reg = NORMALIZE_JPEG_REG_OFFSET(reg); 873 874 reg_offset = (reg << 2); 875 876 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 877 0, 0, PACKETJ_TYPE0)); 878 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 879 amdgpu_ring_write(ring, 0); 880 amdgpu_ring_write(ring, 881 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 882 } else { 883 amdgpu_ring_write(ring, reg_offset); 884 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 885 0, 0, PACKETJ_TYPE0)); 886 } 887 amdgpu_ring_write(ring, val); 888 } 889 890 void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) 891 { 892 int i; 893 894 WARN_ON(ring->wptr % 2 || count % 2); 895 896 for (i = 0; i < count / 2; i++) { 897 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 898 amdgpu_ring_write(ring, 0); 899 } 900 } 901 902 static bool jpeg_v4_0_3_is_idle(void *handle) 903 { 904 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 905 bool ret = false; 906 int i, j; 907 908 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 909 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 910 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 911 912 ret &= ((RREG32_SOC15_OFFSET( 913 JPEG, GET_INST(JPEG, i), 914 regUVD_JRBC0_UVD_JRBC_STATUS, 915 reg_offset) & 916 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 917 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 918 } 919 } 920 921 return ret; 922 } 923 924 static int jpeg_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 925 { 926 struct amdgpu_device *adev = ip_block->adev; 927 int ret = 0; 928 int i, j; 929 930 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 931 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 932 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 933 934 ret &= SOC15_WAIT_ON_RREG_OFFSET( 935 JPEG, GET_INST(JPEG, i), 936 regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset, 937 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 938 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 939 } 940 } 941 return ret; 942 } 943 944 static int jpeg_v4_0_3_set_clockgating_state(void *handle, 945 enum amd_clockgating_state state) 946 { 947 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 948 bool enable = state == AMD_CG_STATE_GATE; 949 int i; 950 951 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 952 if (enable) { 953 if (!jpeg_v4_0_3_is_idle(handle)) 954 return -EBUSY; 955 jpeg_v4_0_3_enable_clock_gating(adev, i); 956 } else { 957 jpeg_v4_0_3_disable_clock_gating(adev, i); 958 } 959 } 960 return 0; 961 } 962 963 static int jpeg_v4_0_3_set_powergating_state(void *handle, 964 enum amd_powergating_state state) 965 { 966 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 967 int ret; 968 969 if (amdgpu_sriov_vf(adev)) { 970 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; 971 return 0; 972 } 973 974 if (state == adev->jpeg.cur_state) 975 return 0; 976 977 if (state == AMD_PG_STATE_GATE) 978 ret = jpeg_v4_0_3_stop(adev); 979 else 980 ret = jpeg_v4_0_3_start(adev); 981 982 if (!ret) 983 adev->jpeg.cur_state = state; 984 985 return ret; 986 } 987 988 static int jpeg_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 989 struct amdgpu_irq_src *source, 990 unsigned int type, 991 enum amdgpu_interrupt_state state) 992 { 993 return 0; 994 } 995 996 static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev, 997 struct amdgpu_irq_src *source, 998 struct amdgpu_iv_entry *entry) 999 { 1000 uint32_t i, inst; 1001 1002 i = node_id_to_phys_map[entry->node_id]; 1003 DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n"); 1004 1005 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) 1006 if (adev->jpeg.inst[inst].aid_id == i) 1007 break; 1008 1009 if (inst >= adev->jpeg.num_jpeg_inst) { 1010 dev_WARN_ONCE(adev->dev, 1, 1011 "Interrupt received for unknown JPEG instance %d", 1012 entry->node_id); 1013 return 0; 1014 } 1015 1016 switch (entry->src_id) { 1017 case VCN_4_0__SRCID__JPEG_DECODE: 1018 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); 1019 break; 1020 case VCN_4_0__SRCID__JPEG1_DECODE: 1021 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]); 1022 break; 1023 case VCN_4_0__SRCID__JPEG2_DECODE: 1024 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]); 1025 break; 1026 case VCN_4_0__SRCID__JPEG3_DECODE: 1027 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]); 1028 break; 1029 case VCN_4_0__SRCID__JPEG4_DECODE: 1030 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]); 1031 break; 1032 case VCN_4_0__SRCID__JPEG5_DECODE: 1033 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]); 1034 break; 1035 case VCN_4_0__SRCID__JPEG6_DECODE: 1036 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]); 1037 break; 1038 case VCN_4_0__SRCID__JPEG7_DECODE: 1039 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]); 1040 break; 1041 default: 1042 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1043 entry->src_id, entry->src_data[0]); 1044 break; 1045 } 1046 1047 return 0; 1048 } 1049 1050 static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = { 1051 .name = "jpeg_v4_0_3", 1052 .early_init = jpeg_v4_0_3_early_init, 1053 .sw_init = jpeg_v4_0_3_sw_init, 1054 .sw_fini = jpeg_v4_0_3_sw_fini, 1055 .hw_init = jpeg_v4_0_3_hw_init, 1056 .hw_fini = jpeg_v4_0_3_hw_fini, 1057 .suspend = jpeg_v4_0_3_suspend, 1058 .resume = jpeg_v4_0_3_resume, 1059 .is_idle = jpeg_v4_0_3_is_idle, 1060 .wait_for_idle = jpeg_v4_0_3_wait_for_idle, 1061 .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state, 1062 .set_powergating_state = jpeg_v4_0_3_set_powergating_state, 1063 }; 1064 1065 static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { 1066 .type = AMDGPU_RING_TYPE_VCN_JPEG, 1067 .align_mask = 0xf, 1068 .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr, 1069 .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr, 1070 .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr, 1071 .parse_cs = jpeg_v2_dec_ring_parse_cs, 1072 .emit_frame_size = 1073 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1074 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1075 8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */ 1076 18 + 18 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */ 1077 8 + 16, 1078 .emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */ 1079 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, 1080 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, 1081 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, 1082 .emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush, 1083 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 1084 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 1085 .insert_nop = jpeg_v4_0_3_dec_ring_nop, 1086 .insert_start = jpeg_v4_0_3_dec_ring_insert_start, 1087 .insert_end = jpeg_v4_0_3_dec_ring_insert_end, 1088 .pad_ib = amdgpu_ring_generic_pad_ib, 1089 .begin_use = amdgpu_jpeg_ring_begin_use, 1090 .end_use = amdgpu_jpeg_ring_end_use, 1091 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, 1092 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, 1093 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1094 }; 1095 1096 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev) 1097 { 1098 int i, j, jpeg_inst; 1099 1100 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1101 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 1102 adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs; 1103 adev->jpeg.inst[i].ring_dec[j].me = i; 1104 adev->jpeg.inst[i].ring_dec[j].pipe = j; 1105 } 1106 jpeg_inst = GET_INST(JPEG, i); 1107 adev->jpeg.inst[i].aid_id = 1108 jpeg_inst / adev->jpeg.num_inst_per_aid; 1109 } 1110 } 1111 1112 static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = { 1113 .set = jpeg_v4_0_3_set_interrupt_state, 1114 .process = jpeg_v4_0_3_process_interrupt, 1115 }; 1116 1117 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1118 { 1119 int i; 1120 1121 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1122 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; 1123 } 1124 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs; 1125 } 1126 1127 const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block = { 1128 .type = AMD_IP_BLOCK_TYPE_JPEG, 1129 .major = 4, 1130 .minor = 0, 1131 .rev = 3, 1132 .funcs = &jpeg_v4_0_3_ip_funcs, 1133 }; 1134 1135 static const struct amdgpu_ras_err_status_reg_entry jpeg_v4_0_3_ue_reg_list[] = { 1136 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0S, regVCN_UE_ERR_STATUS_HI_JPEG0S), 1137 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0S"}, 1138 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0D, regVCN_UE_ERR_STATUS_HI_JPEG0D), 1139 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0D"}, 1140 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1S, regVCN_UE_ERR_STATUS_HI_JPEG1S), 1141 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1S"}, 1142 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1D, regVCN_UE_ERR_STATUS_HI_JPEG1D), 1143 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1D"}, 1144 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2S, regVCN_UE_ERR_STATUS_HI_JPEG2S), 1145 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2S"}, 1146 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2D, regVCN_UE_ERR_STATUS_HI_JPEG2D), 1147 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2D"}, 1148 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3S, regVCN_UE_ERR_STATUS_HI_JPEG3S), 1149 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3S"}, 1150 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3D, regVCN_UE_ERR_STATUS_HI_JPEG3D), 1151 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3D"}, 1152 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4S, regVCN_UE_ERR_STATUS_HI_JPEG4S), 1153 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4S"}, 1154 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4D, regVCN_UE_ERR_STATUS_HI_JPEG4D), 1155 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4D"}, 1156 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5S, regVCN_UE_ERR_STATUS_HI_JPEG5S), 1157 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5S"}, 1158 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5D, regVCN_UE_ERR_STATUS_HI_JPEG5D), 1159 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5D"}, 1160 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6S, regVCN_UE_ERR_STATUS_HI_JPEG6S), 1161 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6S"}, 1162 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6D, regVCN_UE_ERR_STATUS_HI_JPEG6D), 1163 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6D"}, 1164 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7S, regVCN_UE_ERR_STATUS_HI_JPEG7S), 1165 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7S"}, 1166 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7D, regVCN_UE_ERR_STATUS_HI_JPEG7D), 1167 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7D"}, 1168 }; 1169 1170 static void jpeg_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1171 uint32_t jpeg_inst, 1172 void *ras_err_status) 1173 { 1174 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1175 1176 /* jpeg v4_0_3 only support uncorrectable errors */ 1177 amdgpu_ras_inst_query_ras_error_count(adev, 1178 jpeg_v4_0_3_ue_reg_list, 1179 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1180 NULL, 0, GET_INST(VCN, jpeg_inst), 1181 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1182 &err_data->ue_count); 1183 } 1184 1185 static void jpeg_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1186 void *ras_err_status) 1187 { 1188 uint32_t i; 1189 1190 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1191 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1192 return; 1193 } 1194 1195 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1196 jpeg_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1197 } 1198 1199 static void jpeg_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1200 uint32_t jpeg_inst) 1201 { 1202 amdgpu_ras_inst_reset_ras_error_count(adev, 1203 jpeg_v4_0_3_ue_reg_list, 1204 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1205 GET_INST(VCN, jpeg_inst)); 1206 } 1207 1208 static void jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1209 { 1210 uint32_t i; 1211 1212 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1213 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1214 return; 1215 } 1216 1217 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1218 jpeg_v4_0_3_inst_reset_ras_error_count(adev, i); 1219 } 1220 1221 static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = { 1222 .query_ras_error_count = jpeg_v4_0_3_query_ras_error_count, 1223 .reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count, 1224 }; 1225 1226 static struct amdgpu_jpeg_ras jpeg_v4_0_3_ras = { 1227 .ras_block = { 1228 .hw_ops = &jpeg_v4_0_3_ras_hw_ops, 1229 }, 1230 }; 1231 1232 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 1233 { 1234 adev->jpeg.ras = &jpeg_v4_0_3_ras; 1235 } 1236