1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "soc15.h" 27 #include "soc15d.h" 28 #include "jpeg_v2_0.h" 29 #include "jpeg_v4_0_3.h" 30 #include "mmsch_v4_0_3.h" 31 32 #include "vcn/vcn_4_0_3_offset.h" 33 #include "vcn/vcn_4_0_3_sh_mask.h" 34 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 35 36 #define NORMALIZE_JPEG_REG_OFFSET(offset) \ 37 (offset & 0x1FFFF) 38 39 enum jpeg_engin_status { 40 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0, 41 UVD_PGFSM_STATUS__UVDJ_PWR_OFF = 2, 42 }; 43 44 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev); 45 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 46 static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 47 enum amd_powergating_state state); 48 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 49 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring); 50 51 static int amdgpu_ih_srcid_jpeg[] = { 52 VCN_4_0__SRCID__JPEG_DECODE, 53 VCN_4_0__SRCID__JPEG1_DECODE, 54 VCN_4_0__SRCID__JPEG2_DECODE, 55 VCN_4_0__SRCID__JPEG3_DECODE, 56 VCN_4_0__SRCID__JPEG4_DECODE, 57 VCN_4_0__SRCID__JPEG5_DECODE, 58 VCN_4_0__SRCID__JPEG6_DECODE, 59 VCN_4_0__SRCID__JPEG7_DECODE 60 }; 61 62 static const struct amdgpu_hwip_reg_entry jpeg_reg_list_4_0_3[] = { 63 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), 64 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), 65 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_SYS_INT_STATUS), 66 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR), 67 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR), 68 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS), 69 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), 70 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), 71 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), 72 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), 73 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), 74 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), 75 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR), 76 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR), 77 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS), 78 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR), 79 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR), 80 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS), 81 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR), 82 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR), 83 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS), 84 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR), 85 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR), 86 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS), 87 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR), 88 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR), 89 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS), 90 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR), 91 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR), 92 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_STATUS), 93 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR), 94 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR), 95 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS), 96 }; 97 98 static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) 99 { 100 return (adev->jpeg.caps & AMDGPU_JPEG_CAPS(RRMT_ENABLED)) == 0; 101 } 102 103 static inline int jpeg_v4_0_3_core_reg_offset(u32 pipe) 104 { 105 if (pipe) 106 return ((0x40 * pipe) - 0xc80); 107 else 108 return 0; 109 } 110 111 /** 112 * jpeg_v4_0_3_early_init - set function pointers 113 * 114 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 115 * 116 * Set ring and irq function pointers 117 */ 118 static int jpeg_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) 119 { 120 struct amdgpu_device *adev = ip_block->adev; 121 122 switch (amdgpu_user_queue) { 123 case -1: 124 case 0: 125 default: 126 adev->jpeg.disable_kq = false; 127 adev->jpeg.disable_uq = true; 128 break; 129 case 2: 130 adev->jpeg.disable_kq = true; 131 adev->jpeg.disable_uq = true; 132 break; 133 } 134 135 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3; 136 137 jpeg_v4_0_3_set_dec_ring_funcs(adev); 138 jpeg_v4_0_3_set_irq_funcs(adev); 139 jpeg_v4_0_3_set_ras_funcs(adev); 140 141 return 0; 142 } 143 144 /** 145 * jpeg_v4_0_3_sw_init - sw init for JPEG block 146 * 147 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 148 * 149 * Load firmware and sw initialization 150 */ 151 static int jpeg_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 152 { 153 struct amdgpu_device *adev = ip_block->adev; 154 struct amdgpu_ring *ring; 155 int i, j, r, jpeg_inst; 156 157 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 158 /* JPEG TRAP */ 159 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 160 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); 161 if (r) 162 return r; 163 } 164 165 /* JPEG DJPEG POISON EVENT */ 166 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 167 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); 168 if (r) 169 return r; 170 171 /* JPEG EJPEG POISON EVENT */ 172 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 173 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); 174 if (r) 175 return r; 176 177 r = amdgpu_jpeg_sw_init(adev); 178 if (r) 179 return r; 180 181 r = amdgpu_jpeg_resume(adev); 182 if (r) 183 return r; 184 185 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 186 jpeg_inst = GET_INST(JPEG, i); 187 188 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 189 ring = &adev->jpeg.inst[i].ring_dec[j]; 190 ring->use_doorbell = true; 191 if (adev->jpeg.disable_kq) { 192 ring->no_scheduler = true; 193 ring->no_user_submission = true; 194 } 195 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); 196 if (!amdgpu_sriov_vf(adev)) { 197 ring->doorbell_index = 198 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 199 1 + j + 9 * jpeg_inst; 200 } else { 201 if (j < 4) 202 ring->doorbell_index = 203 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 204 4 + j + 32 * jpeg_inst; 205 else 206 ring->doorbell_index = 207 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 208 8 + j + 32 * jpeg_inst; 209 } 210 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); 211 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 212 AMDGPU_RING_PRIO_DEFAULT, NULL); 213 if (r) 214 return r; 215 216 adev->jpeg.internal.jpeg_pitch[j] = 217 regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET; 218 adev->jpeg.inst[i].external.jpeg_pitch[j] = 219 SOC15_REG_OFFSET1(JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_SCRATCH0, 220 jpeg_v4_0_3_core_reg_offset(j)); 221 } 222 } 223 224 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 225 r = amdgpu_jpeg_ras_sw_init(adev); 226 if (r) { 227 dev_err(adev->dev, "Failed to initialize jpeg ras block!\n"); 228 return r; 229 } 230 } 231 232 r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0_3, ARRAY_SIZE(jpeg_reg_list_4_0_3)); 233 if (r) 234 return r; 235 236 adev->jpeg.supported_reset = 237 amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec); 238 if (!amdgpu_sriov_vf(adev)) 239 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 240 r = amdgpu_jpeg_sysfs_reset_mask_init(adev); 241 242 return 0; 243 } 244 245 /** 246 * jpeg_v4_0_3_sw_fini - sw fini for JPEG block 247 * 248 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 249 * 250 * JPEG suspend and free up sw allocation 251 */ 252 static int jpeg_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) 253 { 254 struct amdgpu_device *adev = ip_block->adev; 255 int r; 256 257 r = amdgpu_jpeg_suspend(adev); 258 if (r) 259 return r; 260 261 amdgpu_jpeg_sysfs_reset_mask_fini(adev); 262 263 r = amdgpu_jpeg_sw_fini(adev); 264 265 return r; 266 } 267 268 static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev) 269 { 270 struct amdgpu_ring *ring; 271 uint64_t ctx_addr; 272 uint32_t param, resp, expected; 273 uint32_t tmp, timeout; 274 275 struct amdgpu_mm_table *table = &adev->virt.mm_table; 276 uint32_t *table_loc; 277 uint32_t table_size; 278 uint32_t size, size_dw, item_offset; 279 uint32_t init_status; 280 int i, j, jpeg_inst; 281 282 struct mmsch_v4_0_cmd_direct_write 283 direct_wt = { {0} }; 284 struct mmsch_v4_0_cmd_end end = { {0} }; 285 struct mmsch_v4_0_3_init_header header; 286 287 direct_wt.cmd_header.command_type = 288 MMSCH_COMMAND__DIRECT_REG_WRITE; 289 end.cmd_header.command_type = 290 MMSCH_COMMAND__END; 291 292 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 293 jpeg_inst = GET_INST(JPEG, i); 294 295 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 296 header.version = MMSCH_VERSION; 297 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 298 299 table_loc = (uint32_t *)table->cpu_addr; 300 table_loc += header.total_size; 301 302 item_offset = header.total_size; 303 304 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) { 305 ring = &adev->jpeg.inst[i].ring_dec[j]; 306 table_size = 0; 307 308 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW); 309 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr)); 310 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH); 311 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr)); 312 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE); 313 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4); 314 315 if (j <= 3) { 316 header.mjpegdec0[j].table_offset = item_offset; 317 header.mjpegdec0[j].init_status = 0; 318 header.mjpegdec0[j].table_size = table_size; 319 } else { 320 header.mjpegdec1[j - 4].table_offset = item_offset; 321 header.mjpegdec1[j - 4].init_status = 0; 322 header.mjpegdec1[j - 4].table_size = table_size; 323 } 324 header.total_size += table_size; 325 item_offset += table_size; 326 } 327 328 MMSCH_V4_0_INSERT_END(); 329 330 /* send init table to MMSCH */ 331 size = sizeof(struct mmsch_v4_0_3_init_header); 332 table_loc = (uint32_t *)table->cpu_addr; 333 memcpy((void *)table_loc, &header, size); 334 335 ctx_addr = table->gpu_addr; 336 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 337 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 338 339 tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID); 340 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 341 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 342 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp); 343 344 size = header.total_size; 345 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size); 346 347 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0); 348 349 param = 0x00000001; 350 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param); 351 tmp = 0; 352 timeout = 1000; 353 resp = 0; 354 expected = MMSCH_VF_MAILBOX_RESP__OK; 355 init_status = 356 ((struct mmsch_v4_0_3_init_header *)(table_loc))->mjpegdec0[i].init_status; 357 while (resp != expected) { 358 resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP); 359 360 if (resp != 0) 361 break; 362 udelay(10); 363 tmp = tmp + 10; 364 if (tmp >= timeout) { 365 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 366 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 367 "(expected=0x%08x, readback=0x%08x)\n", 368 tmp, expected, resp); 369 return -EBUSY; 370 } 371 } 372 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE && 373 init_status != MMSCH_VF_ENGINE_STATUS__PASS) 374 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", 375 resp, init_status); 376 377 } 378 return 0; 379 } 380 381 /** 382 * jpeg_v4_0_3_hw_init - start and test JPEG block 383 * 384 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 385 * 386 */ 387 static int jpeg_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) 388 { 389 struct amdgpu_device *adev = ip_block->adev; 390 struct amdgpu_ring *ring; 391 int i, j, r, jpeg_inst; 392 393 if (amdgpu_sriov_vf(adev)) { 394 r = jpeg_v4_0_3_start_sriov(adev); 395 if (r) 396 return r; 397 398 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 399 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 400 ring = &adev->jpeg.inst[i].ring_dec[j]; 401 ring->wptr = 0; 402 ring->wptr_old = 0; 403 jpeg_v4_0_3_dec_ring_set_wptr(ring); 404 ring->sched.ready = true; 405 } 406 } 407 } else { 408 /* This flag is not set for VF, assumed to be disabled always */ 409 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 410 0x100) 411 adev->jpeg.caps |= AMDGPU_JPEG_CAPS(RRMT_ENABLED); 412 413 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 414 jpeg_inst = GET_INST(JPEG, i); 415 416 ring = adev->jpeg.inst[i].ring_dec; 417 418 if (ring->use_doorbell) 419 adev->nbio.funcs->vcn_doorbell_range( 420 adev, ring->use_doorbell, 421 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 422 9 * jpeg_inst, 423 adev->jpeg.inst[i].aid_id); 424 425 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 426 ring = &adev->jpeg.inst[i].ring_dec[j]; 427 if (ring->use_doorbell) 428 WREG32_SOC15_OFFSET( 429 VCN, GET_INST(VCN, i), 430 regVCN_JPEG_DB_CTRL, 431 (ring->pipe ? (ring->pipe - 0x15) : 0), 432 ring->doorbell_index 433 << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 434 VCN_JPEG_DB_CTRL__EN_MASK); 435 r = amdgpu_ring_test_helper(ring); 436 if (r) 437 return r; 438 } 439 } 440 } 441 442 return 0; 443 } 444 445 /** 446 * jpeg_v4_0_3_hw_fini - stop the hardware block 447 * 448 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 449 * 450 * Stop the JPEG block, mark ring as not ready any more 451 */ 452 static int jpeg_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) 453 { 454 struct amdgpu_device *adev = ip_block->adev; 455 int ret = 0; 456 457 cancel_delayed_work_sync(&adev->jpeg.idle_work); 458 459 if (!amdgpu_sriov_vf(adev)) { 460 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) 461 ret = jpeg_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 462 } 463 464 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG) && !amdgpu_sriov_vf(adev)) 465 amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0); 466 467 return ret; 468 } 469 470 /** 471 * jpeg_v4_0_3_suspend - suspend JPEG block 472 * 473 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 474 * 475 * HW fini and suspend JPEG block 476 */ 477 static int jpeg_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) 478 { 479 int r; 480 481 r = jpeg_v4_0_3_hw_fini(ip_block); 482 if (r) 483 return r; 484 485 r = amdgpu_jpeg_suspend(ip_block->adev); 486 487 return r; 488 } 489 490 /** 491 * jpeg_v4_0_3_resume - resume JPEG block 492 * 493 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 494 * 495 * Resume firmware and hw init JPEG block 496 */ 497 static int jpeg_v4_0_3_resume(struct amdgpu_ip_block *ip_block) 498 { 499 int r; 500 501 r = amdgpu_jpeg_resume(ip_block->adev); 502 if (r) 503 return r; 504 505 r = jpeg_v4_0_3_hw_init(ip_block); 506 507 return r; 508 } 509 510 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) 511 { 512 int i, jpeg_inst; 513 uint32_t data; 514 515 jpeg_inst = GET_INST(JPEG, inst_idx); 516 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 517 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 518 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 519 data &= (~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1)); 520 } else { 521 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 522 } 523 524 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 525 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 526 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 527 528 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 529 data &= ~(JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 530 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 531 data &= ~(JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 532 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 533 } 534 535 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) 536 { 537 int i, jpeg_inst; 538 uint32_t data; 539 540 jpeg_inst = GET_INST(JPEG, inst_idx); 541 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 542 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 543 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 544 data |= (JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1); 545 } else { 546 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 547 } 548 549 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 550 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 551 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 552 553 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 554 data |= (JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 555 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 556 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 557 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 558 } 559 560 static void jpeg_v4_0_3_start_inst(struct amdgpu_device *adev, int inst) 561 { 562 int jpeg_inst = GET_INST(JPEG, inst); 563 564 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 565 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 566 SOC15_WAIT_ON_RREG(JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 567 UVD_PGFSM_STATUS__UVDJ_PWR_ON << 568 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 569 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 570 571 /* disable anti hang mechanism */ 572 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 573 0, ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 574 575 /* JPEG disable CGC */ 576 jpeg_v4_0_3_disable_clock_gating(adev, inst); 577 578 /* MJPEG global tiling registers */ 579 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX8_ADDR_CONFIG, 580 adev->gfx.config.gb_addr_config); 581 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX10_ADDR_CONFIG, 582 adev->gfx.config.gb_addr_config); 583 584 /* enable JMI channel */ 585 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0, 586 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 587 } 588 589 static void jpeg_v4_0_3_start_jrbc(struct amdgpu_ring *ring) 590 { 591 struct amdgpu_device *adev = ring->adev; 592 int jpeg_inst = GET_INST(JPEG, ring->me); 593 int reg_offset = jpeg_v4_0_3_core_reg_offset(ring->pipe); 594 595 /* enable System Interrupt for JRBC */ 596 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regJPEG_SYS_INT_EN), 597 JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe, 598 ~(JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe)); 599 600 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 601 regUVD_JMI0_UVD_LMI_JRBC_RB_VMID, 602 reg_offset, 0); 603 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 604 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 605 reg_offset, 606 (0x00000001L | 0x00000002L)); 607 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 608 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW, 609 reg_offset, lower_32_bits(ring->gpu_addr)); 610 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 611 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 612 reg_offset, upper_32_bits(ring->gpu_addr)); 613 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 614 regUVD_JRBC0_UVD_JRBC_RB_RPTR, 615 reg_offset, 0); 616 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 617 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 618 reg_offset, 0); 619 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 620 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 621 reg_offset, 0x00000002L); 622 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 623 regUVD_JRBC0_UVD_JRBC_RB_SIZE, 624 reg_offset, ring->ring_size / 4); 625 ring->wptr = RREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_RB_WPTR, 626 reg_offset); 627 } 628 629 /** 630 * jpeg_v4_0_3_start - start JPEG block 631 * 632 * @adev: amdgpu_device pointer 633 * 634 * Setup and start the JPEG block 635 */ 636 static int jpeg_v4_0_3_start(struct amdgpu_device *adev) 637 { 638 struct amdgpu_ring *ring; 639 int i, j; 640 641 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 642 jpeg_v4_0_3_start_inst(adev, i); 643 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 644 ring = &adev->jpeg.inst[i].ring_dec[j]; 645 jpeg_v4_0_3_start_jrbc(ring); 646 } 647 } 648 649 return 0; 650 } 651 652 static void jpeg_v4_0_3_stop_inst(struct amdgpu_device *adev, int inst) 653 { 654 int jpeg_inst = GET_INST(JPEG, inst); 655 /* reset JMI */ 656 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 657 UVD_JMI_CNTL__SOFT_RESET_MASK, 658 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 659 660 jpeg_v4_0_3_enable_clock_gating(adev, inst); 661 662 /* enable anti hang mechanism */ 663 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 664 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 665 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 666 667 } 668 669 /** 670 * jpeg_v4_0_3_stop - stop JPEG block 671 * 672 * @adev: amdgpu_device pointer 673 * 674 * stop the JPEG block 675 */ 676 static int jpeg_v4_0_3_stop(struct amdgpu_device *adev) 677 { 678 int i; 679 680 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) 681 jpeg_v4_0_3_stop_inst(adev, i); 682 683 return 0; 684 } 685 686 /** 687 * jpeg_v4_0_3_dec_ring_get_rptr - get read pointer 688 * 689 * @ring: amdgpu_ring pointer 690 * 691 * Returns the current hardware read pointer 692 */ 693 static uint64_t jpeg_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring *ring) 694 { 695 struct amdgpu_device *adev = ring->adev; 696 697 return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR, 698 jpeg_v4_0_3_core_reg_offset(ring->pipe)); 699 } 700 701 /** 702 * jpeg_v4_0_3_dec_ring_get_wptr - get write pointer 703 * 704 * @ring: amdgpu_ring pointer 705 * 706 * Returns the current hardware write pointer 707 */ 708 static uint64_t jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring) 709 { 710 struct amdgpu_device *adev = ring->adev; 711 712 if (ring->use_doorbell) 713 return adev->wb.wb[ring->wptr_offs]; 714 715 return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_WPTR, 716 jpeg_v4_0_3_core_reg_offset(ring->pipe)); 717 } 718 719 void jpeg_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 720 { 721 /* JPEG engine access for HDP flush doesn't work when RRMT is enabled. 722 * This is a workaround to avoid any HDP flush through JPEG ring. 723 */ 724 } 725 726 /** 727 * jpeg_v4_0_3_dec_ring_set_wptr - set write pointer 728 * 729 * @ring: amdgpu_ring pointer 730 * 731 * Commits the write pointer to the hardware 732 */ 733 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring) 734 { 735 struct amdgpu_device *adev = ring->adev; 736 737 if (ring->use_doorbell) { 738 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 739 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 740 } else { 741 WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_WPTR, 742 jpeg_v4_0_3_core_reg_offset(ring->pipe), 743 lower_32_bits(ring->wptr)); 744 } 745 } 746 747 /** 748 * jpeg_v4_0_3_dec_ring_insert_start - insert a start command 749 * 750 * @ring: amdgpu_ring pointer 751 * 752 * Write a start command to the ring. 753 */ 754 void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring) 755 { 756 struct amdgpu_device *adev = ring->adev; 757 758 if (!amdgpu_sriov_vf(adev)) { 759 int jpeg_inst = GET_INST(JPEG, ring->me); 760 uint32_t value = 0x80004000; /* default DS14 */ 761 762 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 763 0, 0, PACKETJ_TYPE0)); 764 765 /* PCTL0__MMHUB_DEEPSLEEP_IB could be different on different mmhub version */ 766 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 767 case IP_VERSION(4, 1, 0): 768 amdgpu_ring_write(ring, 0x69004); 769 value = 0x80010000; 770 break; 771 case IP_VERSION(4, 2, 0): 772 amdgpu_ring_write(ring, 0x60804); 773 if (jpeg_inst & 1) 774 value = 0x80010000; 775 break; 776 default: 777 amdgpu_ring_write(ring, 0x62a04); 778 break; 779 } 780 781 amdgpu_ring_write(ring, 782 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, 783 0, PACKETJ_TYPE0)); 784 amdgpu_ring_write(ring, value); 785 } 786 } 787 788 /** 789 * jpeg_v4_0_3_dec_ring_insert_end - insert a end command 790 * 791 * @ring: amdgpu_ring pointer 792 * 793 * Write a end command to the ring. 794 */ 795 void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring) 796 { 797 struct amdgpu_device *adev = ring->adev; 798 799 if (!amdgpu_sriov_vf(adev)) { 800 int jpeg_inst = GET_INST(JPEG, ring->me); 801 uint32_t value = 0x00004000; /* default DS14 */ 802 803 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 804 0, 0, PACKETJ_TYPE0)); 805 806 /* PCTL0__MMHUB_DEEPSLEEP_IB could be different on different mmhub version */ 807 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 808 case IP_VERSION(4, 1, 0): 809 amdgpu_ring_write(ring, 0x69004); 810 value = 0x00010000; 811 break; 812 case IP_VERSION(4, 2, 0): 813 amdgpu_ring_write(ring, 0x60804); 814 if (jpeg_inst & 1) 815 value = 0x00010000; 816 break; 817 default: 818 amdgpu_ring_write(ring, 0x62a04); 819 break; 820 } 821 822 amdgpu_ring_write(ring, 823 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, 824 0, PACKETJ_TYPE0)); 825 amdgpu_ring_write(ring, value); 826 } 827 } 828 829 /** 830 * jpeg_v4_0_3_dec_ring_emit_fence - emit an fence & trap command 831 * 832 * @ring: amdgpu_ring pointer 833 * @addr: address 834 * @seq: sequence number 835 * @flags: fence related flags 836 * 837 * Write a fence and a trap command to the ring. 838 */ 839 void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 840 unsigned int flags) 841 { 842 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 843 844 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 845 0, 0, PACKETJ_TYPE0)); 846 amdgpu_ring_write(ring, seq); 847 848 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 849 0, 0, PACKETJ_TYPE0)); 850 amdgpu_ring_write(ring, seq); 851 852 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 853 0, 0, PACKETJ_TYPE0)); 854 amdgpu_ring_write(ring, lower_32_bits(addr)); 855 856 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 857 0, 0, PACKETJ_TYPE0)); 858 amdgpu_ring_write(ring, upper_32_bits(addr)); 859 860 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 861 0, 0, PACKETJ_TYPE0)); 862 amdgpu_ring_write(ring, 0x8); 863 864 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 865 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 866 amdgpu_ring_write(ring, 0); 867 868 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 869 amdgpu_ring_write(ring, 0); 870 871 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 872 amdgpu_ring_write(ring, 0); 873 874 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 875 amdgpu_ring_write(ring, 0); 876 } 877 878 /** 879 * jpeg_v4_0_3_dec_ring_emit_ib - execute indirect buffer 880 * 881 * @ring: amdgpu_ring pointer 882 * @job: job to retrieve vmid from 883 * @ib: indirect buffer to execute 884 * @flags: unused 885 * 886 * Write ring commands to execute the indirect buffer. 887 */ 888 void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring, 889 struct amdgpu_job *job, 890 struct amdgpu_ib *ib, 891 uint32_t flags) 892 { 893 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 894 895 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 896 0, 0, PACKETJ_TYPE0)); 897 898 if (ring->funcs->parse_cs) 899 amdgpu_ring_write(ring, 0); 900 else 901 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 902 903 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 904 0, 0, PACKETJ_TYPE0)); 905 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 906 907 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 908 0, 0, PACKETJ_TYPE0)); 909 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 910 911 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 912 0, 0, PACKETJ_TYPE0)); 913 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 914 915 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 916 0, 0, PACKETJ_TYPE0)); 917 amdgpu_ring_write(ring, ib->length_dw); 918 919 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 920 0, 0, PACKETJ_TYPE0)); 921 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 922 923 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 924 0, 0, PACKETJ_TYPE0)); 925 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 926 927 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 928 amdgpu_ring_write(ring, 0); 929 930 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 931 0, 0, PACKETJ_TYPE0)); 932 amdgpu_ring_write(ring, 0x01400200); 933 934 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 935 0, 0, PACKETJ_TYPE0)); 936 amdgpu_ring_write(ring, 0x2); 937 938 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_STATUS_INTERNAL_OFFSET, 939 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 940 amdgpu_ring_write(ring, 0x2); 941 } 942 943 void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 944 uint32_t val, uint32_t mask) 945 { 946 uint32_t reg_offset; 947 948 /* Use normalized offsets if required */ 949 if (jpeg_v4_0_3_normalizn_reqd(ring->adev)) 950 reg = NORMALIZE_JPEG_REG_OFFSET(reg); 951 952 reg_offset = (reg << 2); 953 954 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 955 0, 0, PACKETJ_TYPE0)); 956 amdgpu_ring_write(ring, 0x01400200); 957 958 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 959 0, 0, PACKETJ_TYPE0)); 960 amdgpu_ring_write(ring, val); 961 962 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 963 0, 0, PACKETJ_TYPE0)); 964 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 965 amdgpu_ring_write(ring, 0); 966 amdgpu_ring_write(ring, 967 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 968 } else { 969 amdgpu_ring_write(ring, reg_offset); 970 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 971 0, 0, PACKETJ_TYPE3)); 972 } 973 amdgpu_ring_write(ring, mask); 974 } 975 976 void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 977 unsigned int vmid, uint64_t pd_addr) 978 { 979 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 980 uint32_t data0, data1, mask; 981 982 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 983 984 /* wait for register write */ 985 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 986 data1 = lower_32_bits(pd_addr); 987 mask = 0xffffffff; 988 jpeg_v4_0_3_dec_ring_emit_reg_wait(ring, data0, data1, mask); 989 } 990 991 void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 992 { 993 uint32_t reg_offset; 994 995 /* Use normalized offsets if required */ 996 if (jpeg_v4_0_3_normalizn_reqd(ring->adev)) 997 reg = NORMALIZE_JPEG_REG_OFFSET(reg); 998 999 reg_offset = (reg << 2); 1000 1001 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 1002 0, 0, PACKETJ_TYPE0)); 1003 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 1004 amdgpu_ring_write(ring, 0); 1005 amdgpu_ring_write(ring, 1006 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 1007 } else { 1008 amdgpu_ring_write(ring, reg_offset); 1009 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 1010 0, 0, PACKETJ_TYPE0)); 1011 } 1012 amdgpu_ring_write(ring, val); 1013 } 1014 1015 void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) 1016 { 1017 int i; 1018 1019 WARN_ON(ring->wptr % 2 || count % 2); 1020 1021 for (i = 0; i < count / 2; i++) { 1022 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 1023 amdgpu_ring_write(ring, 0); 1024 } 1025 } 1026 1027 static bool jpeg_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block) 1028 { 1029 struct amdgpu_device *adev = ip_block->adev; 1030 bool ret = true; 1031 int i, j; 1032 1033 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1034 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 1035 ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i), 1036 regUVD_JRBC0_UVD_JRBC_STATUS, jpeg_v4_0_3_core_reg_offset(j)) & 1037 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 1038 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 1039 } 1040 } 1041 1042 return ret; 1043 } 1044 1045 static int jpeg_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 1046 { 1047 struct amdgpu_device *adev = ip_block->adev; 1048 int ret = 0; 1049 int i, j; 1050 1051 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1052 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 1053 ret &= (SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i), 1054 regUVD_JRBC0_UVD_JRBC_STATUS, jpeg_v4_0_3_core_reg_offset(j), 1055 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 1056 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 1057 } 1058 } 1059 return ret; 1060 } 1061 1062 static int jpeg_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1063 enum amd_clockgating_state state) 1064 { 1065 struct amdgpu_device *adev = ip_block->adev; 1066 bool enable = state == AMD_CG_STATE_GATE; 1067 int i; 1068 1069 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1070 if (enable) { 1071 if (!jpeg_v4_0_3_is_idle(ip_block)) 1072 return -EBUSY; 1073 jpeg_v4_0_3_enable_clock_gating(adev, i); 1074 } else { 1075 jpeg_v4_0_3_disable_clock_gating(adev, i); 1076 } 1077 } 1078 return 0; 1079 } 1080 1081 static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 1082 enum amd_powergating_state state) 1083 { 1084 struct amdgpu_device *adev = ip_block->adev; 1085 int ret; 1086 1087 if (amdgpu_sriov_vf(adev)) { 1088 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; 1089 return 0; 1090 } 1091 1092 if (state == adev->jpeg.cur_state) 1093 return 0; 1094 1095 if (state == AMD_PG_STATE_GATE) 1096 ret = jpeg_v4_0_3_stop(adev); 1097 else 1098 ret = jpeg_v4_0_3_start(adev); 1099 1100 if (!ret) 1101 adev->jpeg.cur_state = state; 1102 1103 return ret; 1104 } 1105 1106 static int jpeg_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 1107 struct amdgpu_irq_src *source, 1108 unsigned int type, 1109 enum amdgpu_interrupt_state state) 1110 { 1111 return 0; 1112 } 1113 1114 static int jpeg_v4_0_3_set_ras_interrupt_state(struct amdgpu_device *adev, 1115 struct amdgpu_irq_src *source, 1116 unsigned int type, 1117 enum amdgpu_interrupt_state state) 1118 { 1119 return 0; 1120 } 1121 1122 static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1123 struct amdgpu_irq_src *source, 1124 struct amdgpu_iv_entry *entry) 1125 { 1126 uint32_t i, inst; 1127 1128 i = node_id_to_phys_map[entry->node_id]; 1129 DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n"); 1130 1131 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) 1132 if (adev->jpeg.inst[inst].aid_id == i) 1133 break; 1134 1135 if (inst >= adev->jpeg.num_jpeg_inst) { 1136 dev_WARN_ONCE(adev->dev, 1, 1137 "Interrupt received for unknown JPEG instance %d", 1138 entry->node_id); 1139 return 0; 1140 } 1141 1142 switch (entry->src_id) { 1143 case VCN_4_0__SRCID__JPEG_DECODE: 1144 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); 1145 break; 1146 case VCN_4_0__SRCID__JPEG1_DECODE: 1147 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]); 1148 break; 1149 case VCN_4_0__SRCID__JPEG2_DECODE: 1150 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]); 1151 break; 1152 case VCN_4_0__SRCID__JPEG3_DECODE: 1153 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]); 1154 break; 1155 case VCN_4_0__SRCID__JPEG4_DECODE: 1156 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]); 1157 break; 1158 case VCN_4_0__SRCID__JPEG5_DECODE: 1159 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]); 1160 break; 1161 case VCN_4_0__SRCID__JPEG6_DECODE: 1162 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]); 1163 break; 1164 case VCN_4_0__SRCID__JPEG7_DECODE: 1165 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]); 1166 break; 1167 default: 1168 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1169 entry->src_id, entry->src_data[0]); 1170 break; 1171 } 1172 1173 return 0; 1174 } 1175 1176 static void jpeg_v4_0_3_core_stall_reset(struct amdgpu_ring *ring) 1177 { 1178 struct amdgpu_device *adev = ring->adev; 1179 int jpeg_inst = GET_INST(JPEG, ring->me); 1180 int reg_offset = jpeg_v4_0_3_core_reg_offset(ring->pipe); 1181 1182 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1183 regUVD_JMI0_UVD_JMI_CLIENT_STALL, 1184 reg_offset, 0x1F); 1185 SOC15_WAIT_ON_RREG_OFFSET(JPEG, jpeg_inst, 1186 regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS, 1187 reg_offset, 0x1F, 0x1F); 1188 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1189 regUVD_JMI0_JPEG_LMI_DROP, 1190 reg_offset, 0x1F); 1191 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 1 << ring->pipe); 1192 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1193 regUVD_JMI0_UVD_JMI_CLIENT_STALL, 1194 reg_offset, 0x00); 1195 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1196 regUVD_JMI0_JPEG_LMI_DROP, 1197 reg_offset, 0x00); 1198 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 0x00); 1199 } 1200 1201 static int jpeg_v4_0_3_ring_reset(struct amdgpu_ring *ring, 1202 unsigned int vmid, 1203 struct amdgpu_fence *timedout_fence) 1204 { 1205 struct amdgpu_device *adev = ring->adev; 1206 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1207 int r; 1208 1209 /* take the vcn reset mutex here because resetting VCN will reset jpeg as well */ 1210 mutex_lock(&vinst->engine_reset_mutex); 1211 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 1212 jpeg_v4_0_3_core_stall_reset(ring); 1213 jpeg_v4_0_3_start_jrbc(ring); 1214 r = amdgpu_ring_reset_helper_end(ring, timedout_fence); 1215 mutex_unlock(&vinst->engine_reset_mutex); 1216 return r; 1217 } 1218 1219 static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = { 1220 .name = "jpeg_v4_0_3", 1221 .early_init = jpeg_v4_0_3_early_init, 1222 .sw_init = jpeg_v4_0_3_sw_init, 1223 .sw_fini = jpeg_v4_0_3_sw_fini, 1224 .hw_init = jpeg_v4_0_3_hw_init, 1225 .hw_fini = jpeg_v4_0_3_hw_fini, 1226 .suspend = jpeg_v4_0_3_suspend, 1227 .resume = jpeg_v4_0_3_resume, 1228 .is_idle = jpeg_v4_0_3_is_idle, 1229 .wait_for_idle = jpeg_v4_0_3_wait_for_idle, 1230 .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state, 1231 .set_powergating_state = jpeg_v4_0_3_set_powergating_state, 1232 .dump_ip_state = amdgpu_jpeg_dump_ip_state, 1233 .print_ip_state = amdgpu_jpeg_print_ip_state, 1234 }; 1235 1236 static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { 1237 .type = AMDGPU_RING_TYPE_VCN_JPEG, 1238 .align_mask = 0xf, 1239 .no_user_fence = true, 1240 .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr, 1241 .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr, 1242 .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr, 1243 .parse_cs = amdgpu_jpeg_dec_parse_cs, 1244 .emit_frame_size = 1245 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1246 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1247 8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */ 1248 18 + 18 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */ 1249 8 + 16, 1250 .emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */ 1251 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, 1252 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, 1253 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, 1254 .emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush, 1255 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 1256 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 1257 .insert_nop = jpeg_v4_0_3_dec_ring_nop, 1258 .insert_start = jpeg_v4_0_3_dec_ring_insert_start, 1259 .insert_end = jpeg_v4_0_3_dec_ring_insert_end, 1260 .pad_ib = amdgpu_ring_generic_pad_ib, 1261 .begin_use = amdgpu_jpeg_ring_begin_use, 1262 .end_use = amdgpu_jpeg_ring_end_use, 1263 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, 1264 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, 1265 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1266 .reset = jpeg_v4_0_3_ring_reset, 1267 }; 1268 1269 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev) 1270 { 1271 int i, j, jpeg_inst; 1272 1273 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1274 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 1275 adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs; 1276 adev->jpeg.inst[i].ring_dec[j].me = i; 1277 adev->jpeg.inst[i].ring_dec[j].pipe = j; 1278 } 1279 jpeg_inst = GET_INST(JPEG, i); 1280 adev->jpeg.inst[i].aid_id = 1281 jpeg_inst / adev->jpeg.num_inst_per_aid; 1282 } 1283 } 1284 1285 static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = { 1286 .set = jpeg_v4_0_3_set_interrupt_state, 1287 .process = jpeg_v4_0_3_process_interrupt, 1288 }; 1289 1290 static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_ras_irq_funcs = { 1291 .set = jpeg_v4_0_3_set_ras_interrupt_state, 1292 .process = amdgpu_jpeg_process_poison_irq, 1293 }; 1294 1295 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1296 { 1297 int i; 1298 1299 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1300 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; 1301 } 1302 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs; 1303 1304 adev->jpeg.inst->ras_poison_irq.num_types = 1; 1305 adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_3_ras_irq_funcs; 1306 } 1307 1308 const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block = { 1309 .type = AMD_IP_BLOCK_TYPE_JPEG, 1310 .major = 4, 1311 .minor = 0, 1312 .rev = 3, 1313 .funcs = &jpeg_v4_0_3_ip_funcs, 1314 }; 1315 1316 static const struct amdgpu_ras_err_status_reg_entry jpeg_v4_0_3_ue_reg_list[] = { 1317 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0S, regVCN_UE_ERR_STATUS_HI_JPEG0S), 1318 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0S"}, 1319 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0D, regVCN_UE_ERR_STATUS_HI_JPEG0D), 1320 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0D"}, 1321 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1S, regVCN_UE_ERR_STATUS_HI_JPEG1S), 1322 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1S"}, 1323 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1D, regVCN_UE_ERR_STATUS_HI_JPEG1D), 1324 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1D"}, 1325 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2S, regVCN_UE_ERR_STATUS_HI_JPEG2S), 1326 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2S"}, 1327 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2D, regVCN_UE_ERR_STATUS_HI_JPEG2D), 1328 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2D"}, 1329 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3S, regVCN_UE_ERR_STATUS_HI_JPEG3S), 1330 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3S"}, 1331 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3D, regVCN_UE_ERR_STATUS_HI_JPEG3D), 1332 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3D"}, 1333 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4S, regVCN_UE_ERR_STATUS_HI_JPEG4S), 1334 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4S"}, 1335 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4D, regVCN_UE_ERR_STATUS_HI_JPEG4D), 1336 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4D"}, 1337 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5S, regVCN_UE_ERR_STATUS_HI_JPEG5S), 1338 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5S"}, 1339 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5D, regVCN_UE_ERR_STATUS_HI_JPEG5D), 1340 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5D"}, 1341 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6S, regVCN_UE_ERR_STATUS_HI_JPEG6S), 1342 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6S"}, 1343 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6D, regVCN_UE_ERR_STATUS_HI_JPEG6D), 1344 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6D"}, 1345 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7S, regVCN_UE_ERR_STATUS_HI_JPEG7S), 1346 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7S"}, 1347 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7D, regVCN_UE_ERR_STATUS_HI_JPEG7D), 1348 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7D"}, 1349 }; 1350 1351 static void jpeg_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1352 uint32_t jpeg_inst, 1353 void *ras_err_status) 1354 { 1355 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1356 1357 /* jpeg v4_0_3 only support uncorrectable errors */ 1358 amdgpu_ras_inst_query_ras_error_count(adev, 1359 jpeg_v4_0_3_ue_reg_list, 1360 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1361 NULL, 0, GET_INST(VCN, jpeg_inst), 1362 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1363 &err_data->ue_count); 1364 } 1365 1366 static void jpeg_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1367 void *ras_err_status) 1368 { 1369 uint32_t i; 1370 1371 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1372 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1373 return; 1374 } 1375 1376 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1377 jpeg_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1378 } 1379 1380 static void jpeg_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1381 uint32_t jpeg_inst) 1382 { 1383 amdgpu_ras_inst_reset_ras_error_count(adev, 1384 jpeg_v4_0_3_ue_reg_list, 1385 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1386 GET_INST(VCN, jpeg_inst)); 1387 } 1388 1389 static void jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1390 { 1391 uint32_t i; 1392 1393 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1394 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1395 return; 1396 } 1397 1398 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1399 jpeg_v4_0_3_inst_reset_ras_error_count(adev, i); 1400 } 1401 1402 static uint32_t jpeg_v4_0_3_query_poison_by_instance(struct amdgpu_device *adev, 1403 uint32_t instance, uint32_t sub_block) 1404 { 1405 uint32_t poison_stat = 0, reg_value = 0; 1406 1407 switch (sub_block) { 1408 case AMDGPU_JPEG_V4_0_3_JPEG0: 1409 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS); 1410 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF); 1411 break; 1412 case AMDGPU_JPEG_V4_0_3_JPEG1: 1413 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS); 1414 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF); 1415 break; 1416 default: 1417 break; 1418 } 1419 1420 if (poison_stat) 1421 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", 1422 instance, sub_block); 1423 1424 return poison_stat; 1425 } 1426 1427 static bool jpeg_v4_0_3_query_ras_poison_status(struct amdgpu_device *adev) 1428 { 1429 uint32_t inst = 0, sub = 0, poison_stat = 0; 1430 1431 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) 1432 for (sub = 0; sub < AMDGPU_JPEG_V4_0_3_MAX_SUB_BLOCK; sub++) 1433 poison_stat += 1434 jpeg_v4_0_3_query_poison_by_instance(adev, inst, sub); 1435 1436 return !!poison_stat; 1437 } 1438 1439 static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = { 1440 .query_ras_error_count = jpeg_v4_0_3_query_ras_error_count, 1441 .reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count, 1442 .query_poison_status = jpeg_v4_0_3_query_ras_poison_status, 1443 }; 1444 1445 static int jpeg_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1446 { 1447 int r; 1448 1449 r = amdgpu_ras_block_late_init(adev, ras_block); 1450 if (r) 1451 return r; 1452 1453 if (amdgpu_ras_is_supported(adev, ras_block->block) && 1454 adev->jpeg.inst->ras_poison_irq.funcs) { 1455 r = amdgpu_irq_get(adev, &adev->jpeg.inst->ras_poison_irq, 0); 1456 if (r) 1457 goto late_fini; 1458 } 1459 1460 return 0; 1461 1462 late_fini: 1463 amdgpu_ras_block_late_fini(adev, ras_block); 1464 1465 return r; 1466 } 1467 1468 static struct amdgpu_jpeg_ras jpeg_v4_0_3_ras = { 1469 .ras_block = { 1470 .hw_ops = &jpeg_v4_0_3_ras_hw_ops, 1471 .ras_late_init = jpeg_v4_0_3_ras_late_init, 1472 }, 1473 }; 1474 1475 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 1476 { 1477 adev->jpeg.ras = &jpeg_v4_0_3_ras; 1478 } 1479