1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "soc15.h" 27 #include "soc15d.h" 28 #include "jpeg_v4_0_3.h" 29 #include "mmsch_v4_0_3.h" 30 31 #include "vcn/vcn_4_0_3_offset.h" 32 #include "vcn/vcn_4_0_3_sh_mask.h" 33 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 34 35 enum jpeg_engin_status { 36 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0, 37 UVD_PGFSM_STATUS__UVDJ_PWR_OFF = 2, 38 }; 39 40 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev); 41 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 42 static int jpeg_v4_0_3_set_powergating_state(void *handle, 43 enum amd_powergating_state state); 44 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 45 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring); 46 47 static int amdgpu_ih_srcid_jpeg[] = { 48 VCN_4_0__SRCID__JPEG_DECODE, 49 VCN_4_0__SRCID__JPEG1_DECODE, 50 VCN_4_0__SRCID__JPEG2_DECODE, 51 VCN_4_0__SRCID__JPEG3_DECODE, 52 VCN_4_0__SRCID__JPEG4_DECODE, 53 VCN_4_0__SRCID__JPEG5_DECODE, 54 VCN_4_0__SRCID__JPEG6_DECODE, 55 VCN_4_0__SRCID__JPEG7_DECODE 56 }; 57 58 /** 59 * jpeg_v4_0_3_early_init - set function pointers 60 * 61 * @handle: amdgpu_device pointer 62 * 63 * Set ring and irq function pointers 64 */ 65 static int jpeg_v4_0_3_early_init(void *handle) 66 { 67 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 68 69 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS; 70 71 jpeg_v4_0_3_set_dec_ring_funcs(adev); 72 jpeg_v4_0_3_set_irq_funcs(adev); 73 jpeg_v4_0_3_set_ras_funcs(adev); 74 75 return 0; 76 } 77 78 /** 79 * jpeg_v4_0_3_sw_init - sw init for JPEG block 80 * 81 * @handle: amdgpu_device pointer 82 * 83 * Load firmware and sw initialization 84 */ 85 static int jpeg_v4_0_3_sw_init(void *handle) 86 { 87 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 88 struct amdgpu_ring *ring; 89 int i, j, r, jpeg_inst; 90 91 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 92 /* JPEG TRAP */ 93 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 94 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); 95 if (r) 96 return r; 97 } 98 99 r = amdgpu_jpeg_sw_init(adev); 100 if (r) 101 return r; 102 103 r = amdgpu_jpeg_resume(adev); 104 if (r) 105 return r; 106 107 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 108 jpeg_inst = GET_INST(JPEG, i); 109 110 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 111 ring = &adev->jpeg.inst[i].ring_dec[j]; 112 ring->use_doorbell = true; 113 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); 114 if (!amdgpu_sriov_vf(adev)) { 115 ring->doorbell_index = 116 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 117 1 + j + 9 * jpeg_inst; 118 } else { 119 if (j < 4) 120 ring->doorbell_index = 121 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 122 4 + j + 32 * jpeg_inst; 123 else 124 ring->doorbell_index = 125 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 126 8 + j + 32 * jpeg_inst; 127 } 128 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); 129 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 130 AMDGPU_RING_PRIO_DEFAULT, NULL); 131 if (r) 132 return r; 133 134 adev->jpeg.internal.jpeg_pitch[j] = 135 regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET; 136 adev->jpeg.inst[i].external.jpeg_pitch[j] = 137 SOC15_REG_OFFSET1( 138 JPEG, jpeg_inst, 139 regUVD_JRBC0_UVD_JRBC_SCRATCH0, 140 (j ? (0x40 * j - 0xc80) : 0)); 141 } 142 } 143 144 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 145 r = amdgpu_jpeg_ras_sw_init(adev); 146 if (r) { 147 dev_err(adev->dev, "Failed to initialize jpeg ras block!\n"); 148 return r; 149 } 150 } 151 152 return 0; 153 } 154 155 /** 156 * jpeg_v4_0_3_sw_fini - sw fini for JPEG block 157 * 158 * @handle: amdgpu_device pointer 159 * 160 * JPEG suspend and free up sw allocation 161 */ 162 static int jpeg_v4_0_3_sw_fini(void *handle) 163 { 164 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 165 int r; 166 167 r = amdgpu_jpeg_suspend(adev); 168 if (r) 169 return r; 170 171 r = amdgpu_jpeg_sw_fini(adev); 172 173 return r; 174 } 175 176 static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev) 177 { 178 struct amdgpu_ring *ring; 179 uint64_t ctx_addr; 180 uint32_t param, resp, expected; 181 uint32_t tmp, timeout; 182 183 struct amdgpu_mm_table *table = &adev->virt.mm_table; 184 uint32_t *table_loc; 185 uint32_t table_size; 186 uint32_t size, size_dw, item_offset; 187 uint32_t init_status; 188 int i, j, jpeg_inst; 189 190 struct mmsch_v4_0_cmd_direct_write 191 direct_wt = { {0} }; 192 struct mmsch_v4_0_cmd_end end = { {0} }; 193 struct mmsch_v4_0_3_init_header header; 194 195 direct_wt.cmd_header.command_type = 196 MMSCH_COMMAND__DIRECT_REG_WRITE; 197 end.cmd_header.command_type = 198 MMSCH_COMMAND__END; 199 200 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 201 jpeg_inst = GET_INST(JPEG, i); 202 203 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 204 header.version = MMSCH_VERSION; 205 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 206 207 table_loc = (uint32_t *)table->cpu_addr; 208 table_loc += header.total_size; 209 210 item_offset = header.total_size; 211 212 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) { 213 ring = &adev->jpeg.inst[i].ring_dec[j]; 214 table_size = 0; 215 216 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW); 217 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr)); 218 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH); 219 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr)); 220 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE); 221 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4); 222 223 if (j <= 3) { 224 header.mjpegdec0[j].table_offset = item_offset; 225 header.mjpegdec0[j].init_status = 0; 226 header.mjpegdec0[j].table_size = table_size; 227 } else { 228 header.mjpegdec1[j - 4].table_offset = item_offset; 229 header.mjpegdec1[j - 4].init_status = 0; 230 header.mjpegdec1[j - 4].table_size = table_size; 231 } 232 header.total_size += table_size; 233 item_offset += table_size; 234 } 235 236 MMSCH_V4_0_INSERT_END(); 237 238 /* send init table to MMSCH */ 239 size = sizeof(struct mmsch_v4_0_3_init_header); 240 table_loc = (uint32_t *)table->cpu_addr; 241 memcpy((void *)table_loc, &header, size); 242 243 ctx_addr = table->gpu_addr; 244 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 245 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 246 247 tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID); 248 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 249 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 250 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp); 251 252 size = header.total_size; 253 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size); 254 255 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0); 256 257 param = 0x00000001; 258 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param); 259 tmp = 0; 260 timeout = 1000; 261 resp = 0; 262 expected = MMSCH_VF_MAILBOX_RESP__OK; 263 init_status = 264 ((struct mmsch_v4_0_3_init_header *)(table_loc))->mjpegdec0[i].init_status; 265 while (resp != expected) { 266 resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP); 267 268 if (resp != 0) 269 break; 270 udelay(10); 271 tmp = tmp + 10; 272 if (tmp >= timeout) { 273 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 274 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 275 "(expected=0x%08x, readback=0x%08x)\n", 276 tmp, expected, resp); 277 return -EBUSY; 278 } 279 } 280 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE && 281 init_status != MMSCH_VF_ENGINE_STATUS__PASS) 282 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", 283 resp, init_status); 284 285 } 286 return 0; 287 } 288 289 /** 290 * jpeg_v4_0_3_hw_init - start and test JPEG block 291 * 292 * @handle: amdgpu_device pointer 293 * 294 */ 295 static int jpeg_v4_0_3_hw_init(void *handle) 296 { 297 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 298 struct amdgpu_ring *ring; 299 int i, j, r, jpeg_inst; 300 301 if (amdgpu_sriov_vf(adev)) { 302 r = jpeg_v4_0_3_start_sriov(adev); 303 if (r) 304 return r; 305 306 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 307 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 308 ring = &adev->jpeg.inst[i].ring_dec[j]; 309 ring->wptr = 0; 310 ring->wptr_old = 0; 311 jpeg_v4_0_3_dec_ring_set_wptr(ring); 312 ring->sched.ready = true; 313 } 314 } 315 } else { 316 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 317 jpeg_inst = GET_INST(JPEG, i); 318 319 ring = adev->jpeg.inst[i].ring_dec; 320 321 if (ring->use_doorbell) 322 adev->nbio.funcs->vcn_doorbell_range( 323 adev, ring->use_doorbell, 324 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 325 9 * jpeg_inst, 326 adev->jpeg.inst[i].aid_id); 327 328 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 329 ring = &adev->jpeg.inst[i].ring_dec[j]; 330 if (ring->use_doorbell) 331 WREG32_SOC15_OFFSET( 332 VCN, GET_INST(VCN, i), 333 regVCN_JPEG_DB_CTRL, 334 (ring->pipe ? (ring->pipe - 0x15) : 0), 335 ring->doorbell_index 336 << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 337 VCN_JPEG_DB_CTRL__EN_MASK); 338 r = amdgpu_ring_test_helper(ring); 339 if (r) 340 return r; 341 } 342 } 343 } 344 345 return 0; 346 } 347 348 /** 349 * jpeg_v4_0_3_hw_fini - stop the hardware block 350 * 351 * @handle: amdgpu_device pointer 352 * 353 * Stop the JPEG block, mark ring as not ready any more 354 */ 355 static int jpeg_v4_0_3_hw_fini(void *handle) 356 { 357 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 358 int ret = 0; 359 360 cancel_delayed_work_sync(&adev->jpeg.idle_work); 361 362 if (!amdgpu_sriov_vf(adev)) { 363 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) 364 ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE); 365 } 366 367 return ret; 368 } 369 370 /** 371 * jpeg_v4_0_3_suspend - suspend JPEG block 372 * 373 * @handle: amdgpu_device pointer 374 * 375 * HW fini and suspend JPEG block 376 */ 377 static int jpeg_v4_0_3_suspend(void *handle) 378 { 379 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 380 int r; 381 382 r = jpeg_v4_0_3_hw_fini(adev); 383 if (r) 384 return r; 385 386 r = amdgpu_jpeg_suspend(adev); 387 388 return r; 389 } 390 391 /** 392 * jpeg_v4_0_3_resume - resume JPEG block 393 * 394 * @handle: amdgpu_device pointer 395 * 396 * Resume firmware and hw init JPEG block 397 */ 398 static int jpeg_v4_0_3_resume(void *handle) 399 { 400 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 401 int r; 402 403 r = amdgpu_jpeg_resume(adev); 404 if (r) 405 return r; 406 407 r = jpeg_v4_0_3_hw_init(adev); 408 409 return r; 410 } 411 412 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) 413 { 414 int i, jpeg_inst; 415 uint32_t data; 416 417 jpeg_inst = GET_INST(JPEG, inst_idx); 418 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 419 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 420 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 421 data &= (~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1)); 422 } else { 423 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 424 } 425 426 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 427 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 428 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 429 430 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 431 data &= ~(JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 432 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 433 data &= ~(JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 434 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 435 } 436 437 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) 438 { 439 int i, jpeg_inst; 440 uint32_t data; 441 442 jpeg_inst = GET_INST(JPEG, inst_idx); 443 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 444 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 445 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 446 data |= (JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1); 447 } else { 448 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 449 } 450 451 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 452 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 453 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 454 455 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 456 data |= (JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 457 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 458 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 459 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 460 } 461 462 /** 463 * jpeg_v4_0_3_start - start JPEG block 464 * 465 * @adev: amdgpu_device pointer 466 * 467 * Setup and start the JPEG block 468 */ 469 static int jpeg_v4_0_3_start(struct amdgpu_device *adev) 470 { 471 struct amdgpu_ring *ring; 472 int i, j, jpeg_inst; 473 474 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 475 jpeg_inst = GET_INST(JPEG, i); 476 477 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 478 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 479 SOC15_WAIT_ON_RREG( 480 JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 481 UVD_PGFSM_STATUS__UVDJ_PWR_ON 482 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 483 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 484 485 /* disable anti hang mechanism */ 486 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 487 regUVD_JPEG_POWER_STATUS), 488 0, ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 489 490 /* JPEG disable CGC */ 491 jpeg_v4_0_3_disable_clock_gating(adev, i); 492 493 /* MJPEG global tiling registers */ 494 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX8_ADDR_CONFIG, 495 adev->gfx.config.gb_addr_config); 496 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX10_ADDR_CONFIG, 497 adev->gfx.config.gb_addr_config); 498 499 /* enable JMI channel */ 500 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0, 501 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 502 503 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 504 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 505 506 ring = &adev->jpeg.inst[i].ring_dec[j]; 507 508 /* enable System Interrupt for JRBC */ 509 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 510 regJPEG_SYS_INT_EN), 511 JPEG_SYS_INT_EN__DJRBC0_MASK << j, 512 ~(JPEG_SYS_INT_EN__DJRBC0_MASK << j)); 513 514 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 515 regUVD_JMI0_UVD_LMI_JRBC_RB_VMID, 516 reg_offset, 0); 517 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 518 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 519 reg_offset, 520 (0x00000001L | 0x00000002L)); 521 WREG32_SOC15_OFFSET( 522 JPEG, jpeg_inst, 523 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW, 524 reg_offset, lower_32_bits(ring->gpu_addr)); 525 WREG32_SOC15_OFFSET( 526 JPEG, jpeg_inst, 527 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 528 reg_offset, upper_32_bits(ring->gpu_addr)); 529 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 530 regUVD_JRBC0_UVD_JRBC_RB_RPTR, 531 reg_offset, 0); 532 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 533 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 534 reg_offset, 0); 535 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 536 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 537 reg_offset, 0x00000002L); 538 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 539 regUVD_JRBC0_UVD_JRBC_RB_SIZE, 540 reg_offset, ring->ring_size / 4); 541 ring->wptr = RREG32_SOC15_OFFSET( 542 JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_RB_WPTR, 543 reg_offset); 544 } 545 } 546 547 return 0; 548 } 549 550 /** 551 * jpeg_v4_0_3_stop - stop JPEG block 552 * 553 * @adev: amdgpu_device pointer 554 * 555 * stop the JPEG block 556 */ 557 static int jpeg_v4_0_3_stop(struct amdgpu_device *adev) 558 { 559 int i, jpeg_inst; 560 561 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 562 jpeg_inst = GET_INST(JPEG, i); 563 /* reset JMI */ 564 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 565 UVD_JMI_CNTL__SOFT_RESET_MASK, 566 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 567 568 jpeg_v4_0_3_enable_clock_gating(adev, i); 569 570 /* enable anti hang mechanism */ 571 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, 572 regUVD_JPEG_POWER_STATUS), 573 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 574 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 575 576 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 577 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 578 SOC15_WAIT_ON_RREG( 579 JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 580 UVD_PGFSM_STATUS__UVDJ_PWR_OFF 581 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 582 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 583 } 584 585 return 0; 586 } 587 588 /** 589 * jpeg_v4_0_3_dec_ring_get_rptr - get read pointer 590 * 591 * @ring: amdgpu_ring pointer 592 * 593 * Returns the current hardware read pointer 594 */ 595 static uint64_t jpeg_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring *ring) 596 { 597 struct amdgpu_device *adev = ring->adev; 598 599 return RREG32_SOC15_OFFSET( 600 JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR, 601 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); 602 } 603 604 /** 605 * jpeg_v4_0_3_dec_ring_get_wptr - get write pointer 606 * 607 * @ring: amdgpu_ring pointer 608 * 609 * Returns the current hardware write pointer 610 */ 611 static uint64_t jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring) 612 { 613 struct amdgpu_device *adev = ring->adev; 614 615 if (ring->use_doorbell) 616 return adev->wb.wb[ring->wptr_offs]; 617 else 618 return RREG32_SOC15_OFFSET( 619 JPEG, GET_INST(JPEG, ring->me), 620 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 621 ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); 622 } 623 624 /** 625 * jpeg_v4_0_3_dec_ring_set_wptr - set write pointer 626 * 627 * @ring: amdgpu_ring pointer 628 * 629 * Commits the write pointer to the hardware 630 */ 631 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring) 632 { 633 struct amdgpu_device *adev = ring->adev; 634 635 if (ring->use_doorbell) { 636 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 637 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 638 } else { 639 WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), 640 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 641 (ring->pipe ? (0x40 * ring->pipe - 0xc80) : 642 0), 643 lower_32_bits(ring->wptr)); 644 } 645 } 646 647 /** 648 * jpeg_v4_0_3_dec_ring_insert_start - insert a start command 649 * 650 * @ring: amdgpu_ring pointer 651 * 652 * Write a start command to the ring. 653 */ 654 void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring) 655 { 656 if (!amdgpu_sriov_vf(ring->adev)) { 657 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 658 0, 0, PACKETJ_TYPE0)); 659 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 660 } 661 662 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 663 0, 0, PACKETJ_TYPE0)); 664 amdgpu_ring_write(ring, 0x80004000); 665 } 666 667 /** 668 * jpeg_v4_0_3_dec_ring_insert_end - insert a end command 669 * 670 * @ring: amdgpu_ring pointer 671 * 672 * Write a end command to the ring. 673 */ 674 void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring) 675 { 676 if (!amdgpu_sriov_vf(ring->adev)) { 677 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 678 0, 0, PACKETJ_TYPE0)); 679 amdgpu_ring_write(ring, 0x62a04); 680 } 681 682 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 683 0, 0, PACKETJ_TYPE0)); 684 amdgpu_ring_write(ring, 0x00004000); 685 } 686 687 /** 688 * jpeg_v4_0_3_dec_ring_emit_fence - emit an fence & trap command 689 * 690 * @ring: amdgpu_ring pointer 691 * @addr: address 692 * @seq: sequence number 693 * @flags: fence related flags 694 * 695 * Write a fence and a trap command to the ring. 696 */ 697 void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 698 unsigned int flags) 699 { 700 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 701 702 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 703 0, 0, PACKETJ_TYPE0)); 704 amdgpu_ring_write(ring, seq); 705 706 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 707 0, 0, PACKETJ_TYPE0)); 708 amdgpu_ring_write(ring, seq); 709 710 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 711 0, 0, PACKETJ_TYPE0)); 712 amdgpu_ring_write(ring, lower_32_bits(addr)); 713 714 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 715 0, 0, PACKETJ_TYPE0)); 716 amdgpu_ring_write(ring, upper_32_bits(addr)); 717 718 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 719 0, 0, PACKETJ_TYPE0)); 720 amdgpu_ring_write(ring, 0x8); 721 722 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 723 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 724 amdgpu_ring_write(ring, 0); 725 726 if (ring->adev->jpeg.inst[ring->me].aid_id) { 727 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET, 728 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0)); 729 amdgpu_ring_write(ring, 0x4); 730 } else { 731 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 732 amdgpu_ring_write(ring, 0); 733 } 734 735 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 736 0, 0, PACKETJ_TYPE0)); 737 amdgpu_ring_write(ring, 0x3fbc); 738 739 if (ring->adev->jpeg.inst[ring->me].aid_id) { 740 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET, 741 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0)); 742 amdgpu_ring_write(ring, 0x0); 743 } else { 744 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 745 amdgpu_ring_write(ring, 0); 746 } 747 748 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 749 0, 0, PACKETJ_TYPE0)); 750 amdgpu_ring_write(ring, 0x1); 751 752 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 753 amdgpu_ring_write(ring, 0); 754 } 755 756 /** 757 * jpeg_v4_0_3_dec_ring_emit_ib - execute indirect buffer 758 * 759 * @ring: amdgpu_ring pointer 760 * @job: job to retrieve vmid from 761 * @ib: indirect buffer to execute 762 * @flags: unused 763 * 764 * Write ring commands to execute the indirect buffer. 765 */ 766 void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring, 767 struct amdgpu_job *job, 768 struct amdgpu_ib *ib, 769 uint32_t flags) 770 { 771 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 772 773 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 774 0, 0, PACKETJ_TYPE0)); 775 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 776 777 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 778 0, 0, PACKETJ_TYPE0)); 779 amdgpu_ring_write(ring, (vmid | (vmid << 4))); 780 781 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 782 0, 0, PACKETJ_TYPE0)); 783 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 784 785 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 786 0, 0, PACKETJ_TYPE0)); 787 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 788 789 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 790 0, 0, PACKETJ_TYPE0)); 791 amdgpu_ring_write(ring, ib->length_dw); 792 793 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 794 0, 0, PACKETJ_TYPE0)); 795 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 796 797 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 798 0, 0, PACKETJ_TYPE0)); 799 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 800 801 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 802 amdgpu_ring_write(ring, 0); 803 804 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 805 0, 0, PACKETJ_TYPE0)); 806 amdgpu_ring_write(ring, 0x01400200); 807 808 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 809 0, 0, PACKETJ_TYPE0)); 810 amdgpu_ring_write(ring, 0x2); 811 812 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_STATUS_INTERNAL_OFFSET, 813 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 814 amdgpu_ring_write(ring, 0x2); 815 } 816 817 void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 818 uint32_t val, uint32_t mask) 819 { 820 uint32_t reg_offset = (reg << 2); 821 822 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 823 0, 0, PACKETJ_TYPE0)); 824 amdgpu_ring_write(ring, 0x01400200); 825 826 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 827 0, 0, PACKETJ_TYPE0)); 828 amdgpu_ring_write(ring, val); 829 830 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 831 0, 0, PACKETJ_TYPE0)); 832 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 833 amdgpu_ring_write(ring, 0); 834 amdgpu_ring_write(ring, 835 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 836 } else { 837 amdgpu_ring_write(ring, reg_offset); 838 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 839 0, 0, PACKETJ_TYPE3)); 840 } 841 amdgpu_ring_write(ring, mask); 842 } 843 844 void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 845 unsigned int vmid, uint64_t pd_addr) 846 { 847 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 848 uint32_t data0, data1, mask; 849 850 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 851 852 /* wait for register write */ 853 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 854 data1 = lower_32_bits(pd_addr); 855 mask = 0xffffffff; 856 jpeg_v4_0_3_dec_ring_emit_reg_wait(ring, data0, data1, mask); 857 } 858 859 void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 860 { 861 uint32_t reg_offset = (reg << 2); 862 863 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 864 0, 0, PACKETJ_TYPE0)); 865 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 866 amdgpu_ring_write(ring, 0); 867 amdgpu_ring_write(ring, 868 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 869 } else { 870 amdgpu_ring_write(ring, reg_offset); 871 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 872 0, 0, PACKETJ_TYPE0)); 873 } 874 amdgpu_ring_write(ring, val); 875 } 876 877 void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) 878 { 879 int i; 880 881 WARN_ON(ring->wptr % 2 || count % 2); 882 883 for (i = 0; i < count / 2; i++) { 884 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 885 amdgpu_ring_write(ring, 0); 886 } 887 } 888 889 static bool jpeg_v4_0_3_is_idle(void *handle) 890 { 891 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 892 bool ret = false; 893 int i, j; 894 895 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 896 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 897 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 898 899 ret &= ((RREG32_SOC15_OFFSET( 900 JPEG, GET_INST(JPEG, i), 901 regUVD_JRBC0_UVD_JRBC_STATUS, 902 reg_offset) & 903 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 904 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 905 } 906 } 907 908 return ret; 909 } 910 911 static int jpeg_v4_0_3_wait_for_idle(void *handle) 912 { 913 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 914 int ret = 0; 915 int i, j; 916 917 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 918 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 919 unsigned int reg_offset = (j?(0x40 * j - 0xc80):0); 920 921 ret &= SOC15_WAIT_ON_RREG_OFFSET( 922 JPEG, GET_INST(JPEG, i), 923 regUVD_JRBC0_UVD_JRBC_STATUS, reg_offset, 924 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 925 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 926 } 927 } 928 return ret; 929 } 930 931 static int jpeg_v4_0_3_set_clockgating_state(void *handle, 932 enum amd_clockgating_state state) 933 { 934 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 935 bool enable = state == AMD_CG_STATE_GATE; 936 int i; 937 938 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 939 if (enable) { 940 if (!jpeg_v4_0_3_is_idle(handle)) 941 return -EBUSY; 942 jpeg_v4_0_3_enable_clock_gating(adev, i); 943 } else { 944 jpeg_v4_0_3_disable_clock_gating(adev, i); 945 } 946 } 947 return 0; 948 } 949 950 static int jpeg_v4_0_3_set_powergating_state(void *handle, 951 enum amd_powergating_state state) 952 { 953 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 954 int ret; 955 956 if (amdgpu_sriov_vf(adev)) { 957 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; 958 return 0; 959 } 960 961 if (state == adev->jpeg.cur_state) 962 return 0; 963 964 if (state == AMD_PG_STATE_GATE) 965 ret = jpeg_v4_0_3_stop(adev); 966 else 967 ret = jpeg_v4_0_3_start(adev); 968 969 if (!ret) 970 adev->jpeg.cur_state = state; 971 972 return ret; 973 } 974 975 static int jpeg_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 976 struct amdgpu_irq_src *source, 977 unsigned int type, 978 enum amdgpu_interrupt_state state) 979 { 980 return 0; 981 } 982 983 static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev, 984 struct amdgpu_irq_src *source, 985 struct amdgpu_iv_entry *entry) 986 { 987 uint32_t i, inst; 988 989 i = node_id_to_phys_map[entry->node_id]; 990 DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n"); 991 992 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) 993 if (adev->jpeg.inst[inst].aid_id == i) 994 break; 995 996 if (inst >= adev->jpeg.num_jpeg_inst) { 997 dev_WARN_ONCE(adev->dev, 1, 998 "Interrupt received for unknown JPEG instance %d", 999 entry->node_id); 1000 return 0; 1001 } 1002 1003 switch (entry->src_id) { 1004 case VCN_4_0__SRCID__JPEG_DECODE: 1005 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); 1006 break; 1007 case VCN_4_0__SRCID__JPEG1_DECODE: 1008 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]); 1009 break; 1010 case VCN_4_0__SRCID__JPEG2_DECODE: 1011 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]); 1012 break; 1013 case VCN_4_0__SRCID__JPEG3_DECODE: 1014 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]); 1015 break; 1016 case VCN_4_0__SRCID__JPEG4_DECODE: 1017 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]); 1018 break; 1019 case VCN_4_0__SRCID__JPEG5_DECODE: 1020 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]); 1021 break; 1022 case VCN_4_0__SRCID__JPEG6_DECODE: 1023 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]); 1024 break; 1025 case VCN_4_0__SRCID__JPEG7_DECODE: 1026 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]); 1027 break; 1028 default: 1029 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1030 entry->src_id, entry->src_data[0]); 1031 break; 1032 } 1033 1034 return 0; 1035 } 1036 1037 static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = { 1038 .name = "jpeg_v4_0_3", 1039 .early_init = jpeg_v4_0_3_early_init, 1040 .late_init = NULL, 1041 .sw_init = jpeg_v4_0_3_sw_init, 1042 .sw_fini = jpeg_v4_0_3_sw_fini, 1043 .hw_init = jpeg_v4_0_3_hw_init, 1044 .hw_fini = jpeg_v4_0_3_hw_fini, 1045 .suspend = jpeg_v4_0_3_suspend, 1046 .resume = jpeg_v4_0_3_resume, 1047 .is_idle = jpeg_v4_0_3_is_idle, 1048 .wait_for_idle = jpeg_v4_0_3_wait_for_idle, 1049 .check_soft_reset = NULL, 1050 .pre_soft_reset = NULL, 1051 .soft_reset = NULL, 1052 .post_soft_reset = NULL, 1053 .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state, 1054 .set_powergating_state = jpeg_v4_0_3_set_powergating_state, 1055 .dump_ip_state = NULL, 1056 .print_ip_state = NULL, 1057 }; 1058 1059 static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { 1060 .type = AMDGPU_RING_TYPE_VCN_JPEG, 1061 .align_mask = 0xf, 1062 .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr, 1063 .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr, 1064 .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr, 1065 .emit_frame_size = 1066 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1067 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1068 8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */ 1069 22 + 22 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */ 1070 8 + 16, 1071 .emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */ 1072 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, 1073 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, 1074 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, 1075 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 1076 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 1077 .insert_nop = jpeg_v4_0_3_dec_ring_nop, 1078 .insert_start = jpeg_v4_0_3_dec_ring_insert_start, 1079 .insert_end = jpeg_v4_0_3_dec_ring_insert_end, 1080 .pad_ib = amdgpu_ring_generic_pad_ib, 1081 .begin_use = amdgpu_jpeg_ring_begin_use, 1082 .end_use = amdgpu_jpeg_ring_end_use, 1083 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, 1084 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, 1085 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1086 }; 1087 1088 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev) 1089 { 1090 int i, j, jpeg_inst; 1091 1092 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1093 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 1094 adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs; 1095 adev->jpeg.inst[i].ring_dec[j].me = i; 1096 adev->jpeg.inst[i].ring_dec[j].pipe = j; 1097 } 1098 jpeg_inst = GET_INST(JPEG, i); 1099 adev->jpeg.inst[i].aid_id = 1100 jpeg_inst / adev->jpeg.num_inst_per_aid; 1101 } 1102 } 1103 1104 static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = { 1105 .set = jpeg_v4_0_3_set_interrupt_state, 1106 .process = jpeg_v4_0_3_process_interrupt, 1107 }; 1108 1109 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1110 { 1111 int i; 1112 1113 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1114 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; 1115 } 1116 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs; 1117 } 1118 1119 const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block = { 1120 .type = AMD_IP_BLOCK_TYPE_JPEG, 1121 .major = 4, 1122 .minor = 0, 1123 .rev = 3, 1124 .funcs = &jpeg_v4_0_3_ip_funcs, 1125 }; 1126 1127 static const struct amdgpu_ras_err_status_reg_entry jpeg_v4_0_3_ue_reg_list[] = { 1128 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0S, regVCN_UE_ERR_STATUS_HI_JPEG0S), 1129 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0S"}, 1130 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0D, regVCN_UE_ERR_STATUS_HI_JPEG0D), 1131 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0D"}, 1132 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1S, regVCN_UE_ERR_STATUS_HI_JPEG1S), 1133 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1S"}, 1134 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1D, regVCN_UE_ERR_STATUS_HI_JPEG1D), 1135 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1D"}, 1136 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2S, regVCN_UE_ERR_STATUS_HI_JPEG2S), 1137 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2S"}, 1138 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2D, regVCN_UE_ERR_STATUS_HI_JPEG2D), 1139 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2D"}, 1140 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3S, regVCN_UE_ERR_STATUS_HI_JPEG3S), 1141 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3S"}, 1142 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3D, regVCN_UE_ERR_STATUS_HI_JPEG3D), 1143 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3D"}, 1144 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4S, regVCN_UE_ERR_STATUS_HI_JPEG4S), 1145 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4S"}, 1146 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4D, regVCN_UE_ERR_STATUS_HI_JPEG4D), 1147 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4D"}, 1148 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5S, regVCN_UE_ERR_STATUS_HI_JPEG5S), 1149 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5S"}, 1150 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5D, regVCN_UE_ERR_STATUS_HI_JPEG5D), 1151 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5D"}, 1152 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6S, regVCN_UE_ERR_STATUS_HI_JPEG6S), 1153 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6S"}, 1154 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6D, regVCN_UE_ERR_STATUS_HI_JPEG6D), 1155 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6D"}, 1156 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7S, regVCN_UE_ERR_STATUS_HI_JPEG7S), 1157 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7S"}, 1158 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7D, regVCN_UE_ERR_STATUS_HI_JPEG7D), 1159 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7D"}, 1160 }; 1161 1162 static void jpeg_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1163 uint32_t jpeg_inst, 1164 void *ras_err_status) 1165 { 1166 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1167 1168 /* jpeg v4_0_3 only support uncorrectable errors */ 1169 amdgpu_ras_inst_query_ras_error_count(adev, 1170 jpeg_v4_0_3_ue_reg_list, 1171 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1172 NULL, 0, GET_INST(VCN, jpeg_inst), 1173 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1174 &err_data->ue_count); 1175 } 1176 1177 static void jpeg_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1178 void *ras_err_status) 1179 { 1180 uint32_t i; 1181 1182 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1183 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1184 return; 1185 } 1186 1187 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1188 jpeg_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1189 } 1190 1191 static void jpeg_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1192 uint32_t jpeg_inst) 1193 { 1194 amdgpu_ras_inst_reset_ras_error_count(adev, 1195 jpeg_v4_0_3_ue_reg_list, 1196 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1197 GET_INST(VCN, jpeg_inst)); 1198 } 1199 1200 static void jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1201 { 1202 uint32_t i; 1203 1204 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1205 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1206 return; 1207 } 1208 1209 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1210 jpeg_v4_0_3_inst_reset_ras_error_count(adev, i); 1211 } 1212 1213 static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = { 1214 .query_ras_error_count = jpeg_v4_0_3_query_ras_error_count, 1215 .reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count, 1216 }; 1217 1218 static struct amdgpu_jpeg_ras jpeg_v4_0_3_ras = { 1219 .ras_block = { 1220 .hw_ops = &jpeg_v4_0_3_ras_hw_ops, 1221 }, 1222 }; 1223 1224 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 1225 { 1226 adev->jpeg.ras = &jpeg_v4_0_3_ras; 1227 } 1228