1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "soc15.h" 27 #include "soc15d.h" 28 #include "jpeg_v2_0.h" 29 #include "jpeg_v4_0_3.h" 30 #include "mmsch_v4_0_3.h" 31 32 #include "vcn/vcn_4_0_3_offset.h" 33 #include "vcn/vcn_4_0_3_sh_mask.h" 34 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 35 36 #define NORMALIZE_JPEG_REG_OFFSET(offset) \ 37 (offset & 0x1FFFF) 38 39 enum jpeg_engin_status { 40 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0, 41 UVD_PGFSM_STATUS__UVDJ_PWR_OFF = 2, 42 }; 43 44 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev); 45 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 46 static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 47 enum amd_powergating_state state); 48 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 49 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring); 50 51 static int amdgpu_ih_srcid_jpeg[] = { 52 VCN_4_0__SRCID__JPEG_DECODE, 53 VCN_4_0__SRCID__JPEG1_DECODE, 54 VCN_4_0__SRCID__JPEG2_DECODE, 55 VCN_4_0__SRCID__JPEG3_DECODE, 56 VCN_4_0__SRCID__JPEG4_DECODE, 57 VCN_4_0__SRCID__JPEG5_DECODE, 58 VCN_4_0__SRCID__JPEG6_DECODE, 59 VCN_4_0__SRCID__JPEG7_DECODE 60 }; 61 62 static const struct amdgpu_hwip_reg_entry jpeg_reg_list_4_0_3[] = { 63 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), 64 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), 65 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_SYS_INT_STATUS), 66 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR), 67 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR), 68 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS), 69 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), 70 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), 71 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), 72 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), 73 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), 74 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), 75 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR), 76 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR), 77 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS), 78 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR), 79 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR), 80 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS), 81 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR), 82 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR), 83 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS), 84 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR), 85 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR), 86 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS), 87 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR), 88 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR), 89 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS), 90 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR), 91 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR), 92 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_STATUS), 93 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR), 94 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR), 95 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS), 96 }; 97 98 static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) 99 { 100 return (adev->jpeg.caps & AMDGPU_JPEG_CAPS(RRMT_ENABLED)) == 0; 101 } 102 103 static inline int jpeg_v4_0_3_core_reg_offset(u32 pipe) 104 { 105 if (pipe) 106 return ((0x40 * pipe) - 0xc80); 107 else 108 return 0; 109 } 110 111 /** 112 * jpeg_v4_0_3_early_init - set function pointers 113 * 114 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 115 * 116 * Set ring and irq function pointers 117 */ 118 static int jpeg_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) 119 { 120 struct amdgpu_device *adev = ip_block->adev; 121 122 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3; 123 124 jpeg_v4_0_3_set_dec_ring_funcs(adev); 125 jpeg_v4_0_3_set_irq_funcs(adev); 126 jpeg_v4_0_3_set_ras_funcs(adev); 127 128 return 0; 129 } 130 131 /** 132 * jpeg_v4_0_3_sw_init - sw init for JPEG block 133 * 134 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 135 * 136 * Load firmware and sw initialization 137 */ 138 static int jpeg_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 139 { 140 struct amdgpu_device *adev = ip_block->adev; 141 struct amdgpu_ring *ring; 142 int i, j, r, jpeg_inst; 143 144 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 145 /* JPEG TRAP */ 146 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 147 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); 148 if (r) 149 return r; 150 } 151 152 r = amdgpu_jpeg_sw_init(adev); 153 if (r) 154 return r; 155 156 r = amdgpu_jpeg_resume(adev); 157 if (r) 158 return r; 159 160 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 161 jpeg_inst = GET_INST(JPEG, i); 162 163 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 164 ring = &adev->jpeg.inst[i].ring_dec[j]; 165 ring->use_doorbell = true; 166 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); 167 if (!amdgpu_sriov_vf(adev)) { 168 ring->doorbell_index = 169 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 170 1 + j + 9 * jpeg_inst; 171 } else { 172 if (j < 4) 173 ring->doorbell_index = 174 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 175 4 + j + 32 * jpeg_inst; 176 else 177 ring->doorbell_index = 178 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 179 8 + j + 32 * jpeg_inst; 180 } 181 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); 182 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 183 AMDGPU_RING_PRIO_DEFAULT, NULL); 184 if (r) 185 return r; 186 187 adev->jpeg.internal.jpeg_pitch[j] = 188 regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET; 189 adev->jpeg.inst[i].external.jpeg_pitch[j] = 190 SOC15_REG_OFFSET1(JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_SCRATCH0, 191 jpeg_v4_0_3_core_reg_offset(j)); 192 } 193 } 194 195 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 196 r = amdgpu_jpeg_ras_sw_init(adev); 197 if (r) { 198 dev_err(adev->dev, "Failed to initialize jpeg ras block!\n"); 199 return r; 200 } 201 } 202 203 r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0_3, ARRAY_SIZE(jpeg_reg_list_4_0_3)); 204 if (r) 205 return r; 206 207 if (!amdgpu_sriov_vf(adev)) { 208 adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE; 209 r = amdgpu_jpeg_sysfs_reset_mask_init(adev); 210 if (r) 211 return r; 212 } 213 214 return 0; 215 } 216 217 /** 218 * jpeg_v4_0_3_sw_fini - sw fini for JPEG block 219 * 220 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 221 * 222 * JPEG suspend and free up sw allocation 223 */ 224 static int jpeg_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) 225 { 226 struct amdgpu_device *adev = ip_block->adev; 227 int r; 228 229 r = amdgpu_jpeg_suspend(adev); 230 if (r) 231 return r; 232 233 if (!amdgpu_sriov_vf(adev)) 234 amdgpu_jpeg_sysfs_reset_mask_fini(adev); 235 236 r = amdgpu_jpeg_sw_fini(adev); 237 238 return r; 239 } 240 241 static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev) 242 { 243 struct amdgpu_ring *ring; 244 uint64_t ctx_addr; 245 uint32_t param, resp, expected; 246 uint32_t tmp, timeout; 247 248 struct amdgpu_mm_table *table = &adev->virt.mm_table; 249 uint32_t *table_loc; 250 uint32_t table_size; 251 uint32_t size, size_dw, item_offset; 252 uint32_t init_status; 253 int i, j, jpeg_inst; 254 255 struct mmsch_v4_0_cmd_direct_write 256 direct_wt = { {0} }; 257 struct mmsch_v4_0_cmd_end end = { {0} }; 258 struct mmsch_v4_0_3_init_header header; 259 260 direct_wt.cmd_header.command_type = 261 MMSCH_COMMAND__DIRECT_REG_WRITE; 262 end.cmd_header.command_type = 263 MMSCH_COMMAND__END; 264 265 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 266 jpeg_inst = GET_INST(JPEG, i); 267 268 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 269 header.version = MMSCH_VERSION; 270 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 271 272 table_loc = (uint32_t *)table->cpu_addr; 273 table_loc += header.total_size; 274 275 item_offset = header.total_size; 276 277 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) { 278 ring = &adev->jpeg.inst[i].ring_dec[j]; 279 table_size = 0; 280 281 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW); 282 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr)); 283 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH); 284 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr)); 285 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE); 286 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4); 287 288 if (j <= 3) { 289 header.mjpegdec0[j].table_offset = item_offset; 290 header.mjpegdec0[j].init_status = 0; 291 header.mjpegdec0[j].table_size = table_size; 292 } else { 293 header.mjpegdec1[j - 4].table_offset = item_offset; 294 header.mjpegdec1[j - 4].init_status = 0; 295 header.mjpegdec1[j - 4].table_size = table_size; 296 } 297 header.total_size += table_size; 298 item_offset += table_size; 299 } 300 301 MMSCH_V4_0_INSERT_END(); 302 303 /* send init table to MMSCH */ 304 size = sizeof(struct mmsch_v4_0_3_init_header); 305 table_loc = (uint32_t *)table->cpu_addr; 306 memcpy((void *)table_loc, &header, size); 307 308 ctx_addr = table->gpu_addr; 309 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 310 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 311 312 tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID); 313 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 314 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 315 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp); 316 317 size = header.total_size; 318 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size); 319 320 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0); 321 322 param = 0x00000001; 323 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param); 324 tmp = 0; 325 timeout = 1000; 326 resp = 0; 327 expected = MMSCH_VF_MAILBOX_RESP__OK; 328 init_status = 329 ((struct mmsch_v4_0_3_init_header *)(table_loc))->mjpegdec0[i].init_status; 330 while (resp != expected) { 331 resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP); 332 333 if (resp != 0) 334 break; 335 udelay(10); 336 tmp = tmp + 10; 337 if (tmp >= timeout) { 338 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 339 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 340 "(expected=0x%08x, readback=0x%08x)\n", 341 tmp, expected, resp); 342 return -EBUSY; 343 } 344 } 345 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE && 346 init_status != MMSCH_VF_ENGINE_STATUS__PASS) 347 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", 348 resp, init_status); 349 350 } 351 return 0; 352 } 353 354 /** 355 * jpeg_v4_0_3_hw_init - start and test JPEG block 356 * 357 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 358 * 359 */ 360 static int jpeg_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) 361 { 362 struct amdgpu_device *adev = ip_block->adev; 363 struct amdgpu_ring *ring; 364 int i, j, r, jpeg_inst; 365 366 if (amdgpu_sriov_vf(adev)) { 367 r = jpeg_v4_0_3_start_sriov(adev); 368 if (r) 369 return r; 370 371 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 372 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 373 ring = &adev->jpeg.inst[i].ring_dec[j]; 374 ring->wptr = 0; 375 ring->wptr_old = 0; 376 jpeg_v4_0_3_dec_ring_set_wptr(ring); 377 ring->sched.ready = true; 378 } 379 } 380 } else { 381 /* This flag is not set for VF, assumed to be disabled always */ 382 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 383 0x100) 384 adev->jpeg.caps |= AMDGPU_JPEG_CAPS(RRMT_ENABLED); 385 386 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 387 jpeg_inst = GET_INST(JPEG, i); 388 389 ring = adev->jpeg.inst[i].ring_dec; 390 391 if (ring->use_doorbell) 392 adev->nbio.funcs->vcn_doorbell_range( 393 adev, ring->use_doorbell, 394 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 395 9 * jpeg_inst, 396 adev->jpeg.inst[i].aid_id); 397 398 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 399 ring = &adev->jpeg.inst[i].ring_dec[j]; 400 if (ring->use_doorbell) 401 WREG32_SOC15_OFFSET( 402 VCN, GET_INST(VCN, i), 403 regVCN_JPEG_DB_CTRL, 404 (ring->pipe ? (ring->pipe - 0x15) : 0), 405 ring->doorbell_index 406 << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 407 VCN_JPEG_DB_CTRL__EN_MASK); 408 r = amdgpu_ring_test_helper(ring); 409 if (r) 410 return r; 411 } 412 } 413 } 414 415 return 0; 416 } 417 418 /** 419 * jpeg_v4_0_3_hw_fini - stop the hardware block 420 * 421 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 422 * 423 * Stop the JPEG block, mark ring as not ready any more 424 */ 425 static int jpeg_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) 426 { 427 struct amdgpu_device *adev = ip_block->adev; 428 int ret = 0; 429 430 cancel_delayed_work_sync(&adev->jpeg.idle_work); 431 432 if (!amdgpu_sriov_vf(adev)) { 433 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) 434 ret = jpeg_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 435 } 436 437 return ret; 438 } 439 440 /** 441 * jpeg_v4_0_3_suspend - suspend JPEG block 442 * 443 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 444 * 445 * HW fini and suspend JPEG block 446 */ 447 static int jpeg_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) 448 { 449 int r; 450 451 r = jpeg_v4_0_3_hw_fini(ip_block); 452 if (r) 453 return r; 454 455 r = amdgpu_jpeg_suspend(ip_block->adev); 456 457 return r; 458 } 459 460 /** 461 * jpeg_v4_0_3_resume - resume JPEG block 462 * 463 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 464 * 465 * Resume firmware and hw init JPEG block 466 */ 467 static int jpeg_v4_0_3_resume(struct amdgpu_ip_block *ip_block) 468 { 469 int r; 470 471 r = amdgpu_jpeg_resume(ip_block->adev); 472 if (r) 473 return r; 474 475 r = jpeg_v4_0_3_hw_init(ip_block); 476 477 return r; 478 } 479 480 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) 481 { 482 int i, jpeg_inst; 483 uint32_t data; 484 485 jpeg_inst = GET_INST(JPEG, inst_idx); 486 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 487 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 488 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 489 data &= (~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1)); 490 } else { 491 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 492 } 493 494 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 495 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 496 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 497 498 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 499 data &= ~(JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 500 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 501 data &= ~(JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 502 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 503 } 504 505 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) 506 { 507 int i, jpeg_inst; 508 uint32_t data; 509 510 jpeg_inst = GET_INST(JPEG, inst_idx); 511 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 512 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 513 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 514 data |= (JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1); 515 } else { 516 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 517 } 518 519 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 520 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 521 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 522 523 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 524 data |= (JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 525 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 526 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 527 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 528 } 529 530 static void jpeg_v4_0_3_start_inst(struct amdgpu_device *adev, int inst) 531 { 532 int jpeg_inst = GET_INST(JPEG, inst); 533 534 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 535 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 536 SOC15_WAIT_ON_RREG(JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 537 UVD_PGFSM_STATUS__UVDJ_PWR_ON << 538 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 539 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 540 541 /* disable anti hang mechanism */ 542 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 543 0, ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 544 545 /* JPEG disable CGC */ 546 jpeg_v4_0_3_disable_clock_gating(adev, inst); 547 548 /* MJPEG global tiling registers */ 549 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX8_ADDR_CONFIG, 550 adev->gfx.config.gb_addr_config); 551 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX10_ADDR_CONFIG, 552 adev->gfx.config.gb_addr_config); 553 554 /* enable JMI channel */ 555 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0, 556 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 557 } 558 559 static void jpeg_v4_0_3_start_jrbc(struct amdgpu_ring *ring) 560 { 561 struct amdgpu_device *adev = ring->adev; 562 int jpeg_inst = GET_INST(JPEG, ring->me); 563 int reg_offset = jpeg_v4_0_3_core_reg_offset(ring->pipe); 564 565 /* enable System Interrupt for JRBC */ 566 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regJPEG_SYS_INT_EN), 567 JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe, 568 ~(JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe)); 569 570 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 571 regUVD_JMI0_UVD_LMI_JRBC_RB_VMID, 572 reg_offset, 0); 573 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 574 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 575 reg_offset, 576 (0x00000001L | 0x00000002L)); 577 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 578 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW, 579 reg_offset, lower_32_bits(ring->gpu_addr)); 580 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 581 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 582 reg_offset, upper_32_bits(ring->gpu_addr)); 583 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 584 regUVD_JRBC0_UVD_JRBC_RB_RPTR, 585 reg_offset, 0); 586 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 587 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 588 reg_offset, 0); 589 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 590 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 591 reg_offset, 0x00000002L); 592 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 593 regUVD_JRBC0_UVD_JRBC_RB_SIZE, 594 reg_offset, ring->ring_size / 4); 595 ring->wptr = RREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_RB_WPTR, 596 reg_offset); 597 } 598 599 /** 600 * jpeg_v4_0_3_start - start JPEG block 601 * 602 * @adev: amdgpu_device pointer 603 * 604 * Setup and start the JPEG block 605 */ 606 static int jpeg_v4_0_3_start(struct amdgpu_device *adev) 607 { 608 struct amdgpu_ring *ring; 609 int i, j; 610 611 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 612 jpeg_v4_0_3_start_inst(adev, i); 613 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 614 ring = &adev->jpeg.inst[i].ring_dec[j]; 615 jpeg_v4_0_3_start_jrbc(ring); 616 } 617 } 618 619 return 0; 620 } 621 622 static void jpeg_v4_0_3_stop_inst(struct amdgpu_device *adev, int inst) 623 { 624 int jpeg_inst = GET_INST(JPEG, inst); 625 /* reset JMI */ 626 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 627 UVD_JMI_CNTL__SOFT_RESET_MASK, 628 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 629 630 jpeg_v4_0_3_enable_clock_gating(adev, inst); 631 632 /* enable anti hang mechanism */ 633 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 634 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 635 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 636 637 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 638 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 639 SOC15_WAIT_ON_RREG(JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 640 UVD_PGFSM_STATUS__UVDJ_PWR_OFF << 641 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 642 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 643 } 644 645 /** 646 * jpeg_v4_0_3_stop - stop JPEG block 647 * 648 * @adev: amdgpu_device pointer 649 * 650 * stop the JPEG block 651 */ 652 static int jpeg_v4_0_3_stop(struct amdgpu_device *adev) 653 { 654 int i; 655 656 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) 657 jpeg_v4_0_3_stop_inst(adev, i); 658 659 return 0; 660 } 661 662 /** 663 * jpeg_v4_0_3_dec_ring_get_rptr - get read pointer 664 * 665 * @ring: amdgpu_ring pointer 666 * 667 * Returns the current hardware read pointer 668 */ 669 static uint64_t jpeg_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring *ring) 670 { 671 struct amdgpu_device *adev = ring->adev; 672 673 return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR, 674 jpeg_v4_0_3_core_reg_offset(ring->pipe)); 675 } 676 677 /** 678 * jpeg_v4_0_3_dec_ring_get_wptr - get write pointer 679 * 680 * @ring: amdgpu_ring pointer 681 * 682 * Returns the current hardware write pointer 683 */ 684 static uint64_t jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring) 685 { 686 struct amdgpu_device *adev = ring->adev; 687 688 if (ring->use_doorbell) 689 return adev->wb.wb[ring->wptr_offs]; 690 691 return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_WPTR, 692 jpeg_v4_0_3_core_reg_offset(ring->pipe)); 693 } 694 695 static void jpeg_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 696 { 697 /* JPEG engine access for HDP flush doesn't work when RRMT is enabled. 698 * This is a workaround to avoid any HDP flush through JPEG ring. 699 */ 700 } 701 702 /** 703 * jpeg_v4_0_3_dec_ring_set_wptr - set write pointer 704 * 705 * @ring: amdgpu_ring pointer 706 * 707 * Commits the write pointer to the hardware 708 */ 709 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring) 710 { 711 struct amdgpu_device *adev = ring->adev; 712 713 if (ring->use_doorbell) { 714 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 715 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 716 } else { 717 WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_WPTR, 718 jpeg_v4_0_3_core_reg_offset(ring->pipe), 719 lower_32_bits(ring->wptr)); 720 } 721 } 722 723 /** 724 * jpeg_v4_0_3_dec_ring_insert_start - insert a start command 725 * 726 * @ring: amdgpu_ring pointer 727 * 728 * Write a start command to the ring. 729 */ 730 void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring) 731 { 732 if (!amdgpu_sriov_vf(ring->adev)) { 733 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 734 0, 0, PACKETJ_TYPE0)); 735 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 736 737 amdgpu_ring_write(ring, 738 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, 739 0, PACKETJ_TYPE0)); 740 amdgpu_ring_write(ring, 0x80004000); 741 } 742 } 743 744 /** 745 * jpeg_v4_0_3_dec_ring_insert_end - insert a end command 746 * 747 * @ring: amdgpu_ring pointer 748 * 749 * Write a end command to the ring. 750 */ 751 void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring) 752 { 753 if (!amdgpu_sriov_vf(ring->adev)) { 754 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 755 0, 0, PACKETJ_TYPE0)); 756 amdgpu_ring_write(ring, 0x62a04); 757 758 amdgpu_ring_write(ring, 759 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, 760 0, PACKETJ_TYPE0)); 761 amdgpu_ring_write(ring, 0x00004000); 762 } 763 } 764 765 /** 766 * jpeg_v4_0_3_dec_ring_emit_fence - emit an fence & trap command 767 * 768 * @ring: amdgpu_ring pointer 769 * @addr: address 770 * @seq: sequence number 771 * @flags: fence related flags 772 * 773 * Write a fence and a trap command to the ring. 774 */ 775 void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 776 unsigned int flags) 777 { 778 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 779 780 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 781 0, 0, PACKETJ_TYPE0)); 782 amdgpu_ring_write(ring, seq); 783 784 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 785 0, 0, PACKETJ_TYPE0)); 786 amdgpu_ring_write(ring, seq); 787 788 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 789 0, 0, PACKETJ_TYPE0)); 790 amdgpu_ring_write(ring, lower_32_bits(addr)); 791 792 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 793 0, 0, PACKETJ_TYPE0)); 794 amdgpu_ring_write(ring, upper_32_bits(addr)); 795 796 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 797 0, 0, PACKETJ_TYPE0)); 798 amdgpu_ring_write(ring, 0x8); 799 800 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 801 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 802 amdgpu_ring_write(ring, 0); 803 804 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 805 amdgpu_ring_write(ring, 0); 806 807 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 808 amdgpu_ring_write(ring, 0); 809 810 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 811 amdgpu_ring_write(ring, 0); 812 } 813 814 /** 815 * jpeg_v4_0_3_dec_ring_emit_ib - execute indirect buffer 816 * 817 * @ring: amdgpu_ring pointer 818 * @job: job to retrieve vmid from 819 * @ib: indirect buffer to execute 820 * @flags: unused 821 * 822 * Write ring commands to execute the indirect buffer. 823 */ 824 void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring, 825 struct amdgpu_job *job, 826 struct amdgpu_ib *ib, 827 uint32_t flags) 828 { 829 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 830 831 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 832 0, 0, PACKETJ_TYPE0)); 833 834 if (ring->funcs->parse_cs) 835 amdgpu_ring_write(ring, 0); 836 else 837 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 838 839 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 840 0, 0, PACKETJ_TYPE0)); 841 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 842 843 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 844 0, 0, PACKETJ_TYPE0)); 845 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 846 847 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 848 0, 0, PACKETJ_TYPE0)); 849 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 850 851 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 852 0, 0, PACKETJ_TYPE0)); 853 amdgpu_ring_write(ring, ib->length_dw); 854 855 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 856 0, 0, PACKETJ_TYPE0)); 857 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 858 859 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 860 0, 0, PACKETJ_TYPE0)); 861 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 862 863 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 864 amdgpu_ring_write(ring, 0); 865 866 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 867 0, 0, PACKETJ_TYPE0)); 868 amdgpu_ring_write(ring, 0x01400200); 869 870 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 871 0, 0, PACKETJ_TYPE0)); 872 amdgpu_ring_write(ring, 0x2); 873 874 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_STATUS_INTERNAL_OFFSET, 875 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 876 amdgpu_ring_write(ring, 0x2); 877 } 878 879 void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 880 uint32_t val, uint32_t mask) 881 { 882 uint32_t reg_offset; 883 884 /* Use normalized offsets if required */ 885 if (jpeg_v4_0_3_normalizn_reqd(ring->adev)) 886 reg = NORMALIZE_JPEG_REG_OFFSET(reg); 887 888 reg_offset = (reg << 2); 889 890 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 891 0, 0, PACKETJ_TYPE0)); 892 amdgpu_ring_write(ring, 0x01400200); 893 894 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 895 0, 0, PACKETJ_TYPE0)); 896 amdgpu_ring_write(ring, val); 897 898 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 899 0, 0, PACKETJ_TYPE0)); 900 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 901 amdgpu_ring_write(ring, 0); 902 amdgpu_ring_write(ring, 903 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 904 } else { 905 amdgpu_ring_write(ring, reg_offset); 906 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 907 0, 0, PACKETJ_TYPE3)); 908 } 909 amdgpu_ring_write(ring, mask); 910 } 911 912 void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 913 unsigned int vmid, uint64_t pd_addr) 914 { 915 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 916 uint32_t data0, data1, mask; 917 918 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 919 920 /* wait for register write */ 921 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 922 data1 = lower_32_bits(pd_addr); 923 mask = 0xffffffff; 924 jpeg_v4_0_3_dec_ring_emit_reg_wait(ring, data0, data1, mask); 925 } 926 927 void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 928 { 929 uint32_t reg_offset; 930 931 /* Use normalized offsets if required */ 932 if (jpeg_v4_0_3_normalizn_reqd(ring->adev)) 933 reg = NORMALIZE_JPEG_REG_OFFSET(reg); 934 935 reg_offset = (reg << 2); 936 937 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 938 0, 0, PACKETJ_TYPE0)); 939 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 940 amdgpu_ring_write(ring, 0); 941 amdgpu_ring_write(ring, 942 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 943 } else { 944 amdgpu_ring_write(ring, reg_offset); 945 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 946 0, 0, PACKETJ_TYPE0)); 947 } 948 amdgpu_ring_write(ring, val); 949 } 950 951 void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) 952 { 953 int i; 954 955 WARN_ON(ring->wptr % 2 || count % 2); 956 957 for (i = 0; i < count / 2; i++) { 958 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 959 amdgpu_ring_write(ring, 0); 960 } 961 } 962 963 static bool jpeg_v4_0_3_is_idle(void *handle) 964 { 965 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 966 bool ret = false; 967 int i, j; 968 969 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 970 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 971 ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i), 972 regUVD_JRBC0_UVD_JRBC_STATUS, jpeg_v4_0_3_core_reg_offset(j)) & 973 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 974 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 975 } 976 } 977 978 return ret; 979 } 980 981 static int jpeg_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 982 { 983 struct amdgpu_device *adev = ip_block->adev; 984 int ret = 0; 985 int i, j; 986 987 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 988 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 989 ret &= (SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i), 990 regUVD_JRBC0_UVD_JRBC_STATUS, jpeg_v4_0_3_core_reg_offset(j), 991 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 992 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 993 } 994 } 995 return ret; 996 } 997 998 static int jpeg_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 999 enum amd_clockgating_state state) 1000 { 1001 struct amdgpu_device *adev = ip_block->adev; 1002 bool enable = state == AMD_CG_STATE_GATE; 1003 int i; 1004 1005 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1006 if (enable) { 1007 if (!jpeg_v4_0_3_is_idle(adev)) 1008 return -EBUSY; 1009 jpeg_v4_0_3_enable_clock_gating(adev, i); 1010 } else { 1011 jpeg_v4_0_3_disable_clock_gating(adev, i); 1012 } 1013 } 1014 return 0; 1015 } 1016 1017 static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 1018 enum amd_powergating_state state) 1019 { 1020 struct amdgpu_device *adev = ip_block->adev; 1021 int ret; 1022 1023 if (amdgpu_sriov_vf(adev)) { 1024 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; 1025 return 0; 1026 } 1027 1028 if (state == adev->jpeg.cur_state) 1029 return 0; 1030 1031 if (state == AMD_PG_STATE_GATE) 1032 ret = jpeg_v4_0_3_stop(adev); 1033 else 1034 ret = jpeg_v4_0_3_start(adev); 1035 1036 if (!ret) 1037 adev->jpeg.cur_state = state; 1038 1039 return ret; 1040 } 1041 1042 static int jpeg_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 1043 struct amdgpu_irq_src *source, 1044 unsigned int type, 1045 enum amdgpu_interrupt_state state) 1046 { 1047 return 0; 1048 } 1049 1050 static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1051 struct amdgpu_irq_src *source, 1052 struct amdgpu_iv_entry *entry) 1053 { 1054 uint32_t i, inst; 1055 1056 i = node_id_to_phys_map[entry->node_id]; 1057 DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n"); 1058 1059 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) 1060 if (adev->jpeg.inst[inst].aid_id == i) 1061 break; 1062 1063 if (inst >= adev->jpeg.num_jpeg_inst) { 1064 dev_WARN_ONCE(adev->dev, 1, 1065 "Interrupt received for unknown JPEG instance %d", 1066 entry->node_id); 1067 return 0; 1068 } 1069 1070 switch (entry->src_id) { 1071 case VCN_4_0__SRCID__JPEG_DECODE: 1072 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); 1073 break; 1074 case VCN_4_0__SRCID__JPEG1_DECODE: 1075 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]); 1076 break; 1077 case VCN_4_0__SRCID__JPEG2_DECODE: 1078 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]); 1079 break; 1080 case VCN_4_0__SRCID__JPEG3_DECODE: 1081 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]); 1082 break; 1083 case VCN_4_0__SRCID__JPEG4_DECODE: 1084 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]); 1085 break; 1086 case VCN_4_0__SRCID__JPEG5_DECODE: 1087 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]); 1088 break; 1089 case VCN_4_0__SRCID__JPEG6_DECODE: 1090 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]); 1091 break; 1092 case VCN_4_0__SRCID__JPEG7_DECODE: 1093 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]); 1094 break; 1095 default: 1096 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1097 entry->src_id, entry->src_data[0]); 1098 break; 1099 } 1100 1101 return 0; 1102 } 1103 1104 static void jpeg_v4_0_3_core_stall_reset(struct amdgpu_ring *ring) 1105 { 1106 struct amdgpu_device *adev = ring->adev; 1107 int jpeg_inst = GET_INST(JPEG, ring->me); 1108 int reg_offset = jpeg_v4_0_3_core_reg_offset(ring->pipe); 1109 1110 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1111 regUVD_JMI0_UVD_JMI_CLIENT_STALL, 1112 reg_offset, 0x1F); 1113 SOC15_WAIT_ON_RREG(JPEG, jpeg_inst, 1114 regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS, 1115 0x1F, 0x1F); 1116 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1117 regUVD_JMI0_JPEG_LMI_DROP, 1118 reg_offset, 0x1F); 1119 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1120 regJPEG_CORE_RST_CTRL, 1121 reg_offset, 1 << ring->pipe); 1122 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1123 regUVD_JMI0_UVD_JMI_CLIENT_STALL, 1124 reg_offset, 0x00); 1125 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1126 regUVD_JMI0_JPEG_LMI_DROP, 1127 reg_offset, 0x00); 1128 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1129 regJPEG_CORE_RST_CTRL, 1130 reg_offset, 0x00); 1131 } 1132 1133 static int jpeg_v4_0_3_ring_reset(struct amdgpu_ring *ring, unsigned int vmid) 1134 { 1135 if (amdgpu_sriov_vf(ring->adev)) 1136 return -EOPNOTSUPP; 1137 1138 jpeg_v4_0_3_core_stall_reset(ring); 1139 jpeg_v4_0_3_start_jrbc(ring); 1140 return amdgpu_ring_test_helper(ring); 1141 } 1142 1143 static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = { 1144 .name = "jpeg_v4_0_3", 1145 .early_init = jpeg_v4_0_3_early_init, 1146 .sw_init = jpeg_v4_0_3_sw_init, 1147 .sw_fini = jpeg_v4_0_3_sw_fini, 1148 .hw_init = jpeg_v4_0_3_hw_init, 1149 .hw_fini = jpeg_v4_0_3_hw_fini, 1150 .suspend = jpeg_v4_0_3_suspend, 1151 .resume = jpeg_v4_0_3_resume, 1152 .is_idle = jpeg_v4_0_3_is_idle, 1153 .wait_for_idle = jpeg_v4_0_3_wait_for_idle, 1154 .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state, 1155 .set_powergating_state = jpeg_v4_0_3_set_powergating_state, 1156 .dump_ip_state = amdgpu_jpeg_dump_ip_state, 1157 .print_ip_state = amdgpu_jpeg_print_ip_state, 1158 }; 1159 1160 static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { 1161 .type = AMDGPU_RING_TYPE_VCN_JPEG, 1162 .align_mask = 0xf, 1163 .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr, 1164 .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr, 1165 .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr, 1166 .parse_cs = jpeg_v2_dec_ring_parse_cs, 1167 .emit_frame_size = 1168 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1169 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1170 8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */ 1171 18 + 18 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */ 1172 8 + 16, 1173 .emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */ 1174 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, 1175 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, 1176 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, 1177 .emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush, 1178 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 1179 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 1180 .insert_nop = jpeg_v4_0_3_dec_ring_nop, 1181 .insert_start = jpeg_v4_0_3_dec_ring_insert_start, 1182 .insert_end = jpeg_v4_0_3_dec_ring_insert_end, 1183 .pad_ib = amdgpu_ring_generic_pad_ib, 1184 .begin_use = amdgpu_jpeg_ring_begin_use, 1185 .end_use = amdgpu_jpeg_ring_end_use, 1186 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, 1187 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, 1188 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1189 .reset = jpeg_v4_0_3_ring_reset, 1190 }; 1191 1192 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev) 1193 { 1194 int i, j, jpeg_inst; 1195 1196 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1197 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 1198 adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs; 1199 adev->jpeg.inst[i].ring_dec[j].me = i; 1200 adev->jpeg.inst[i].ring_dec[j].pipe = j; 1201 } 1202 jpeg_inst = GET_INST(JPEG, i); 1203 adev->jpeg.inst[i].aid_id = 1204 jpeg_inst / adev->jpeg.num_inst_per_aid; 1205 } 1206 } 1207 1208 static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = { 1209 .set = jpeg_v4_0_3_set_interrupt_state, 1210 .process = jpeg_v4_0_3_process_interrupt, 1211 }; 1212 1213 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1214 { 1215 int i; 1216 1217 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1218 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; 1219 } 1220 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs; 1221 } 1222 1223 const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block = { 1224 .type = AMD_IP_BLOCK_TYPE_JPEG, 1225 .major = 4, 1226 .minor = 0, 1227 .rev = 3, 1228 .funcs = &jpeg_v4_0_3_ip_funcs, 1229 }; 1230 1231 static const struct amdgpu_ras_err_status_reg_entry jpeg_v4_0_3_ue_reg_list[] = { 1232 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0S, regVCN_UE_ERR_STATUS_HI_JPEG0S), 1233 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0S"}, 1234 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0D, regVCN_UE_ERR_STATUS_HI_JPEG0D), 1235 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0D"}, 1236 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1S, regVCN_UE_ERR_STATUS_HI_JPEG1S), 1237 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1S"}, 1238 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1D, regVCN_UE_ERR_STATUS_HI_JPEG1D), 1239 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1D"}, 1240 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2S, regVCN_UE_ERR_STATUS_HI_JPEG2S), 1241 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2S"}, 1242 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2D, regVCN_UE_ERR_STATUS_HI_JPEG2D), 1243 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2D"}, 1244 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3S, regVCN_UE_ERR_STATUS_HI_JPEG3S), 1245 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3S"}, 1246 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3D, regVCN_UE_ERR_STATUS_HI_JPEG3D), 1247 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3D"}, 1248 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4S, regVCN_UE_ERR_STATUS_HI_JPEG4S), 1249 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4S"}, 1250 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4D, regVCN_UE_ERR_STATUS_HI_JPEG4D), 1251 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4D"}, 1252 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5S, regVCN_UE_ERR_STATUS_HI_JPEG5S), 1253 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5S"}, 1254 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5D, regVCN_UE_ERR_STATUS_HI_JPEG5D), 1255 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5D"}, 1256 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6S, regVCN_UE_ERR_STATUS_HI_JPEG6S), 1257 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6S"}, 1258 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6D, regVCN_UE_ERR_STATUS_HI_JPEG6D), 1259 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6D"}, 1260 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7S, regVCN_UE_ERR_STATUS_HI_JPEG7S), 1261 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7S"}, 1262 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7D, regVCN_UE_ERR_STATUS_HI_JPEG7D), 1263 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7D"}, 1264 }; 1265 1266 static void jpeg_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1267 uint32_t jpeg_inst, 1268 void *ras_err_status) 1269 { 1270 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1271 1272 /* jpeg v4_0_3 only support uncorrectable errors */ 1273 amdgpu_ras_inst_query_ras_error_count(adev, 1274 jpeg_v4_0_3_ue_reg_list, 1275 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1276 NULL, 0, GET_INST(VCN, jpeg_inst), 1277 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1278 &err_data->ue_count); 1279 } 1280 1281 static void jpeg_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1282 void *ras_err_status) 1283 { 1284 uint32_t i; 1285 1286 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1287 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1288 return; 1289 } 1290 1291 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1292 jpeg_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1293 } 1294 1295 static void jpeg_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1296 uint32_t jpeg_inst) 1297 { 1298 amdgpu_ras_inst_reset_ras_error_count(adev, 1299 jpeg_v4_0_3_ue_reg_list, 1300 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1301 GET_INST(VCN, jpeg_inst)); 1302 } 1303 1304 static void jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1305 { 1306 uint32_t i; 1307 1308 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1309 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1310 return; 1311 } 1312 1313 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1314 jpeg_v4_0_3_inst_reset_ras_error_count(adev, i); 1315 } 1316 1317 static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = { 1318 .query_ras_error_count = jpeg_v4_0_3_query_ras_error_count, 1319 .reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count, 1320 }; 1321 1322 static int jpeg_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 1323 enum aca_smu_type type, void *data) 1324 { 1325 struct aca_bank_info info; 1326 u64 misc0; 1327 int ret; 1328 1329 ret = aca_bank_info_decode(bank, &info); 1330 if (ret) 1331 return ret; 1332 1333 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 1334 switch (type) { 1335 case ACA_SMU_TYPE_UE: 1336 bank->aca_err_type = ACA_ERROR_TYPE_UE; 1337 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 1338 1ULL); 1339 break; 1340 case ACA_SMU_TYPE_CE: 1341 bank->aca_err_type = ACA_ERROR_TYPE_CE; 1342 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_CE, 1343 ACA_REG__MISC0__ERRCNT(misc0)); 1344 break; 1345 default: 1346 return -EINVAL; 1347 } 1348 1349 return ret; 1350 } 1351 1352 /* reference to smu driver if header file */ 1353 static int jpeg_v4_0_3_err_codes[] = { 1354 16, 17, 18, 19, 20, 21, 22, 23, /* JPEG[0-7][S|D] */ 1355 24, 25, 26, 27, 28, 29, 30, 31 1356 }; 1357 1358 static bool jpeg_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 1359 enum aca_smu_type type, void *data) 1360 { 1361 u32 instlo; 1362 1363 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 1364 instlo &= GENMASK(31, 1); 1365 1366 if (instlo != mmSMNAID_AID0_MCA_SMU) 1367 return false; 1368 1369 if (aca_bank_check_error_codes(handle->adev, bank, 1370 jpeg_v4_0_3_err_codes, 1371 ARRAY_SIZE(jpeg_v4_0_3_err_codes))) 1372 return false; 1373 1374 return true; 1375 } 1376 1377 static const struct aca_bank_ops jpeg_v4_0_3_aca_bank_ops = { 1378 .aca_bank_parser = jpeg_v4_0_3_aca_bank_parser, 1379 .aca_bank_is_valid = jpeg_v4_0_3_aca_bank_is_valid, 1380 }; 1381 1382 static const struct aca_info jpeg_v4_0_3_aca_info = { 1383 .hwip = ACA_HWIP_TYPE_SMU, 1384 .mask = ACA_ERROR_UE_MASK, 1385 .bank_ops = &jpeg_v4_0_3_aca_bank_ops, 1386 }; 1387 1388 static int jpeg_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1389 { 1390 int r; 1391 1392 r = amdgpu_ras_block_late_init(adev, ras_block); 1393 if (r) 1394 return r; 1395 1396 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__JPEG, 1397 &jpeg_v4_0_3_aca_info, NULL); 1398 if (r) 1399 goto late_fini; 1400 1401 return 0; 1402 1403 late_fini: 1404 amdgpu_ras_block_late_fini(adev, ras_block); 1405 1406 return r; 1407 } 1408 1409 static struct amdgpu_jpeg_ras jpeg_v4_0_3_ras = { 1410 .ras_block = { 1411 .hw_ops = &jpeg_v4_0_3_ras_hw_ops, 1412 .ras_late_init = jpeg_v4_0_3_ras_late_init, 1413 }, 1414 }; 1415 1416 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 1417 { 1418 adev->jpeg.ras = &jpeg_v4_0_3_ras; 1419 } 1420