1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "soc15.h" 27 #include "soc15d.h" 28 #include "jpeg_v2_0.h" 29 #include "jpeg_v4_0_3.h" 30 #include "mmsch_v4_0_3.h" 31 32 #include "vcn/vcn_4_0_3_offset.h" 33 #include "vcn/vcn_4_0_3_sh_mask.h" 34 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 35 36 #define NORMALIZE_JPEG_REG_OFFSET(offset) \ 37 (offset & 0x1FFFF) 38 39 enum jpeg_engin_status { 40 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0, 41 UVD_PGFSM_STATUS__UVDJ_PWR_OFF = 2, 42 }; 43 44 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev); 45 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 46 static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 47 enum amd_powergating_state state); 48 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 49 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring); 50 51 static int amdgpu_ih_srcid_jpeg[] = { 52 VCN_4_0__SRCID__JPEG_DECODE, 53 VCN_4_0__SRCID__JPEG1_DECODE, 54 VCN_4_0__SRCID__JPEG2_DECODE, 55 VCN_4_0__SRCID__JPEG3_DECODE, 56 VCN_4_0__SRCID__JPEG4_DECODE, 57 VCN_4_0__SRCID__JPEG5_DECODE, 58 VCN_4_0__SRCID__JPEG6_DECODE, 59 VCN_4_0__SRCID__JPEG7_DECODE 60 }; 61 62 static const struct amdgpu_hwip_reg_entry jpeg_reg_list_4_0_3[] = { 63 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), 64 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), 65 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_SYS_INT_STATUS), 66 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR), 67 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR), 68 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS), 69 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), 70 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), 71 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), 72 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), 73 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), 74 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), 75 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR), 76 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR), 77 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS), 78 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR), 79 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR), 80 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS), 81 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR), 82 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR), 83 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS), 84 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR), 85 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR), 86 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS), 87 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR), 88 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR), 89 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS), 90 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR), 91 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR), 92 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_STATUS), 93 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR), 94 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR), 95 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS), 96 }; 97 98 static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) 99 { 100 return (adev->jpeg.caps & AMDGPU_JPEG_CAPS(RRMT_ENABLED)) == 0; 101 } 102 103 static inline int jpeg_v4_0_3_core_reg_offset(u32 pipe) 104 { 105 if (pipe) 106 return ((0x40 * pipe) - 0xc80); 107 else 108 return 0; 109 } 110 111 /** 112 * jpeg_v4_0_3_early_init - set function pointers 113 * 114 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 115 * 116 * Set ring and irq function pointers 117 */ 118 static int jpeg_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) 119 { 120 struct amdgpu_device *adev = ip_block->adev; 121 122 adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3; 123 124 jpeg_v4_0_3_set_dec_ring_funcs(adev); 125 jpeg_v4_0_3_set_irq_funcs(adev); 126 jpeg_v4_0_3_set_ras_funcs(adev); 127 128 return 0; 129 } 130 131 /** 132 * jpeg_v4_0_3_sw_init - sw init for JPEG block 133 * 134 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 135 * 136 * Load firmware and sw initialization 137 */ 138 static int jpeg_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 139 { 140 struct amdgpu_device *adev = ip_block->adev; 141 struct amdgpu_ring *ring; 142 int i, j, r, jpeg_inst; 143 144 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 145 /* JPEG TRAP */ 146 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 147 amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); 148 if (r) 149 return r; 150 } 151 152 /* JPEG DJPEG POISON EVENT */ 153 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 154 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); 155 if (r) 156 return r; 157 158 /* JPEG EJPEG POISON EVENT */ 159 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 160 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); 161 if (r) 162 return r; 163 164 r = amdgpu_jpeg_sw_init(adev); 165 if (r) 166 return r; 167 168 r = amdgpu_jpeg_resume(adev); 169 if (r) 170 return r; 171 172 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 173 jpeg_inst = GET_INST(JPEG, i); 174 175 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 176 ring = &adev->jpeg.inst[i].ring_dec[j]; 177 ring->use_doorbell = true; 178 ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); 179 if (!amdgpu_sriov_vf(adev)) { 180 ring->doorbell_index = 181 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 182 1 + j + 9 * jpeg_inst; 183 } else { 184 if (j < 4) 185 ring->doorbell_index = 186 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 187 4 + j + 32 * jpeg_inst; 188 else 189 ring->doorbell_index = 190 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 191 8 + j + 32 * jpeg_inst; 192 } 193 sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); 194 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 195 AMDGPU_RING_PRIO_DEFAULT, NULL); 196 if (r) 197 return r; 198 199 adev->jpeg.internal.jpeg_pitch[j] = 200 regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET; 201 adev->jpeg.inst[i].external.jpeg_pitch[j] = 202 SOC15_REG_OFFSET1(JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_SCRATCH0, 203 jpeg_v4_0_3_core_reg_offset(j)); 204 } 205 } 206 207 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 208 r = amdgpu_jpeg_ras_sw_init(adev); 209 if (r) { 210 dev_err(adev->dev, "Failed to initialize jpeg ras block!\n"); 211 return r; 212 } 213 } 214 215 r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0_3, ARRAY_SIZE(jpeg_reg_list_4_0_3)); 216 if (r) 217 return r; 218 219 if (!amdgpu_sriov_vf(adev)) { 220 adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE; 221 r = amdgpu_jpeg_sysfs_reset_mask_init(adev); 222 if (r) 223 return r; 224 } 225 226 return 0; 227 } 228 229 /** 230 * jpeg_v4_0_3_sw_fini - sw fini for JPEG block 231 * 232 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 233 * 234 * JPEG suspend and free up sw allocation 235 */ 236 static int jpeg_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) 237 { 238 struct amdgpu_device *adev = ip_block->adev; 239 int r; 240 241 r = amdgpu_jpeg_suspend(adev); 242 if (r) 243 return r; 244 245 if (!amdgpu_sriov_vf(adev)) 246 amdgpu_jpeg_sysfs_reset_mask_fini(adev); 247 248 r = amdgpu_jpeg_sw_fini(adev); 249 250 return r; 251 } 252 253 static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev) 254 { 255 struct amdgpu_ring *ring; 256 uint64_t ctx_addr; 257 uint32_t param, resp, expected; 258 uint32_t tmp, timeout; 259 260 struct amdgpu_mm_table *table = &adev->virt.mm_table; 261 uint32_t *table_loc; 262 uint32_t table_size; 263 uint32_t size, size_dw, item_offset; 264 uint32_t init_status; 265 int i, j, jpeg_inst; 266 267 struct mmsch_v4_0_cmd_direct_write 268 direct_wt = { {0} }; 269 struct mmsch_v4_0_cmd_end end = { {0} }; 270 struct mmsch_v4_0_3_init_header header; 271 272 direct_wt.cmd_header.command_type = 273 MMSCH_COMMAND__DIRECT_REG_WRITE; 274 end.cmd_header.command_type = 275 MMSCH_COMMAND__END; 276 277 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 278 jpeg_inst = GET_INST(JPEG, i); 279 280 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 281 header.version = MMSCH_VERSION; 282 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 283 284 table_loc = (uint32_t *)table->cpu_addr; 285 table_loc += header.total_size; 286 287 item_offset = header.total_size; 288 289 for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) { 290 ring = &adev->jpeg.inst[i].ring_dec[j]; 291 table_size = 0; 292 293 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW); 294 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, lower_32_bits(ring->gpu_addr)); 295 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH); 296 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, upper_32_bits(ring->gpu_addr)); 297 tmp = SOC15_REG_OFFSET(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE); 298 MMSCH_V4_0_INSERT_DIRECT_WT(tmp, ring->ring_size / 4); 299 300 if (j <= 3) { 301 header.mjpegdec0[j].table_offset = item_offset; 302 header.mjpegdec0[j].init_status = 0; 303 header.mjpegdec0[j].table_size = table_size; 304 } else { 305 header.mjpegdec1[j - 4].table_offset = item_offset; 306 header.mjpegdec1[j - 4].init_status = 0; 307 header.mjpegdec1[j - 4].table_size = table_size; 308 } 309 header.total_size += table_size; 310 item_offset += table_size; 311 } 312 313 MMSCH_V4_0_INSERT_END(); 314 315 /* send init table to MMSCH */ 316 size = sizeof(struct mmsch_v4_0_3_init_header); 317 table_loc = (uint32_t *)table->cpu_addr; 318 memcpy((void *)table_loc, &header, size); 319 320 ctx_addr = table->gpu_addr; 321 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 322 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 323 324 tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID); 325 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 326 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 327 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp); 328 329 size = header.total_size; 330 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size); 331 332 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0); 333 334 param = 0x00000001; 335 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param); 336 tmp = 0; 337 timeout = 1000; 338 resp = 0; 339 expected = MMSCH_VF_MAILBOX_RESP__OK; 340 init_status = 341 ((struct mmsch_v4_0_3_init_header *)(table_loc))->mjpegdec0[i].init_status; 342 while (resp != expected) { 343 resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP); 344 345 if (resp != 0) 346 break; 347 udelay(10); 348 tmp = tmp + 10; 349 if (tmp >= timeout) { 350 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 351 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 352 "(expected=0x%08x, readback=0x%08x)\n", 353 tmp, expected, resp); 354 return -EBUSY; 355 } 356 } 357 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE && 358 init_status != MMSCH_VF_ENGINE_STATUS__PASS) 359 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", 360 resp, init_status); 361 362 } 363 return 0; 364 } 365 366 /** 367 * jpeg_v4_0_3_hw_init - start and test JPEG block 368 * 369 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 370 * 371 */ 372 static int jpeg_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) 373 { 374 struct amdgpu_device *adev = ip_block->adev; 375 struct amdgpu_ring *ring; 376 int i, j, r, jpeg_inst; 377 378 if (amdgpu_sriov_vf(adev)) { 379 r = jpeg_v4_0_3_start_sriov(adev); 380 if (r) 381 return r; 382 383 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 384 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 385 ring = &adev->jpeg.inst[i].ring_dec[j]; 386 ring->wptr = 0; 387 ring->wptr_old = 0; 388 jpeg_v4_0_3_dec_ring_set_wptr(ring); 389 ring->sched.ready = true; 390 } 391 } 392 } else { 393 /* This flag is not set for VF, assumed to be disabled always */ 394 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 395 0x100) 396 adev->jpeg.caps |= AMDGPU_JPEG_CAPS(RRMT_ENABLED); 397 398 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 399 jpeg_inst = GET_INST(JPEG, i); 400 401 ring = adev->jpeg.inst[i].ring_dec; 402 403 if (ring->use_doorbell) 404 adev->nbio.funcs->vcn_doorbell_range( 405 adev, ring->use_doorbell, 406 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 407 9 * jpeg_inst, 408 adev->jpeg.inst[i].aid_id); 409 410 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 411 ring = &adev->jpeg.inst[i].ring_dec[j]; 412 if (ring->use_doorbell) 413 WREG32_SOC15_OFFSET( 414 VCN, GET_INST(VCN, i), 415 regVCN_JPEG_DB_CTRL, 416 (ring->pipe ? (ring->pipe - 0x15) : 0), 417 ring->doorbell_index 418 << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 419 VCN_JPEG_DB_CTRL__EN_MASK); 420 r = amdgpu_ring_test_helper(ring); 421 if (r) 422 return r; 423 } 424 } 425 } 426 427 return 0; 428 } 429 430 /** 431 * jpeg_v4_0_3_hw_fini - stop the hardware block 432 * 433 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 434 * 435 * Stop the JPEG block, mark ring as not ready any more 436 */ 437 static int jpeg_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) 438 { 439 struct amdgpu_device *adev = ip_block->adev; 440 int ret = 0; 441 442 cancel_delayed_work_sync(&adev->jpeg.idle_work); 443 444 if (!amdgpu_sriov_vf(adev)) { 445 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) 446 ret = jpeg_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 447 } 448 449 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) 450 amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0); 451 452 return ret; 453 } 454 455 /** 456 * jpeg_v4_0_3_suspend - suspend JPEG block 457 * 458 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 459 * 460 * HW fini and suspend JPEG block 461 */ 462 static int jpeg_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) 463 { 464 int r; 465 466 r = jpeg_v4_0_3_hw_fini(ip_block); 467 if (r) 468 return r; 469 470 r = amdgpu_jpeg_suspend(ip_block->adev); 471 472 return r; 473 } 474 475 /** 476 * jpeg_v4_0_3_resume - resume JPEG block 477 * 478 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 479 * 480 * Resume firmware and hw init JPEG block 481 */ 482 static int jpeg_v4_0_3_resume(struct amdgpu_ip_block *ip_block) 483 { 484 int r; 485 486 r = amdgpu_jpeg_resume(ip_block->adev); 487 if (r) 488 return r; 489 490 r = jpeg_v4_0_3_hw_init(ip_block); 491 492 return r; 493 } 494 495 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) 496 { 497 int i, jpeg_inst; 498 uint32_t data; 499 500 jpeg_inst = GET_INST(JPEG, inst_idx); 501 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 502 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 503 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 504 data &= (~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1)); 505 } else { 506 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 507 } 508 509 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 510 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 511 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 512 513 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 514 data &= ~(JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 515 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 516 data &= ~(JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 517 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 518 } 519 520 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) 521 { 522 int i, jpeg_inst; 523 uint32_t data; 524 525 jpeg_inst = GET_INST(JPEG, inst_idx); 526 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL); 527 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 528 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 529 data |= (JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK << 1); 530 } else { 531 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 532 } 533 534 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 535 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 536 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_CTRL, data); 537 538 data = RREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE); 539 data |= (JPEG_CGC_GATE__JMCIF_MASK | JPEG_CGC_GATE__JRBBM_MASK); 540 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) 541 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK << i); 542 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CGC_GATE, data); 543 } 544 545 static void jpeg_v4_0_3_start_inst(struct amdgpu_device *adev, int inst) 546 { 547 int jpeg_inst = GET_INST(JPEG, inst); 548 549 WREG32_SOC15(JPEG, jpeg_inst, regUVD_PGFSM_CONFIG, 550 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT); 551 SOC15_WAIT_ON_RREG(JPEG, jpeg_inst, regUVD_PGFSM_STATUS, 552 UVD_PGFSM_STATUS__UVDJ_PWR_ON << 553 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT, 554 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 555 556 /* disable anti hang mechanism */ 557 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 558 0, ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 559 560 /* JPEG disable CGC */ 561 jpeg_v4_0_3_disable_clock_gating(adev, inst); 562 563 /* MJPEG global tiling registers */ 564 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX8_ADDR_CONFIG, 565 adev->gfx.config.gb_addr_config); 566 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_DEC_GFX10_ADDR_CONFIG, 567 adev->gfx.config.gb_addr_config); 568 569 /* enable JMI channel */ 570 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0, 571 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 572 } 573 574 static void jpeg_v4_0_3_start_jrbc(struct amdgpu_ring *ring) 575 { 576 struct amdgpu_device *adev = ring->adev; 577 int jpeg_inst = GET_INST(JPEG, ring->me); 578 int reg_offset = jpeg_v4_0_3_core_reg_offset(ring->pipe); 579 580 /* enable System Interrupt for JRBC */ 581 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regJPEG_SYS_INT_EN), 582 JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe, 583 ~(JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe)); 584 585 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 586 regUVD_JMI0_UVD_LMI_JRBC_RB_VMID, 587 reg_offset, 0); 588 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 589 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 590 reg_offset, 591 (0x00000001L | 0x00000002L)); 592 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 593 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_LOW, 594 reg_offset, lower_32_bits(ring->gpu_addr)); 595 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 596 regUVD_JMI0_UVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 597 reg_offset, upper_32_bits(ring->gpu_addr)); 598 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 599 regUVD_JRBC0_UVD_JRBC_RB_RPTR, 600 reg_offset, 0); 601 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 602 regUVD_JRBC0_UVD_JRBC_RB_WPTR, 603 reg_offset, 0); 604 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 605 regUVD_JRBC0_UVD_JRBC_RB_CNTL, 606 reg_offset, 0x00000002L); 607 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 608 regUVD_JRBC0_UVD_JRBC_RB_SIZE, 609 reg_offset, ring->ring_size / 4); 610 ring->wptr = RREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JRBC0_UVD_JRBC_RB_WPTR, 611 reg_offset); 612 } 613 614 /** 615 * jpeg_v4_0_3_start - start JPEG block 616 * 617 * @adev: amdgpu_device pointer 618 * 619 * Setup and start the JPEG block 620 */ 621 static int jpeg_v4_0_3_start(struct amdgpu_device *adev) 622 { 623 struct amdgpu_ring *ring; 624 int i, j; 625 626 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 627 jpeg_v4_0_3_start_inst(adev, i); 628 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 629 ring = &adev->jpeg.inst[i].ring_dec[j]; 630 jpeg_v4_0_3_start_jrbc(ring); 631 } 632 } 633 634 return 0; 635 } 636 637 static void jpeg_v4_0_3_stop_inst(struct amdgpu_device *adev, int inst) 638 { 639 int jpeg_inst = GET_INST(JPEG, inst); 640 /* reset JMI */ 641 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 642 UVD_JMI_CNTL__SOFT_RESET_MASK, 643 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 644 645 jpeg_v4_0_3_enable_clock_gating(adev, inst); 646 647 /* enable anti hang mechanism */ 648 WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 649 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 650 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 651 652 } 653 654 /** 655 * jpeg_v4_0_3_stop - stop JPEG block 656 * 657 * @adev: amdgpu_device pointer 658 * 659 * stop the JPEG block 660 */ 661 static int jpeg_v4_0_3_stop(struct amdgpu_device *adev) 662 { 663 int i; 664 665 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) 666 jpeg_v4_0_3_stop_inst(adev, i); 667 668 return 0; 669 } 670 671 /** 672 * jpeg_v4_0_3_dec_ring_get_rptr - get read pointer 673 * 674 * @ring: amdgpu_ring pointer 675 * 676 * Returns the current hardware read pointer 677 */ 678 static uint64_t jpeg_v4_0_3_dec_ring_get_rptr(struct amdgpu_ring *ring) 679 { 680 struct amdgpu_device *adev = ring->adev; 681 682 return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_RPTR, 683 jpeg_v4_0_3_core_reg_offset(ring->pipe)); 684 } 685 686 /** 687 * jpeg_v4_0_3_dec_ring_get_wptr - get write pointer 688 * 689 * @ring: amdgpu_ring pointer 690 * 691 * Returns the current hardware write pointer 692 */ 693 static uint64_t jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring) 694 { 695 struct amdgpu_device *adev = ring->adev; 696 697 if (ring->use_doorbell) 698 return adev->wb.wb[ring->wptr_offs]; 699 700 return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_WPTR, 701 jpeg_v4_0_3_core_reg_offset(ring->pipe)); 702 } 703 704 void jpeg_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 705 { 706 /* JPEG engine access for HDP flush doesn't work when RRMT is enabled. 707 * This is a workaround to avoid any HDP flush through JPEG ring. 708 */ 709 } 710 711 /** 712 * jpeg_v4_0_3_dec_ring_set_wptr - set write pointer 713 * 714 * @ring: amdgpu_ring pointer 715 * 716 * Commits the write pointer to the hardware 717 */ 718 static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring) 719 { 720 struct amdgpu_device *adev = ring->adev; 721 722 if (ring->use_doorbell) { 723 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 724 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 725 } else { 726 WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC0_UVD_JRBC_RB_WPTR, 727 jpeg_v4_0_3_core_reg_offset(ring->pipe), 728 lower_32_bits(ring->wptr)); 729 } 730 } 731 732 /** 733 * jpeg_v4_0_3_dec_ring_insert_start - insert a start command 734 * 735 * @ring: amdgpu_ring pointer 736 * 737 * Write a start command to the ring. 738 */ 739 void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring) 740 { 741 if (!amdgpu_sriov_vf(ring->adev)) { 742 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 743 0, 0, PACKETJ_TYPE0)); 744 amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 745 746 amdgpu_ring_write(ring, 747 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, 748 0, PACKETJ_TYPE0)); 749 amdgpu_ring_write(ring, 0x80004000); 750 } 751 } 752 753 /** 754 * jpeg_v4_0_3_dec_ring_insert_end - insert a end command 755 * 756 * @ring: amdgpu_ring pointer 757 * 758 * Write a end command to the ring. 759 */ 760 void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring) 761 { 762 if (!amdgpu_sriov_vf(ring->adev)) { 763 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 764 0, 0, PACKETJ_TYPE0)); 765 amdgpu_ring_write(ring, 0x62a04); 766 767 amdgpu_ring_write(ring, 768 PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, 769 0, PACKETJ_TYPE0)); 770 amdgpu_ring_write(ring, 0x00004000); 771 } 772 } 773 774 /** 775 * jpeg_v4_0_3_dec_ring_emit_fence - emit an fence & trap command 776 * 777 * @ring: amdgpu_ring pointer 778 * @addr: address 779 * @seq: sequence number 780 * @flags: fence related flags 781 * 782 * Write a fence and a trap command to the ring. 783 */ 784 void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 785 unsigned int flags) 786 { 787 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 788 789 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 790 0, 0, PACKETJ_TYPE0)); 791 amdgpu_ring_write(ring, seq); 792 793 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 794 0, 0, PACKETJ_TYPE0)); 795 amdgpu_ring_write(ring, seq); 796 797 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 798 0, 0, PACKETJ_TYPE0)); 799 amdgpu_ring_write(ring, lower_32_bits(addr)); 800 801 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 802 0, 0, PACKETJ_TYPE0)); 803 amdgpu_ring_write(ring, upper_32_bits(addr)); 804 805 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 806 0, 0, PACKETJ_TYPE0)); 807 amdgpu_ring_write(ring, 0x8); 808 809 amdgpu_ring_write(ring, PACKETJ(regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 810 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 811 amdgpu_ring_write(ring, 0); 812 813 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 814 amdgpu_ring_write(ring, 0); 815 816 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 817 amdgpu_ring_write(ring, 0); 818 819 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 820 amdgpu_ring_write(ring, 0); 821 } 822 823 /** 824 * jpeg_v4_0_3_dec_ring_emit_ib - execute indirect buffer 825 * 826 * @ring: amdgpu_ring pointer 827 * @job: job to retrieve vmid from 828 * @ib: indirect buffer to execute 829 * @flags: unused 830 * 831 * Write ring commands to execute the indirect buffer. 832 */ 833 void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring, 834 struct amdgpu_job *job, 835 struct amdgpu_ib *ib, 836 uint32_t flags) 837 { 838 unsigned int vmid = AMDGPU_JOB_GET_VMID(job); 839 840 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 841 0, 0, PACKETJ_TYPE0)); 842 843 if (ring->funcs->parse_cs) 844 amdgpu_ring_write(ring, 0); 845 else 846 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 847 848 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 849 0, 0, PACKETJ_TYPE0)); 850 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 851 852 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 853 0, 0, PACKETJ_TYPE0)); 854 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 855 856 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 857 0, 0, PACKETJ_TYPE0)); 858 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 859 860 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 861 0, 0, PACKETJ_TYPE0)); 862 amdgpu_ring_write(ring, ib->length_dw); 863 864 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 865 0, 0, PACKETJ_TYPE0)); 866 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 867 868 amdgpu_ring_write(ring, PACKETJ(regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 869 0, 0, PACKETJ_TYPE0)); 870 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 871 872 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 873 amdgpu_ring_write(ring, 0); 874 875 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 876 0, 0, PACKETJ_TYPE0)); 877 amdgpu_ring_write(ring, 0x01400200); 878 879 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 880 0, 0, PACKETJ_TYPE0)); 881 amdgpu_ring_write(ring, 0x2); 882 883 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_STATUS_INTERNAL_OFFSET, 884 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 885 amdgpu_ring_write(ring, 0x2); 886 } 887 888 void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 889 uint32_t val, uint32_t mask) 890 { 891 uint32_t reg_offset; 892 893 /* Use normalized offsets if required */ 894 if (jpeg_v4_0_3_normalizn_reqd(ring->adev)) 895 reg = NORMALIZE_JPEG_REG_OFFSET(reg); 896 897 reg_offset = (reg << 2); 898 899 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 900 0, 0, PACKETJ_TYPE0)); 901 amdgpu_ring_write(ring, 0x01400200); 902 903 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 904 0, 0, PACKETJ_TYPE0)); 905 amdgpu_ring_write(ring, val); 906 907 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 908 0, 0, PACKETJ_TYPE0)); 909 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 910 amdgpu_ring_write(ring, 0); 911 amdgpu_ring_write(ring, 912 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 913 } else { 914 amdgpu_ring_write(ring, reg_offset); 915 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 916 0, 0, PACKETJ_TYPE3)); 917 } 918 amdgpu_ring_write(ring, mask); 919 } 920 921 void jpeg_v4_0_3_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 922 unsigned int vmid, uint64_t pd_addr) 923 { 924 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 925 uint32_t data0, data1, mask; 926 927 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 928 929 /* wait for register write */ 930 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 931 data1 = lower_32_bits(pd_addr); 932 mask = 0xffffffff; 933 jpeg_v4_0_3_dec_ring_emit_reg_wait(ring, data0, data1, mask); 934 } 935 936 void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 937 { 938 uint32_t reg_offset; 939 940 /* Use normalized offsets if required */ 941 if (jpeg_v4_0_3_normalizn_reqd(ring->adev)) 942 reg = NORMALIZE_JPEG_REG_OFFSET(reg); 943 944 reg_offset = (reg << 2); 945 946 amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 947 0, 0, PACKETJ_TYPE0)); 948 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 949 amdgpu_ring_write(ring, 0); 950 amdgpu_ring_write(ring, 951 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 952 } else { 953 amdgpu_ring_write(ring, reg_offset); 954 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 955 0, 0, PACKETJ_TYPE0)); 956 } 957 amdgpu_ring_write(ring, val); 958 } 959 960 void jpeg_v4_0_3_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) 961 { 962 int i; 963 964 WARN_ON(ring->wptr % 2 || count % 2); 965 966 for (i = 0; i < count / 2; i++) { 967 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 968 amdgpu_ring_write(ring, 0); 969 } 970 } 971 972 static bool jpeg_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block) 973 { 974 struct amdgpu_device *adev = ip_block->adev; 975 bool ret = false; 976 int i, j; 977 978 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 979 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 980 ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i), 981 regUVD_JRBC0_UVD_JRBC_STATUS, jpeg_v4_0_3_core_reg_offset(j)) & 982 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 983 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 984 } 985 } 986 987 return ret; 988 } 989 990 static int jpeg_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 991 { 992 struct amdgpu_device *adev = ip_block->adev; 993 int ret = 0; 994 int i, j; 995 996 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 997 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 998 ret &= (SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i), 999 regUVD_JRBC0_UVD_JRBC_STATUS, jpeg_v4_0_3_core_reg_offset(j), 1000 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 1001 UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 1002 } 1003 } 1004 return ret; 1005 } 1006 1007 static int jpeg_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1008 enum amd_clockgating_state state) 1009 { 1010 struct amdgpu_device *adev = ip_block->adev; 1011 bool enable = state == AMD_CG_STATE_GATE; 1012 int i; 1013 1014 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1015 if (enable) { 1016 if (!jpeg_v4_0_3_is_idle(ip_block)) 1017 return -EBUSY; 1018 jpeg_v4_0_3_enable_clock_gating(adev, i); 1019 } else { 1020 jpeg_v4_0_3_disable_clock_gating(adev, i); 1021 } 1022 } 1023 return 0; 1024 } 1025 1026 static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 1027 enum amd_powergating_state state) 1028 { 1029 struct amdgpu_device *adev = ip_block->adev; 1030 int ret; 1031 1032 if (amdgpu_sriov_vf(adev)) { 1033 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; 1034 return 0; 1035 } 1036 1037 if (state == adev->jpeg.cur_state) 1038 return 0; 1039 1040 if (state == AMD_PG_STATE_GATE) 1041 ret = jpeg_v4_0_3_stop(adev); 1042 else 1043 ret = jpeg_v4_0_3_start(adev); 1044 1045 if (!ret) 1046 adev->jpeg.cur_state = state; 1047 1048 return ret; 1049 } 1050 1051 static int jpeg_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 1052 struct amdgpu_irq_src *source, 1053 unsigned int type, 1054 enum amdgpu_interrupt_state state) 1055 { 1056 return 0; 1057 } 1058 1059 static int jpeg_v4_0_3_set_ras_interrupt_state(struct amdgpu_device *adev, 1060 struct amdgpu_irq_src *source, 1061 unsigned int type, 1062 enum amdgpu_interrupt_state state) 1063 { 1064 return 0; 1065 } 1066 1067 static int jpeg_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1068 struct amdgpu_irq_src *source, 1069 struct amdgpu_iv_entry *entry) 1070 { 1071 uint32_t i, inst; 1072 1073 i = node_id_to_phys_map[entry->node_id]; 1074 DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n"); 1075 1076 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) 1077 if (adev->jpeg.inst[inst].aid_id == i) 1078 break; 1079 1080 if (inst >= adev->jpeg.num_jpeg_inst) { 1081 dev_WARN_ONCE(adev->dev, 1, 1082 "Interrupt received for unknown JPEG instance %d", 1083 entry->node_id); 1084 return 0; 1085 } 1086 1087 switch (entry->src_id) { 1088 case VCN_4_0__SRCID__JPEG_DECODE: 1089 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); 1090 break; 1091 case VCN_4_0__SRCID__JPEG1_DECODE: 1092 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]); 1093 break; 1094 case VCN_4_0__SRCID__JPEG2_DECODE: 1095 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]); 1096 break; 1097 case VCN_4_0__SRCID__JPEG3_DECODE: 1098 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]); 1099 break; 1100 case VCN_4_0__SRCID__JPEG4_DECODE: 1101 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]); 1102 break; 1103 case VCN_4_0__SRCID__JPEG5_DECODE: 1104 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]); 1105 break; 1106 case VCN_4_0__SRCID__JPEG6_DECODE: 1107 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]); 1108 break; 1109 case VCN_4_0__SRCID__JPEG7_DECODE: 1110 amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]); 1111 break; 1112 default: 1113 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1114 entry->src_id, entry->src_data[0]); 1115 break; 1116 } 1117 1118 return 0; 1119 } 1120 1121 static void jpeg_v4_0_3_core_stall_reset(struct amdgpu_ring *ring) 1122 { 1123 struct amdgpu_device *adev = ring->adev; 1124 int jpeg_inst = GET_INST(JPEG, ring->me); 1125 int reg_offset = jpeg_v4_0_3_core_reg_offset(ring->pipe); 1126 1127 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1128 regUVD_JMI0_UVD_JMI_CLIENT_STALL, 1129 reg_offset, 0x1F); 1130 SOC15_WAIT_ON_RREG_OFFSET(JPEG, jpeg_inst, 1131 regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS, 1132 reg_offset, 0x1F, 0x1F); 1133 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1134 regUVD_JMI0_JPEG_LMI_DROP, 1135 reg_offset, 0x1F); 1136 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 1 << ring->pipe); 1137 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1138 regUVD_JMI0_UVD_JMI_CLIENT_STALL, 1139 reg_offset, 0x00); 1140 WREG32_SOC15_OFFSET(JPEG, jpeg_inst, 1141 regUVD_JMI0_JPEG_LMI_DROP, 1142 reg_offset, 0x00); 1143 WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 0x00); 1144 } 1145 1146 static int jpeg_v4_0_3_ring_reset(struct amdgpu_ring *ring, unsigned int vmid) 1147 { 1148 if (amdgpu_sriov_vf(ring->adev)) 1149 return -EOPNOTSUPP; 1150 1151 jpeg_v4_0_3_core_stall_reset(ring); 1152 jpeg_v4_0_3_start_jrbc(ring); 1153 return amdgpu_ring_test_helper(ring); 1154 } 1155 1156 static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = { 1157 .name = "jpeg_v4_0_3", 1158 .early_init = jpeg_v4_0_3_early_init, 1159 .sw_init = jpeg_v4_0_3_sw_init, 1160 .sw_fini = jpeg_v4_0_3_sw_fini, 1161 .hw_init = jpeg_v4_0_3_hw_init, 1162 .hw_fini = jpeg_v4_0_3_hw_fini, 1163 .suspend = jpeg_v4_0_3_suspend, 1164 .resume = jpeg_v4_0_3_resume, 1165 .is_idle = jpeg_v4_0_3_is_idle, 1166 .wait_for_idle = jpeg_v4_0_3_wait_for_idle, 1167 .set_clockgating_state = jpeg_v4_0_3_set_clockgating_state, 1168 .set_powergating_state = jpeg_v4_0_3_set_powergating_state, 1169 .dump_ip_state = amdgpu_jpeg_dump_ip_state, 1170 .print_ip_state = amdgpu_jpeg_print_ip_state, 1171 }; 1172 1173 static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { 1174 .type = AMDGPU_RING_TYPE_VCN_JPEG, 1175 .align_mask = 0xf, 1176 .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr, 1177 .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr, 1178 .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr, 1179 .parse_cs = jpeg_v2_dec_ring_parse_cs, 1180 .emit_frame_size = 1181 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1182 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1183 8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */ 1184 18 + 18 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */ 1185 8 + 16, 1186 .emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */ 1187 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, 1188 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, 1189 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, 1190 .emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush, 1191 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 1192 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 1193 .insert_nop = jpeg_v4_0_3_dec_ring_nop, 1194 .insert_start = jpeg_v4_0_3_dec_ring_insert_start, 1195 .insert_end = jpeg_v4_0_3_dec_ring_insert_end, 1196 .pad_ib = amdgpu_ring_generic_pad_ib, 1197 .begin_use = amdgpu_jpeg_ring_begin_use, 1198 .end_use = amdgpu_jpeg_ring_end_use, 1199 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, 1200 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, 1201 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1202 .reset = jpeg_v4_0_3_ring_reset, 1203 }; 1204 1205 static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev) 1206 { 1207 int i, j, jpeg_inst; 1208 1209 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1210 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { 1211 adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v4_0_3_dec_ring_vm_funcs; 1212 adev->jpeg.inst[i].ring_dec[j].me = i; 1213 adev->jpeg.inst[i].ring_dec[j].pipe = j; 1214 } 1215 jpeg_inst = GET_INST(JPEG, i); 1216 adev->jpeg.inst[i].aid_id = 1217 jpeg_inst / adev->jpeg.num_inst_per_aid; 1218 } 1219 } 1220 1221 static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_irq_funcs = { 1222 .set = jpeg_v4_0_3_set_interrupt_state, 1223 .process = jpeg_v4_0_3_process_interrupt, 1224 }; 1225 1226 static const struct amdgpu_irq_src_funcs jpeg_v4_0_3_ras_irq_funcs = { 1227 .set = jpeg_v4_0_3_set_ras_interrupt_state, 1228 .process = amdgpu_jpeg_process_poison_irq, 1229 }; 1230 1231 static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1232 { 1233 int i; 1234 1235 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 1236 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; 1237 } 1238 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_3_irq_funcs; 1239 1240 adev->jpeg.inst->ras_poison_irq.num_types = 1; 1241 adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_3_ras_irq_funcs; 1242 } 1243 1244 const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block = { 1245 .type = AMD_IP_BLOCK_TYPE_JPEG, 1246 .major = 4, 1247 .minor = 0, 1248 .rev = 3, 1249 .funcs = &jpeg_v4_0_3_ip_funcs, 1250 }; 1251 1252 static const struct amdgpu_ras_err_status_reg_entry jpeg_v4_0_3_ue_reg_list[] = { 1253 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0S, regVCN_UE_ERR_STATUS_HI_JPEG0S), 1254 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0S"}, 1255 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG0D, regVCN_UE_ERR_STATUS_HI_JPEG0D), 1256 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG0D"}, 1257 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1S, regVCN_UE_ERR_STATUS_HI_JPEG1S), 1258 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1S"}, 1259 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG1D, regVCN_UE_ERR_STATUS_HI_JPEG1D), 1260 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG1D"}, 1261 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2S, regVCN_UE_ERR_STATUS_HI_JPEG2S), 1262 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2S"}, 1263 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG2D, regVCN_UE_ERR_STATUS_HI_JPEG2D), 1264 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG2D"}, 1265 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3S, regVCN_UE_ERR_STATUS_HI_JPEG3S), 1266 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3S"}, 1267 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG3D, regVCN_UE_ERR_STATUS_HI_JPEG3D), 1268 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG3D"}, 1269 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4S, regVCN_UE_ERR_STATUS_HI_JPEG4S), 1270 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4S"}, 1271 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG4D, regVCN_UE_ERR_STATUS_HI_JPEG4D), 1272 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG4D"}, 1273 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5S, regVCN_UE_ERR_STATUS_HI_JPEG5S), 1274 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5S"}, 1275 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG5D, regVCN_UE_ERR_STATUS_HI_JPEG5D), 1276 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG5D"}, 1277 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6S, regVCN_UE_ERR_STATUS_HI_JPEG6S), 1278 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6S"}, 1279 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG6D, regVCN_UE_ERR_STATUS_HI_JPEG6D), 1280 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG6D"}, 1281 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7S, regVCN_UE_ERR_STATUS_HI_JPEG7S), 1282 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7S"}, 1283 {AMDGPU_RAS_REG_ENTRY(JPEG, 0, regVCN_UE_ERR_STATUS_LO_JPEG7D, regVCN_UE_ERR_STATUS_HI_JPEG7D), 1284 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "JPEG7D"}, 1285 }; 1286 1287 static void jpeg_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1288 uint32_t jpeg_inst, 1289 void *ras_err_status) 1290 { 1291 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1292 1293 /* jpeg v4_0_3 only support uncorrectable errors */ 1294 amdgpu_ras_inst_query_ras_error_count(adev, 1295 jpeg_v4_0_3_ue_reg_list, 1296 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1297 NULL, 0, GET_INST(VCN, jpeg_inst), 1298 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1299 &err_data->ue_count); 1300 } 1301 1302 static void jpeg_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1303 void *ras_err_status) 1304 { 1305 uint32_t i; 1306 1307 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1308 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1309 return; 1310 } 1311 1312 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1313 jpeg_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1314 } 1315 1316 static void jpeg_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1317 uint32_t jpeg_inst) 1318 { 1319 amdgpu_ras_inst_reset_ras_error_count(adev, 1320 jpeg_v4_0_3_ue_reg_list, 1321 ARRAY_SIZE(jpeg_v4_0_3_ue_reg_list), 1322 GET_INST(VCN, jpeg_inst)); 1323 } 1324 1325 static void jpeg_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1326 { 1327 uint32_t i; 1328 1329 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) { 1330 dev_warn(adev->dev, "JPEG RAS is not supported\n"); 1331 return; 1332 } 1333 1334 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) 1335 jpeg_v4_0_3_inst_reset_ras_error_count(adev, i); 1336 } 1337 1338 static uint32_t jpeg_v4_0_3_query_poison_by_instance(struct amdgpu_device *adev, 1339 uint32_t instance, uint32_t sub_block) 1340 { 1341 uint32_t poison_stat = 0, reg_value = 0; 1342 1343 switch (sub_block) { 1344 case AMDGPU_JPEG_V4_0_3_JPEG0: 1345 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS); 1346 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF); 1347 break; 1348 case AMDGPU_JPEG_V4_0_3_JPEG1: 1349 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS); 1350 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF); 1351 break; 1352 default: 1353 break; 1354 } 1355 1356 if (poison_stat) 1357 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", 1358 instance, sub_block); 1359 1360 return poison_stat; 1361 } 1362 1363 static bool jpeg_v4_0_3_query_ras_poison_status(struct amdgpu_device *adev) 1364 { 1365 uint32_t inst = 0, sub = 0, poison_stat = 0; 1366 1367 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) 1368 for (sub = 0; sub < AMDGPU_JPEG_V4_0_3_MAX_SUB_BLOCK; sub++) 1369 poison_stat += 1370 jpeg_v4_0_3_query_poison_by_instance(adev, inst, sub); 1371 1372 return !!poison_stat; 1373 } 1374 1375 static const struct amdgpu_ras_block_hw_ops jpeg_v4_0_3_ras_hw_ops = { 1376 .query_ras_error_count = jpeg_v4_0_3_query_ras_error_count, 1377 .reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count, 1378 .query_poison_status = jpeg_v4_0_3_query_ras_poison_status, 1379 }; 1380 1381 static int jpeg_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 1382 enum aca_smu_type type, void *data) 1383 { 1384 struct aca_bank_info info; 1385 u64 misc0; 1386 int ret; 1387 1388 ret = aca_bank_info_decode(bank, &info); 1389 if (ret) 1390 return ret; 1391 1392 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 1393 switch (type) { 1394 case ACA_SMU_TYPE_UE: 1395 bank->aca_err_type = ACA_ERROR_TYPE_UE; 1396 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 1397 1ULL); 1398 break; 1399 case ACA_SMU_TYPE_CE: 1400 bank->aca_err_type = ACA_ERROR_TYPE_CE; 1401 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 1402 ACA_REG__MISC0__ERRCNT(misc0)); 1403 break; 1404 default: 1405 return -EINVAL; 1406 } 1407 1408 return ret; 1409 } 1410 1411 /* reference to smu driver if header file */ 1412 static int jpeg_v4_0_3_err_codes[] = { 1413 16, 17, 18, 19, 20, 21, 22, 23, /* JPEG[0-7][S|D] */ 1414 24, 25, 26, 27, 28, 29, 30, 31 1415 }; 1416 1417 static bool jpeg_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 1418 enum aca_smu_type type, void *data) 1419 { 1420 u32 instlo; 1421 1422 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 1423 instlo &= GENMASK(31, 1); 1424 1425 if (instlo != mmSMNAID_AID0_MCA_SMU) 1426 return false; 1427 1428 if (aca_bank_check_error_codes(handle->adev, bank, 1429 jpeg_v4_0_3_err_codes, 1430 ARRAY_SIZE(jpeg_v4_0_3_err_codes))) 1431 return false; 1432 1433 return true; 1434 } 1435 1436 static const struct aca_bank_ops jpeg_v4_0_3_aca_bank_ops = { 1437 .aca_bank_parser = jpeg_v4_0_3_aca_bank_parser, 1438 .aca_bank_is_valid = jpeg_v4_0_3_aca_bank_is_valid, 1439 }; 1440 1441 static const struct aca_info jpeg_v4_0_3_aca_info = { 1442 .hwip = ACA_HWIP_TYPE_SMU, 1443 .mask = ACA_ERROR_UE_MASK, 1444 .bank_ops = &jpeg_v4_0_3_aca_bank_ops, 1445 }; 1446 1447 static int jpeg_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 1448 { 1449 int r; 1450 1451 r = amdgpu_ras_block_late_init(adev, ras_block); 1452 if (r) 1453 return r; 1454 1455 if (amdgpu_ras_is_supported(adev, ras_block->block) && 1456 adev->jpeg.inst->ras_poison_irq.funcs) { 1457 r = amdgpu_irq_get(adev, &adev->jpeg.inst->ras_poison_irq, 0); 1458 if (r) 1459 goto late_fini; 1460 } 1461 1462 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__JPEG, 1463 &jpeg_v4_0_3_aca_info, NULL); 1464 if (r) 1465 goto late_fini; 1466 1467 return 0; 1468 1469 late_fini: 1470 amdgpu_ras_block_late_fini(adev, ras_block); 1471 1472 return r; 1473 } 1474 1475 static struct amdgpu_jpeg_ras jpeg_v4_0_3_ras = { 1476 .ras_block = { 1477 .hw_ops = &jpeg_v4_0_3_ras_hw_ops, 1478 .ras_late_init = jpeg_v4_0_3_ras_late_init, 1479 }, 1480 }; 1481 1482 static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 1483 { 1484 adev->jpeg.ras = &jpeg_v4_0_3_ras; 1485 } 1486