1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v2_0.h" 30 #include "jpeg_v4_0.h" 31 #include "mmsch_v4_0.h" 32 33 #include "vcn/vcn_4_0_0_offset.h" 34 #include "vcn/vcn_4_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 36 37 #define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 38 39 static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev); 40 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev); 41 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev); 42 static int jpeg_v4_0_set_powergating_state(void *handle, 43 enum amd_powergating_state state); 44 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev); 45 46 static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 47 48 /** 49 * jpeg_v4_0_early_init - set function pointers 50 * 51 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 52 * 53 * Set ring and irq function pointers 54 */ 55 static int jpeg_v4_0_early_init(struct amdgpu_ip_block *ip_block) 56 { 57 struct amdgpu_device *adev = ip_block->adev; 58 59 60 adev->jpeg.num_jpeg_inst = 1; 61 adev->jpeg.num_jpeg_rings = 1; 62 63 jpeg_v4_0_set_dec_ring_funcs(adev); 64 jpeg_v4_0_set_irq_funcs(adev); 65 jpeg_v4_0_set_ras_funcs(adev); 66 67 return 0; 68 } 69 70 /** 71 * jpeg_v4_0_sw_init - sw init for JPEG block 72 * 73 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 74 * 75 * Load firmware and sw initialization 76 */ 77 static int jpeg_v4_0_sw_init(struct amdgpu_ip_block *ip_block) 78 { 79 struct amdgpu_device *adev = ip_block->adev; 80 struct amdgpu_ring *ring; 81 int r; 82 83 /* JPEG TRAP */ 84 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 85 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 86 if (r) 87 return r; 88 89 /* JPEG DJPEG POISON EVENT */ 90 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 91 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); 92 if (r) 93 return r; 94 95 /* JPEG EJPEG POISON EVENT */ 96 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 97 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); 98 if (r) 99 return r; 100 101 r = amdgpu_jpeg_sw_init(adev); 102 if (r) 103 return r; 104 105 r = amdgpu_jpeg_resume(adev); 106 if (r) 107 return r; 108 109 ring = adev->jpeg.inst->ring_dec; 110 ring->use_doorbell = true; 111 ring->doorbell_index = amdgpu_sriov_vf(adev) ? (((adev->doorbell_index.vcn.vcn_ring0_1) << 1) + 4) : ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1); 112 ring->vm_hub = AMDGPU_MMHUB0(0); 113 114 sprintf(ring->name, "jpeg_dec"); 115 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 116 AMDGPU_RING_PRIO_DEFAULT, NULL); 117 if (r) 118 return r; 119 120 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; 121 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); 122 123 r = amdgpu_jpeg_ras_sw_init(adev); 124 if (r) 125 return r; 126 127 return 0; 128 } 129 130 /** 131 * jpeg_v4_0_sw_fini - sw fini for JPEG block 132 * 133 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 134 * 135 * JPEG suspend and free up sw allocation 136 */ 137 static int jpeg_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) 138 { 139 struct amdgpu_device *adev = ip_block->adev; 140 int r; 141 142 r = amdgpu_jpeg_suspend(adev); 143 if (r) 144 return r; 145 146 r = amdgpu_jpeg_sw_fini(adev); 147 148 return r; 149 } 150 151 /** 152 * jpeg_v4_0_hw_init - start and test JPEG block 153 * 154 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 155 * 156 */ 157 static int jpeg_v4_0_hw_init(struct amdgpu_ip_block *ip_block) 158 { 159 struct amdgpu_device *adev = ip_block->adev; 160 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 161 int r; 162 163 if (amdgpu_sriov_vf(adev)) { 164 r = jpeg_v4_0_start_sriov(adev); 165 if (r) 166 return r; 167 ring->wptr = 0; 168 ring->wptr_old = 0; 169 jpeg_v4_0_dec_ring_set_wptr(ring); 170 ring->sched.ready = true; 171 } else { 172 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 173 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 174 175 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL, 176 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 177 VCN_JPEG_DB_CTRL__EN_MASK); 178 179 r = amdgpu_ring_test_helper(ring); 180 if (r) 181 return r; 182 } 183 184 return 0; 185 } 186 187 /** 188 * jpeg_v4_0_hw_fini - stop the hardware block 189 * 190 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 191 * 192 * Stop the JPEG block, mark ring as not ready any more 193 */ 194 static int jpeg_v4_0_hw_fini(struct amdgpu_ip_block *ip_block) 195 { 196 struct amdgpu_device *adev = ip_block->adev; 197 198 cancel_delayed_work_sync(&adev->vcn.idle_work); 199 if (!amdgpu_sriov_vf(adev)) { 200 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 201 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS)) 202 jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 203 } 204 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) 205 amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0); 206 207 return 0; 208 } 209 210 /** 211 * jpeg_v4_0_suspend - suspend JPEG block 212 * 213 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 214 * 215 * HW fini and suspend JPEG block 216 */ 217 static int jpeg_v4_0_suspend(struct amdgpu_ip_block *ip_block) 218 { 219 int r; 220 221 r = jpeg_v4_0_hw_fini(ip_block); 222 if (r) 223 return r; 224 225 r = amdgpu_jpeg_suspend(ip_block->adev); 226 227 return r; 228 } 229 230 /** 231 * jpeg_v4_0_resume - resume JPEG block 232 * 233 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 234 * 235 * Resume firmware and hw init JPEG block 236 */ 237 static int jpeg_v4_0_resume(struct amdgpu_ip_block *ip_block) 238 { 239 int r; 240 241 r = amdgpu_jpeg_resume(ip_block->adev); 242 if (r) 243 return r; 244 245 r = jpeg_v4_0_hw_init(ip_block); 246 247 return r; 248 } 249 250 static void jpeg_v4_0_disable_clock_gating(struct amdgpu_device *adev) 251 { 252 uint32_t data = 0; 253 254 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 255 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 256 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 257 data &= (~JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK); 258 } else { 259 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 260 } 261 262 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 263 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 264 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 265 266 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 267 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 268 | JPEG_CGC_GATE__JPEG2_DEC_MASK 269 | JPEG_CGC_GATE__JMCIF_MASK 270 | JPEG_CGC_GATE__JRBBM_MASK); 271 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 272 } 273 274 static void jpeg_v4_0_enable_clock_gating(struct amdgpu_device *adev) 275 { 276 uint32_t data = 0; 277 278 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 279 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 280 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 281 data |= JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK; 282 } else { 283 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 284 } 285 286 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 287 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 288 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 289 290 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 291 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 292 |JPEG_CGC_GATE__JPEG2_DEC_MASK 293 |JPEG_CGC_GATE__JMCIF_MASK 294 |JPEG_CGC_GATE__JRBBM_MASK); 295 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 296 } 297 298 static int jpeg_v4_0_disable_static_power_gating(struct amdgpu_device *adev) 299 { 300 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 301 uint32_t data = 0; 302 int r = 0; 303 304 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 305 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data); 306 307 r = SOC15_WAIT_ON_RREG(JPEG, 0, 308 regUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 309 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 310 311 if (r) { 312 DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG disable power gating failed\n"); 313 return r; 314 } 315 } 316 317 /* disable anti hang mechanism */ 318 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 319 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 320 321 /* keep the JPEG in static PG mode */ 322 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 323 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); 324 325 return 0; 326 } 327 328 static int jpeg_v4_0_enable_static_power_gating(struct amdgpu_device *adev) 329 { 330 /* enable anti hang mechanism */ 331 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 332 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 333 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 334 335 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 336 uint32_t data = 0; 337 int r = 0; 338 339 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 340 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data); 341 342 r = SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS, 343 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 344 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 345 346 if (r) { 347 DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG enable power gating failed\n"); 348 return r; 349 } 350 } 351 352 return 0; 353 } 354 355 /** 356 * jpeg_v4_0_start - start JPEG block 357 * 358 * @adev: amdgpu_device pointer 359 * 360 * Setup and start the JPEG block 361 */ 362 static int jpeg_v4_0_start(struct amdgpu_device *adev) 363 { 364 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 365 int r; 366 367 if (adev->pm.dpm_enabled) 368 amdgpu_dpm_enable_jpeg(adev, true); 369 370 /* disable power gating */ 371 r = jpeg_v4_0_disable_static_power_gating(adev); 372 if (r) 373 return r; 374 375 /* JPEG disable CGC */ 376 jpeg_v4_0_disable_clock_gating(adev); 377 378 /* MJPEG global tiling registers */ 379 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, 380 adev->gfx.config.gb_addr_config); 381 382 383 /* enable JMI channel */ 384 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0, 385 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 386 387 /* enable System Interrupt for JRBC */ 388 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN), 389 JPEG_SYS_INT_EN__DJRBC_MASK, 390 ~JPEG_SYS_INT_EN__DJRBC_MASK); 391 392 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0); 393 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 394 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 395 lower_32_bits(ring->gpu_addr)); 396 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 397 upper_32_bits(ring->gpu_addr)); 398 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0); 399 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0); 400 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L); 401 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); 402 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 403 404 return 0; 405 } 406 407 static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev) 408 { 409 struct amdgpu_ring *ring; 410 uint64_t ctx_addr; 411 uint32_t param, resp, expected; 412 uint32_t tmp, timeout; 413 414 struct amdgpu_mm_table *table = &adev->virt.mm_table; 415 uint32_t *table_loc; 416 uint32_t table_size; 417 uint32_t size, size_dw; 418 uint32_t init_status; 419 420 struct mmsch_v4_0_cmd_direct_write 421 direct_wt = { {0} }; 422 struct mmsch_v4_0_cmd_end end = { {0} }; 423 struct mmsch_v4_0_init_header header; 424 425 direct_wt.cmd_header.command_type = 426 MMSCH_COMMAND__DIRECT_REG_WRITE; 427 end.cmd_header.command_type = 428 MMSCH_COMMAND__END; 429 430 size = sizeof(struct mmsch_v4_0_init_header); 431 table_loc = (uint32_t *)table->cpu_addr; 432 memcpy(&header, (void *)table_loc, size); 433 434 header.version = MMSCH_VERSION; 435 header.total_size = RREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE); 436 437 header.jpegdec.init_status = 0; 438 header.jpegdec.table_offset = 0; 439 header.jpegdec.table_size = 0; 440 441 table_loc = (uint32_t *)table->cpu_addr; 442 table_loc += header.total_size; 443 444 table_size = 0; 445 446 ring = adev->jpeg.inst->ring_dec; 447 448 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, 449 regUVD_LMI_JRBC_RB_64BIT_BAR_LOW), 450 lower_32_bits(ring->gpu_addr)); 451 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, 452 regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH), 453 upper_32_bits(ring->gpu_addr)); 454 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, 455 regUVD_JRBC_RB_SIZE), ring->ring_size / 4); 456 457 /* add end packet */ 458 MMSCH_V4_0_INSERT_END(); 459 460 /* refine header */ 461 header.jpegdec.init_status = 0; 462 header.jpegdec.table_offset = header.total_size; 463 header.jpegdec.table_size = table_size; 464 header.total_size += table_size; 465 466 /* Update init table header in memory */ 467 size = sizeof(struct mmsch_v4_0_init_header); 468 table_loc = (uint32_t *)table->cpu_addr; 469 memcpy((void *)table_loc, &header, size); 470 471 /* Perform HDP flush before writing to MMSCH registers */ 472 amdgpu_device_flush_hdp(adev, NULL); 473 474 /* message MMSCH (in VCN[0]) to initialize this client 475 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 476 * of memory descriptor location 477 */ 478 ctx_addr = table->gpu_addr; 479 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 480 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 481 482 /* 2, update vmid of descriptor */ 483 tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID); 484 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 485 /* use domain0 for MM scheduler */ 486 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 487 WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp); 488 489 /* 3, notify mmsch about the size of this descriptor */ 490 size = header.total_size; 491 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size); 492 493 /* 4, set resp to zero */ 494 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); 495 496 /* 5, kick off the initialization and wait until 497 * MMSCH_VF_MAILBOX_RESP becomes non-zero 498 */ 499 param = 0x00000001; 500 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param); 501 tmp = 0; 502 timeout = 1000; 503 resp = 0; 504 expected = MMSCH_VF_MAILBOX_RESP__OK; 505 init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->jpegdec.init_status; 506 while (resp != expected) { 507 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); 508 509 if (resp != 0) 510 break; 511 udelay(10); 512 tmp = tmp + 10; 513 if (tmp >= timeout) { 514 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 515 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 516 "(expected=0x%08x, readback=0x%08x)\n", 517 tmp, expected, resp); 518 return -EBUSY; 519 } 520 } 521 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 522 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) { 523 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", resp, init_status); 524 return -EINVAL; 525 } 526 527 return 0; 528 529 } 530 531 /** 532 * jpeg_v4_0_stop - stop JPEG block 533 * 534 * @adev: amdgpu_device pointer 535 * 536 * stop the JPEG block 537 */ 538 static int jpeg_v4_0_stop(struct amdgpu_device *adev) 539 { 540 int r; 541 542 /* reset JMI */ 543 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 544 UVD_JMI_CNTL__SOFT_RESET_MASK, 545 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 546 547 jpeg_v4_0_enable_clock_gating(adev); 548 549 /* enable power gating */ 550 r = jpeg_v4_0_enable_static_power_gating(adev); 551 if (r) 552 return r; 553 554 if (adev->pm.dpm_enabled) 555 amdgpu_dpm_enable_jpeg(adev, false); 556 557 return 0; 558 } 559 560 /** 561 * jpeg_v4_0_dec_ring_get_rptr - get read pointer 562 * 563 * @ring: amdgpu_ring pointer 564 * 565 * Returns the current hardware read pointer 566 */ 567 static uint64_t jpeg_v4_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 568 { 569 struct amdgpu_device *adev = ring->adev; 570 571 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR); 572 } 573 574 /** 575 * jpeg_v4_0_dec_ring_get_wptr - get write pointer 576 * 577 * @ring: amdgpu_ring pointer 578 * 579 * Returns the current hardware write pointer 580 */ 581 static uint64_t jpeg_v4_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 582 { 583 struct amdgpu_device *adev = ring->adev; 584 585 if (ring->use_doorbell) 586 return *ring->wptr_cpu_addr; 587 else 588 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 589 } 590 591 /** 592 * jpeg_v4_0_dec_ring_set_wptr - set write pointer 593 * 594 * @ring: amdgpu_ring pointer 595 * 596 * Commits the write pointer to the hardware 597 */ 598 static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 599 { 600 struct amdgpu_device *adev = ring->adev; 601 602 if (ring->use_doorbell) { 603 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 604 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 605 } else { 606 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 607 } 608 } 609 610 static bool jpeg_v4_0_is_idle(void *handle) 611 { 612 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 613 int ret = 1; 614 615 ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) & 616 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 617 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 618 619 return ret; 620 } 621 622 static int jpeg_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 623 { 624 struct amdgpu_device *adev = ip_block->adev; 625 626 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, 627 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 628 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 629 } 630 631 static int jpeg_v4_0_set_clockgating_state(void *handle, 632 enum amd_clockgating_state state) 633 { 634 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 635 bool enable = state == AMD_CG_STATE_GATE; 636 637 if (enable) { 638 if (!jpeg_v4_0_is_idle(handle)) 639 return -EBUSY; 640 jpeg_v4_0_enable_clock_gating(adev); 641 } else { 642 jpeg_v4_0_disable_clock_gating(adev); 643 } 644 645 return 0; 646 } 647 648 static int jpeg_v4_0_set_powergating_state(void *handle, 649 enum amd_powergating_state state) 650 { 651 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 652 int ret; 653 654 if (amdgpu_sriov_vf(adev)) { 655 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; 656 return 0; 657 } 658 659 if (state == adev->jpeg.cur_state) 660 return 0; 661 662 if (state == AMD_PG_STATE_GATE) 663 ret = jpeg_v4_0_stop(adev); 664 else 665 ret = jpeg_v4_0_start(adev); 666 667 if (!ret) 668 adev->jpeg.cur_state = state; 669 670 return ret; 671 } 672 673 static int jpeg_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev, 674 struct amdgpu_irq_src *source, 675 unsigned int type, 676 enum amdgpu_interrupt_state state) 677 { 678 return 0; 679 } 680 681 static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev, 682 struct amdgpu_irq_src *source, 683 struct amdgpu_iv_entry *entry) 684 { 685 DRM_DEBUG("IH: JPEG TRAP\n"); 686 687 switch (entry->src_id) { 688 case VCN_4_0__SRCID__JPEG_DECODE: 689 amdgpu_fence_process(adev->jpeg.inst->ring_dec); 690 break; 691 default: 692 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 693 entry->src_id, entry->src_data[0]); 694 break; 695 } 696 697 return 0; 698 } 699 700 static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = { 701 .name = "jpeg_v4_0", 702 .early_init = jpeg_v4_0_early_init, 703 .sw_init = jpeg_v4_0_sw_init, 704 .sw_fini = jpeg_v4_0_sw_fini, 705 .hw_init = jpeg_v4_0_hw_init, 706 .hw_fini = jpeg_v4_0_hw_fini, 707 .suspend = jpeg_v4_0_suspend, 708 .resume = jpeg_v4_0_resume, 709 .is_idle = jpeg_v4_0_is_idle, 710 .wait_for_idle = jpeg_v4_0_wait_for_idle, 711 .set_clockgating_state = jpeg_v4_0_set_clockgating_state, 712 .set_powergating_state = jpeg_v4_0_set_powergating_state, 713 }; 714 715 static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = { 716 .type = AMDGPU_RING_TYPE_VCN_JPEG, 717 .align_mask = 0xf, 718 .get_rptr = jpeg_v4_0_dec_ring_get_rptr, 719 .get_wptr = jpeg_v4_0_dec_ring_get_wptr, 720 .set_wptr = jpeg_v4_0_dec_ring_set_wptr, 721 .parse_cs = jpeg_v2_dec_ring_parse_cs, 722 .emit_frame_size = 723 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 724 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 725 8 + /* jpeg_v4_0_dec_ring_emit_vm_flush */ 726 18 + 18 + /* jpeg_v4_0_dec_ring_emit_fence x2 vm fence */ 727 8 + 16, 728 .emit_ib_size = 22, /* jpeg_v4_0_dec_ring_emit_ib */ 729 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 730 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 731 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 732 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 733 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 734 .insert_nop = jpeg_v2_0_dec_ring_nop, 735 .insert_start = jpeg_v2_0_dec_ring_insert_start, 736 .insert_end = jpeg_v2_0_dec_ring_insert_end, 737 .pad_ib = amdgpu_ring_generic_pad_ib, 738 .begin_use = amdgpu_jpeg_ring_begin_use, 739 .end_use = amdgpu_jpeg_ring_end_use, 740 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 741 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 742 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 743 }; 744 745 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev) 746 { 747 adev->jpeg.inst->ring_dec->funcs = &jpeg_v4_0_dec_ring_vm_funcs; 748 } 749 750 static const struct amdgpu_irq_src_funcs jpeg_v4_0_irq_funcs = { 751 .process = jpeg_v4_0_process_interrupt, 752 }; 753 754 static const struct amdgpu_irq_src_funcs jpeg_v4_0_ras_irq_funcs = { 755 .set = jpeg_v4_0_set_ras_interrupt_state, 756 .process = amdgpu_jpeg_process_poison_irq, 757 }; 758 759 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev) 760 { 761 adev->jpeg.inst->irq.num_types = 1; 762 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs; 763 764 adev->jpeg.inst->ras_poison_irq.num_types = 1; 765 adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_ras_irq_funcs; 766 } 767 768 const struct amdgpu_ip_block_version jpeg_v4_0_ip_block = { 769 .type = AMD_IP_BLOCK_TYPE_JPEG, 770 .major = 4, 771 .minor = 0, 772 .rev = 0, 773 .funcs = &jpeg_v4_0_ip_funcs, 774 }; 775 776 static uint32_t jpeg_v4_0_query_poison_by_instance(struct amdgpu_device *adev, 777 uint32_t instance, uint32_t sub_block) 778 { 779 uint32_t poison_stat = 0, reg_value = 0; 780 781 switch (sub_block) { 782 case AMDGPU_JPEG_V4_0_JPEG0: 783 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS); 784 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF); 785 break; 786 case AMDGPU_JPEG_V4_0_JPEG1: 787 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS); 788 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF); 789 break; 790 default: 791 break; 792 } 793 794 if (poison_stat) 795 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", 796 instance, sub_block); 797 798 return poison_stat; 799 } 800 801 static bool jpeg_v4_0_query_ras_poison_status(struct amdgpu_device *adev) 802 { 803 uint32_t inst = 0, sub = 0, poison_stat = 0; 804 805 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) 806 for (sub = 0; sub < AMDGPU_JPEG_V4_0_MAX_SUB_BLOCK; sub++) 807 poison_stat += 808 jpeg_v4_0_query_poison_by_instance(adev, inst, sub); 809 810 return !!poison_stat; 811 } 812 813 const struct amdgpu_ras_block_hw_ops jpeg_v4_0_ras_hw_ops = { 814 .query_poison_status = jpeg_v4_0_query_ras_poison_status, 815 }; 816 817 static struct amdgpu_jpeg_ras jpeg_v4_0_ras = { 818 .ras_block = { 819 .hw_ops = &jpeg_v4_0_ras_hw_ops, 820 .ras_late_init = amdgpu_jpeg_ras_late_init, 821 }, 822 }; 823 824 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev) 825 { 826 switch (amdgpu_ip_version(adev, JPEG_HWIP, 0)) { 827 case IP_VERSION(4, 0, 0): 828 adev->jpeg.ras = &jpeg_v4_0_ras; 829 break; 830 default: 831 break; 832 } 833 } 834