1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v2_0.h" 30 #include "jpeg_v4_0.h" 31 32 #include "vcn/vcn_4_0_0_offset.h" 33 #include "vcn/vcn_4_0_0_sh_mask.h" 34 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 35 36 #define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 37 38 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev); 39 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev); 40 static int jpeg_v4_0_set_powergating_state(void *handle, 41 enum amd_powergating_state state); 42 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev); 43 44 /** 45 * jpeg_v4_0_early_init - set function pointers 46 * 47 * @handle: amdgpu_device pointer 48 * 49 * Set ring and irq function pointers 50 */ 51 static int jpeg_v4_0_early_init(void *handle) 52 { 53 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 54 55 56 adev->jpeg.num_jpeg_inst = 1; 57 58 jpeg_v4_0_set_dec_ring_funcs(adev); 59 jpeg_v4_0_set_irq_funcs(adev); 60 jpeg_v4_0_set_ras_funcs(adev); 61 62 return 0; 63 } 64 65 /** 66 * jpeg_v4_0_sw_init - sw init for JPEG block 67 * 68 * @handle: amdgpu_device pointer 69 * 70 * Load firmware and sw initialization 71 */ 72 static int jpeg_v4_0_sw_init(void *handle) 73 { 74 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 75 struct amdgpu_ring *ring; 76 int r; 77 78 /* JPEG TRAP */ 79 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 80 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 81 if (r) 82 return r; 83 84 /* JPEG DJPEG POISON EVENT */ 85 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 86 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->irq); 87 if (r) 88 return r; 89 90 /* JPEG EJPEG POISON EVENT */ 91 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 92 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->irq); 93 if (r) 94 return r; 95 96 r = amdgpu_jpeg_sw_init(adev); 97 if (r) 98 return r; 99 100 r = amdgpu_jpeg_resume(adev); 101 if (r) 102 return r; 103 104 ring = &adev->jpeg.inst->ring_dec; 105 ring->use_doorbell = true; 106 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 107 sprintf(ring->name, "jpeg_dec"); 108 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 109 AMDGPU_RING_PRIO_DEFAULT, NULL); 110 if (r) 111 return r; 112 113 adev->jpeg.internal.jpeg_pitch = regUVD_JPEG_PITCH_INTERNAL_OFFSET; 114 adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); 115 116 return 0; 117 } 118 119 /** 120 * jpeg_v4_0_sw_fini - sw fini for JPEG block 121 * 122 * @handle: amdgpu_device pointer 123 * 124 * JPEG suspend and free up sw allocation 125 */ 126 static int jpeg_v4_0_sw_fini(void *handle) 127 { 128 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 129 int r; 130 131 r = amdgpu_jpeg_suspend(adev); 132 if (r) 133 return r; 134 135 r = amdgpu_jpeg_sw_fini(adev); 136 137 return r; 138 } 139 140 /** 141 * jpeg_v4_0_hw_init - start and test JPEG block 142 * 143 * @handle: amdgpu_device pointer 144 * 145 */ 146 static int jpeg_v4_0_hw_init(void *handle) 147 { 148 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 149 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 150 int r; 151 152 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 153 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 154 155 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL, 156 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 157 VCN_JPEG_DB_CTRL__EN_MASK); 158 159 r = amdgpu_ring_test_helper(ring); 160 if (r) 161 return r; 162 163 DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n"); 164 165 return 0; 166 } 167 168 /** 169 * jpeg_v4_0_hw_fini - stop the hardware block 170 * 171 * @handle: amdgpu_device pointer 172 * 173 * Stop the JPEG block, mark ring as not ready any more 174 */ 175 static int jpeg_v4_0_hw_fini(void *handle) 176 { 177 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 178 179 cancel_delayed_work_sync(&adev->vcn.idle_work); 180 181 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 182 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS)) 183 jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 184 185 amdgpu_irq_put(adev, &adev->jpeg.inst->irq, 0); 186 187 return 0; 188 } 189 190 /** 191 * jpeg_v4_0_suspend - suspend JPEG block 192 * 193 * @handle: amdgpu_device pointer 194 * 195 * HW fini and suspend JPEG block 196 */ 197 static int jpeg_v4_0_suspend(void *handle) 198 { 199 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 200 int r; 201 202 r = jpeg_v4_0_hw_fini(adev); 203 if (r) 204 return r; 205 206 r = amdgpu_jpeg_suspend(adev); 207 208 return r; 209 } 210 211 /** 212 * jpeg_v4_0_resume - resume JPEG block 213 * 214 * @handle: amdgpu_device pointer 215 * 216 * Resume firmware and hw init JPEG block 217 */ 218 static int jpeg_v4_0_resume(void *handle) 219 { 220 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 221 int r; 222 223 r = amdgpu_jpeg_resume(adev); 224 if (r) 225 return r; 226 227 r = jpeg_v4_0_hw_init(adev); 228 229 return r; 230 } 231 232 static void jpeg_v4_0_disable_clock_gating(struct amdgpu_device *adev) 233 { 234 uint32_t data = 0; 235 236 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 237 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 238 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 239 data &= (~JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK); 240 } else { 241 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 242 } 243 244 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 245 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 246 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 247 248 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 249 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 250 | JPEG_CGC_GATE__JPEG2_DEC_MASK 251 | JPEG_CGC_GATE__JMCIF_MASK 252 | JPEG_CGC_GATE__JRBBM_MASK); 253 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 254 } 255 256 static void jpeg_v4_0_enable_clock_gating(struct amdgpu_device *adev) 257 { 258 uint32_t data = 0; 259 260 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 261 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 262 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 263 data |= JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK; 264 } else { 265 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 266 } 267 268 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 269 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 270 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 271 272 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 273 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 274 |JPEG_CGC_GATE__JPEG2_DEC_MASK 275 |JPEG_CGC_GATE__JMCIF_MASK 276 |JPEG_CGC_GATE__JRBBM_MASK); 277 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 278 } 279 280 static int jpeg_v4_0_disable_static_power_gating(struct amdgpu_device *adev) 281 { 282 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 283 uint32_t data = 0; 284 int r = 0; 285 286 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 287 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data); 288 289 r = SOC15_WAIT_ON_RREG(JPEG, 0, 290 regUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 291 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 292 293 if (r) { 294 DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG disable power gating failed\n"); 295 return r; 296 } 297 } 298 299 /* disable anti hang mechanism */ 300 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 301 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 302 303 /* keep the JPEG in static PG mode */ 304 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 305 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); 306 307 return 0; 308 } 309 310 static int jpeg_v4_0_enable_static_power_gating(struct amdgpu_device *adev) 311 { 312 /* enable anti hang mechanism */ 313 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 314 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 315 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 316 317 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 318 uint32_t data = 0; 319 int r = 0; 320 321 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 322 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data); 323 324 r = SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS, 325 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 326 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 327 328 if (r) { 329 DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG enable power gating failed\n"); 330 return r; 331 } 332 } 333 334 return 0; 335 } 336 337 /** 338 * jpeg_v4_0_start - start JPEG block 339 * 340 * @adev: amdgpu_device pointer 341 * 342 * Setup and start the JPEG block 343 */ 344 static int jpeg_v4_0_start(struct amdgpu_device *adev) 345 { 346 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 347 int r; 348 349 if (adev->pm.dpm_enabled) 350 amdgpu_dpm_enable_jpeg(adev, true); 351 352 /* disable power gating */ 353 r = jpeg_v4_0_disable_static_power_gating(adev); 354 if (r) 355 return r; 356 357 /* JPEG disable CGC */ 358 jpeg_v4_0_disable_clock_gating(adev); 359 360 /* MJPEG global tiling registers */ 361 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, 362 adev->gfx.config.gb_addr_config); 363 364 365 /* enable JMI channel */ 366 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0, 367 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 368 369 /* enable System Interrupt for JRBC */ 370 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN), 371 JPEG_SYS_INT_EN__DJRBC_MASK, 372 ~JPEG_SYS_INT_EN__DJRBC_MASK); 373 374 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0); 375 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 376 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 377 lower_32_bits(ring->gpu_addr)); 378 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 379 upper_32_bits(ring->gpu_addr)); 380 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0); 381 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0); 382 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L); 383 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); 384 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 385 386 return 0; 387 } 388 389 /** 390 * jpeg_v4_0_stop - stop JPEG block 391 * 392 * @adev: amdgpu_device pointer 393 * 394 * stop the JPEG block 395 */ 396 static int jpeg_v4_0_stop(struct amdgpu_device *adev) 397 { 398 int r; 399 400 /* reset JMI */ 401 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 402 UVD_JMI_CNTL__SOFT_RESET_MASK, 403 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 404 405 jpeg_v4_0_enable_clock_gating(adev); 406 407 /* enable power gating */ 408 r = jpeg_v4_0_enable_static_power_gating(adev); 409 if (r) 410 return r; 411 412 if (adev->pm.dpm_enabled) 413 amdgpu_dpm_enable_jpeg(adev, false); 414 415 return 0; 416 } 417 418 /** 419 * jpeg_v4_0_dec_ring_get_rptr - get read pointer 420 * 421 * @ring: amdgpu_ring pointer 422 * 423 * Returns the current hardware read pointer 424 */ 425 static uint64_t jpeg_v4_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 426 { 427 struct amdgpu_device *adev = ring->adev; 428 429 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR); 430 } 431 432 /** 433 * jpeg_v4_0_dec_ring_get_wptr - get write pointer 434 * 435 * @ring: amdgpu_ring pointer 436 * 437 * Returns the current hardware write pointer 438 */ 439 static uint64_t jpeg_v4_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 440 { 441 struct amdgpu_device *adev = ring->adev; 442 443 if (ring->use_doorbell) 444 return *ring->wptr_cpu_addr; 445 else 446 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 447 } 448 449 /** 450 * jpeg_v4_0_dec_ring_set_wptr - set write pointer 451 * 452 * @ring: amdgpu_ring pointer 453 * 454 * Commits the write pointer to the hardware 455 */ 456 static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 457 { 458 struct amdgpu_device *adev = ring->adev; 459 460 if (ring->use_doorbell) { 461 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 462 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 463 } else { 464 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 465 } 466 } 467 468 static bool jpeg_v4_0_is_idle(void *handle) 469 { 470 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 471 int ret = 1; 472 473 ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) & 474 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 475 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 476 477 return ret; 478 } 479 480 static int jpeg_v4_0_wait_for_idle(void *handle) 481 { 482 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 483 484 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, 485 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 486 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 487 } 488 489 static int jpeg_v4_0_set_clockgating_state(void *handle, 490 enum amd_clockgating_state state) 491 { 492 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 493 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 494 495 if (enable) { 496 if (!jpeg_v4_0_is_idle(handle)) 497 return -EBUSY; 498 jpeg_v4_0_enable_clock_gating(adev); 499 } else { 500 jpeg_v4_0_disable_clock_gating(adev); 501 } 502 503 return 0; 504 } 505 506 static int jpeg_v4_0_set_powergating_state(void *handle, 507 enum amd_powergating_state state) 508 { 509 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 510 int ret; 511 512 if (state == adev->jpeg.cur_state) 513 return 0; 514 515 if (state == AMD_PG_STATE_GATE) 516 ret = jpeg_v4_0_stop(adev); 517 else 518 ret = jpeg_v4_0_start(adev); 519 520 if (!ret) 521 adev->jpeg.cur_state = state; 522 523 return ret; 524 } 525 526 static int jpeg_v4_0_set_interrupt_state(struct amdgpu_device *adev, 527 struct amdgpu_irq_src *source, 528 unsigned type, 529 enum amdgpu_interrupt_state state) 530 { 531 return 0; 532 } 533 534 static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev, 535 struct amdgpu_irq_src *source, 536 struct amdgpu_iv_entry *entry) 537 { 538 DRM_DEBUG("IH: JPEG TRAP\n"); 539 540 switch (entry->src_id) { 541 case VCN_4_0__SRCID__JPEG_DECODE: 542 amdgpu_fence_process(&adev->jpeg.inst->ring_dec); 543 break; 544 case VCN_4_0__SRCID_DJPEG0_POISON: 545 case VCN_4_0__SRCID_EJPEG0_POISON: 546 amdgpu_jpeg_process_poison_irq(adev, source, entry); 547 break; 548 default: 549 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 550 entry->src_id, entry->src_data[0]); 551 break; 552 } 553 554 return 0; 555 } 556 557 static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = { 558 .name = "jpeg_v4_0", 559 .early_init = jpeg_v4_0_early_init, 560 .late_init = NULL, 561 .sw_init = jpeg_v4_0_sw_init, 562 .sw_fini = jpeg_v4_0_sw_fini, 563 .hw_init = jpeg_v4_0_hw_init, 564 .hw_fini = jpeg_v4_0_hw_fini, 565 .suspend = jpeg_v4_0_suspend, 566 .resume = jpeg_v4_0_resume, 567 .is_idle = jpeg_v4_0_is_idle, 568 .wait_for_idle = jpeg_v4_0_wait_for_idle, 569 .check_soft_reset = NULL, 570 .pre_soft_reset = NULL, 571 .soft_reset = NULL, 572 .post_soft_reset = NULL, 573 .set_clockgating_state = jpeg_v4_0_set_clockgating_state, 574 .set_powergating_state = jpeg_v4_0_set_powergating_state, 575 }; 576 577 static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = { 578 .type = AMDGPU_RING_TYPE_VCN_JPEG, 579 .align_mask = 0xf, 580 .vmhub = AMDGPU_MMHUB_0, 581 .get_rptr = jpeg_v4_0_dec_ring_get_rptr, 582 .get_wptr = jpeg_v4_0_dec_ring_get_wptr, 583 .set_wptr = jpeg_v4_0_dec_ring_set_wptr, 584 .emit_frame_size = 585 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 586 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 587 8 + /* jpeg_v4_0_dec_ring_emit_vm_flush */ 588 18 + 18 + /* jpeg_v4_0_dec_ring_emit_fence x2 vm fence */ 589 8 + 16, 590 .emit_ib_size = 22, /* jpeg_v4_0_dec_ring_emit_ib */ 591 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 592 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 593 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 594 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 595 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 596 .insert_nop = jpeg_v2_0_dec_ring_nop, 597 .insert_start = jpeg_v2_0_dec_ring_insert_start, 598 .insert_end = jpeg_v2_0_dec_ring_insert_end, 599 .pad_ib = amdgpu_ring_generic_pad_ib, 600 .begin_use = amdgpu_jpeg_ring_begin_use, 601 .end_use = amdgpu_jpeg_ring_end_use, 602 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 603 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 604 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 605 }; 606 607 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev) 608 { 609 adev->jpeg.inst->ring_dec.funcs = &jpeg_v4_0_dec_ring_vm_funcs; 610 DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n"); 611 } 612 613 static const struct amdgpu_irq_src_funcs jpeg_v4_0_irq_funcs = { 614 .set = jpeg_v4_0_set_interrupt_state, 615 .process = jpeg_v4_0_process_interrupt, 616 }; 617 618 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev) 619 { 620 adev->jpeg.inst->irq.num_types = 1; 621 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs; 622 } 623 624 const struct amdgpu_ip_block_version jpeg_v4_0_ip_block = { 625 .type = AMD_IP_BLOCK_TYPE_JPEG, 626 .major = 4, 627 .minor = 0, 628 .rev = 0, 629 .funcs = &jpeg_v4_0_ip_funcs, 630 }; 631 632 static uint32_t jpeg_v4_0_query_poison_by_instance(struct amdgpu_device *adev, 633 uint32_t instance, uint32_t sub_block) 634 { 635 uint32_t poison_stat = 0, reg_value = 0; 636 637 switch (sub_block) { 638 case AMDGPU_JPEG_V4_0_JPEG0: 639 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS); 640 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF); 641 break; 642 case AMDGPU_JPEG_V4_0_JPEG1: 643 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS); 644 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF); 645 break; 646 default: 647 break; 648 } 649 650 if (poison_stat) 651 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", 652 instance, sub_block); 653 654 return poison_stat; 655 } 656 657 static bool jpeg_v4_0_query_ras_poison_status(struct amdgpu_device *adev) 658 { 659 uint32_t inst = 0, sub = 0, poison_stat = 0; 660 661 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) 662 for (sub = 0; sub < AMDGPU_JPEG_V4_0_MAX_SUB_BLOCK; sub++) 663 poison_stat += 664 jpeg_v4_0_query_poison_by_instance(adev, inst, sub); 665 666 return !!poison_stat; 667 } 668 669 const struct amdgpu_ras_block_hw_ops jpeg_v4_0_ras_hw_ops = { 670 .query_poison_status = jpeg_v4_0_query_ras_poison_status, 671 }; 672 673 static struct amdgpu_jpeg_ras jpeg_v4_0_ras = { 674 .ras_block = { 675 .hw_ops = &jpeg_v4_0_ras_hw_ops, 676 }, 677 }; 678 679 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev) 680 { 681 switch (adev->ip_versions[JPEG_HWIP][0]) { 682 case IP_VERSION(4, 0, 0): 683 adev->jpeg.ras = &jpeg_v4_0_ras; 684 break; 685 default: 686 break; 687 } 688 689 jpeg_set_ras_funcs(adev); 690 } 691