1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v2_0.h" 30 #include "jpeg_v4_0.h" 31 #include "mmsch_v4_0.h" 32 33 #include "vcn/vcn_4_0_0_offset.h" 34 #include "vcn/vcn_4_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 36 37 #define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 38 39 static const struct amdgpu_hwip_reg_entry jpeg_reg_list_4_0[] = { 40 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), 41 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), 42 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR), 43 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR), 44 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL), 45 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE), 46 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS), 47 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), 48 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), 49 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), 50 SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), 51 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), 52 SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), 53 }; 54 55 static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev); 56 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev); 57 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev); 58 static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 59 enum amd_powergating_state state); 60 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev); 61 static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 62 63 /** 64 * jpeg_v4_0_early_init - set function pointers 65 * 66 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 67 * 68 * Set ring and irq function pointers 69 */ 70 static int jpeg_v4_0_early_init(struct amdgpu_ip_block *ip_block) 71 { 72 struct amdgpu_device *adev = ip_block->adev; 73 74 75 adev->jpeg.num_jpeg_inst = 1; 76 adev->jpeg.num_jpeg_rings = 1; 77 78 jpeg_v4_0_set_dec_ring_funcs(adev); 79 jpeg_v4_0_set_irq_funcs(adev); 80 jpeg_v4_0_set_ras_funcs(adev); 81 82 return 0; 83 } 84 85 /** 86 * jpeg_v4_0_sw_init - sw init for JPEG block 87 * 88 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 89 * 90 * Load firmware and sw initialization 91 */ 92 static int jpeg_v4_0_sw_init(struct amdgpu_ip_block *ip_block) 93 { 94 struct amdgpu_device *adev = ip_block->adev; 95 struct amdgpu_ring *ring; 96 int r; 97 98 /* JPEG TRAP */ 99 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 100 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 101 if (r) 102 return r; 103 104 /* JPEG DJPEG POISON EVENT */ 105 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 106 VCN_4_0__SRCID_DJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); 107 if (r) 108 return r; 109 110 /* JPEG EJPEG POISON EVENT */ 111 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 112 VCN_4_0__SRCID_EJPEG0_POISON, &adev->jpeg.inst->ras_poison_irq); 113 if (r) 114 return r; 115 116 r = amdgpu_jpeg_sw_init(adev); 117 if (r) 118 return r; 119 120 r = amdgpu_jpeg_resume(adev); 121 if (r) 122 return r; 123 124 ring = adev->jpeg.inst->ring_dec; 125 ring->use_doorbell = true; 126 ring->doorbell_index = amdgpu_sriov_vf(adev) ? (((adev->doorbell_index.vcn.vcn_ring0_1) << 1) + 4) : ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1); 127 ring->vm_hub = AMDGPU_MMHUB0(0); 128 129 sprintf(ring->name, "jpeg_dec"); 130 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 131 AMDGPU_RING_PRIO_DEFAULT, NULL); 132 if (r) 133 return r; 134 135 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; 136 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); 137 138 r = amdgpu_jpeg_ras_sw_init(adev); 139 if (r) 140 return r; 141 142 r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_4_0, ARRAY_SIZE(jpeg_reg_list_4_0)); 143 if (r) 144 return r; 145 146 /* TODO: Add queue reset mask when FW fully supports it */ 147 adev->jpeg.supported_reset = 148 amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]); 149 r = amdgpu_jpeg_sysfs_reset_mask_init(adev); 150 if (r) 151 return r; 152 153 return 0; 154 } 155 156 /** 157 * jpeg_v4_0_sw_fini - sw fini for JPEG block 158 * 159 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 160 * 161 * JPEG suspend and free up sw allocation 162 */ 163 static int jpeg_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) 164 { 165 struct amdgpu_device *adev = ip_block->adev; 166 int r; 167 168 r = amdgpu_jpeg_suspend(adev); 169 if (r) 170 return r; 171 172 amdgpu_jpeg_sysfs_reset_mask_fini(adev); 173 r = amdgpu_jpeg_sw_fini(adev); 174 175 return r; 176 } 177 178 /** 179 * jpeg_v4_0_hw_init - start and test JPEG block 180 * 181 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 182 * 183 */ 184 static int jpeg_v4_0_hw_init(struct amdgpu_ip_block *ip_block) 185 { 186 struct amdgpu_device *adev = ip_block->adev; 187 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 188 int r; 189 190 if (amdgpu_sriov_vf(adev)) { 191 r = jpeg_v4_0_start_sriov(adev); 192 if (r) 193 return r; 194 ring->wptr = 0; 195 ring->wptr_old = 0; 196 jpeg_v4_0_dec_ring_set_wptr(ring); 197 ring->sched.ready = true; 198 } else { 199 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 200 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 201 202 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL, 203 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 204 VCN_JPEG_DB_CTRL__EN_MASK); 205 206 r = amdgpu_ring_test_helper(ring); 207 if (r) 208 return r; 209 } 210 211 return 0; 212 } 213 214 /** 215 * jpeg_v4_0_hw_fini - stop the hardware block 216 * 217 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 218 * 219 * Stop the JPEG block, mark ring as not ready any more 220 */ 221 static int jpeg_v4_0_hw_fini(struct amdgpu_ip_block *ip_block) 222 { 223 struct amdgpu_device *adev = ip_block->adev; 224 225 cancel_delayed_work_sync(&adev->jpeg.idle_work); 226 if (!amdgpu_sriov_vf(adev)) { 227 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 228 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS)) 229 jpeg_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 230 } 231 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) 232 amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0); 233 234 return 0; 235 } 236 237 /** 238 * jpeg_v4_0_suspend - suspend JPEG block 239 * 240 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 241 * 242 * HW fini and suspend JPEG block 243 */ 244 static int jpeg_v4_0_suspend(struct amdgpu_ip_block *ip_block) 245 { 246 int r; 247 248 r = jpeg_v4_0_hw_fini(ip_block); 249 if (r) 250 return r; 251 252 r = amdgpu_jpeg_suspend(ip_block->adev); 253 254 return r; 255 } 256 257 /** 258 * jpeg_v4_0_resume - resume JPEG block 259 * 260 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 261 * 262 * Resume firmware and hw init JPEG block 263 */ 264 static int jpeg_v4_0_resume(struct amdgpu_ip_block *ip_block) 265 { 266 int r; 267 268 r = amdgpu_jpeg_resume(ip_block->adev); 269 if (r) 270 return r; 271 272 r = jpeg_v4_0_hw_init(ip_block); 273 274 return r; 275 } 276 277 static void jpeg_v4_0_disable_clock_gating(struct amdgpu_device *adev) 278 { 279 uint32_t data = 0; 280 281 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 282 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 283 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 284 data &= (~JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK); 285 } else { 286 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 287 } 288 289 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 290 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 291 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 292 293 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 294 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 295 | JPEG_CGC_GATE__JPEG2_DEC_MASK 296 | JPEG_CGC_GATE__JMCIF_MASK 297 | JPEG_CGC_GATE__JRBBM_MASK); 298 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 299 } 300 301 static void jpeg_v4_0_enable_clock_gating(struct amdgpu_device *adev) 302 { 303 uint32_t data = 0; 304 305 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); 306 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) { 307 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 308 data |= JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK; 309 } else { 310 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 311 } 312 313 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 314 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 315 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); 316 317 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); 318 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 319 |JPEG_CGC_GATE__JPEG2_DEC_MASK 320 |JPEG_CGC_GATE__JMCIF_MASK 321 |JPEG_CGC_GATE__JRBBM_MASK); 322 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); 323 } 324 325 static int jpeg_v4_0_disable_static_power_gating(struct amdgpu_device *adev) 326 { 327 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 328 uint32_t data = 0; 329 int r = 0; 330 331 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 332 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data); 333 334 r = SOC15_WAIT_ON_RREG(JPEG, 0, 335 regUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 336 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 337 338 if (r) { 339 DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG disable power gating failed\n"); 340 return r; 341 } 342 } 343 344 /* disable anti hang mechanism */ 345 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 346 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 347 348 /* keep the JPEG in static PG mode */ 349 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, 350 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); 351 352 return 0; 353 } 354 355 static int jpeg_v4_0_enable_static_power_gating(struct amdgpu_device *adev) 356 { 357 /* enable anti hang mechanism */ 358 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 359 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 360 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 361 362 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 363 uint32_t data = 0; 364 int r = 0; 365 366 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 367 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_PGFSM_CONFIG), data); 368 369 r = SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS, 370 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 371 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 372 373 if (r) { 374 DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG enable power gating failed\n"); 375 return r; 376 } 377 } 378 379 return 0; 380 } 381 382 /** 383 * jpeg_v4_0_start - start JPEG block 384 * 385 * @adev: amdgpu_device pointer 386 * 387 * Setup and start the JPEG block 388 */ 389 static int jpeg_v4_0_start(struct amdgpu_device *adev) 390 { 391 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 392 int r; 393 394 if (adev->pm.dpm_enabled) 395 amdgpu_dpm_enable_jpeg(adev, true); 396 397 /* disable power gating */ 398 r = jpeg_v4_0_disable_static_power_gating(adev); 399 if (r) 400 return r; 401 402 /* JPEG disable CGC */ 403 jpeg_v4_0_disable_clock_gating(adev); 404 405 /* MJPEG global tiling registers */ 406 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, 407 adev->gfx.config.gb_addr_config); 408 409 410 /* enable JMI channel */ 411 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0, 412 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 413 414 /* enable System Interrupt for JRBC */ 415 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN), 416 JPEG_SYS_INT_EN__DJRBC_MASK, 417 ~JPEG_SYS_INT_EN__DJRBC_MASK); 418 419 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0); 420 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 421 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 422 lower_32_bits(ring->gpu_addr)); 423 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 424 upper_32_bits(ring->gpu_addr)); 425 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0); 426 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0); 427 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L); 428 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4); 429 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 430 431 return 0; 432 } 433 434 static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev) 435 { 436 struct amdgpu_ring *ring; 437 uint64_t ctx_addr; 438 uint32_t param, resp, expected; 439 uint32_t tmp, timeout; 440 441 struct amdgpu_mm_table *table = &adev->virt.mm_table; 442 uint32_t *table_loc; 443 uint32_t table_size; 444 uint32_t size, size_dw; 445 uint32_t init_status; 446 447 struct mmsch_v4_0_cmd_direct_write 448 direct_wt = { {0} }; 449 struct mmsch_v4_0_cmd_end end = { {0} }; 450 struct mmsch_v4_0_init_header header; 451 452 direct_wt.cmd_header.command_type = 453 MMSCH_COMMAND__DIRECT_REG_WRITE; 454 end.cmd_header.command_type = 455 MMSCH_COMMAND__END; 456 457 size = sizeof(struct mmsch_v4_0_init_header); 458 table_loc = (uint32_t *)table->cpu_addr; 459 memcpy(&header, (void *)table_loc, size); 460 461 header.version = MMSCH_VERSION; 462 header.total_size = RREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE); 463 464 header.jpegdec.init_status = 0; 465 header.jpegdec.table_offset = 0; 466 header.jpegdec.table_size = 0; 467 468 table_loc = (uint32_t *)table->cpu_addr; 469 table_loc += header.total_size; 470 471 table_size = 0; 472 473 ring = adev->jpeg.inst->ring_dec; 474 475 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, 476 regUVD_LMI_JRBC_RB_64BIT_BAR_LOW), 477 lower_32_bits(ring->gpu_addr)); 478 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, 479 regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH), 480 upper_32_bits(ring->gpu_addr)); 481 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(JPEG, 0, 482 regUVD_JRBC_RB_SIZE), ring->ring_size / 4); 483 484 /* add end packet */ 485 MMSCH_V4_0_INSERT_END(); 486 487 /* refine header */ 488 header.jpegdec.init_status = 0; 489 header.jpegdec.table_offset = header.total_size; 490 header.jpegdec.table_size = table_size; 491 header.total_size += table_size; 492 493 /* Update init table header in memory */ 494 size = sizeof(struct mmsch_v4_0_init_header); 495 table_loc = (uint32_t *)table->cpu_addr; 496 memcpy((void *)table_loc, &header, size); 497 498 /* Perform HDP flush before writing to MMSCH registers */ 499 amdgpu_device_flush_hdp(adev, NULL); 500 501 /* message MMSCH (in VCN[0]) to initialize this client 502 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 503 * of memory descriptor location 504 */ 505 ctx_addr = table->gpu_addr; 506 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 507 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 508 509 /* 2, update vmid of descriptor */ 510 tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID); 511 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 512 /* use domain0 for MM scheduler */ 513 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 514 WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp); 515 516 /* 3, notify mmsch about the size of this descriptor */ 517 size = header.total_size; 518 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size); 519 520 /* 4, set resp to zero */ 521 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); 522 523 /* 5, kick off the initialization and wait until 524 * MMSCH_VF_MAILBOX_RESP becomes non-zero 525 */ 526 param = 0x00000001; 527 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param); 528 tmp = 0; 529 timeout = 1000; 530 resp = 0; 531 expected = MMSCH_VF_MAILBOX_RESP__OK; 532 init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->jpegdec.init_status; 533 while (resp != expected) { 534 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); 535 536 if (resp != 0) 537 break; 538 udelay(10); 539 tmp = tmp + 10; 540 if (tmp >= timeout) { 541 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 542 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 543 "(expected=0x%08x, readback=0x%08x)\n", 544 tmp, expected, resp); 545 return -EBUSY; 546 } 547 } 548 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 549 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) { 550 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init status for jpeg: %x\n", resp, init_status); 551 return -EINVAL; 552 } 553 554 return 0; 555 556 } 557 558 /** 559 * jpeg_v4_0_stop - stop JPEG block 560 * 561 * @adev: amdgpu_device pointer 562 * 563 * stop the JPEG block 564 */ 565 static int jpeg_v4_0_stop(struct amdgpu_device *adev) 566 { 567 int r; 568 569 /* reset JMI */ 570 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 571 UVD_JMI_CNTL__SOFT_RESET_MASK, 572 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 573 574 jpeg_v4_0_enable_clock_gating(adev); 575 576 /* enable power gating */ 577 r = jpeg_v4_0_enable_static_power_gating(adev); 578 if (r) 579 return r; 580 581 if (adev->pm.dpm_enabled) 582 amdgpu_dpm_enable_jpeg(adev, false); 583 584 return 0; 585 } 586 587 /** 588 * jpeg_v4_0_dec_ring_get_rptr - get read pointer 589 * 590 * @ring: amdgpu_ring pointer 591 * 592 * Returns the current hardware read pointer 593 */ 594 static uint64_t jpeg_v4_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 595 { 596 struct amdgpu_device *adev = ring->adev; 597 598 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR); 599 } 600 601 /** 602 * jpeg_v4_0_dec_ring_get_wptr - get write pointer 603 * 604 * @ring: amdgpu_ring pointer 605 * 606 * Returns the current hardware write pointer 607 */ 608 static uint64_t jpeg_v4_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 609 { 610 struct amdgpu_device *adev = ring->adev; 611 612 if (ring->use_doorbell) 613 return *ring->wptr_cpu_addr; 614 else 615 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR); 616 } 617 618 /** 619 * jpeg_v4_0_dec_ring_set_wptr - set write pointer 620 * 621 * @ring: amdgpu_ring pointer 622 * 623 * Commits the write pointer to the hardware 624 */ 625 static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 626 { 627 struct amdgpu_device *adev = ring->adev; 628 629 if (ring->use_doorbell) { 630 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 631 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 632 } else { 633 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 634 } 635 } 636 637 static bool jpeg_v4_0_is_idle(void *handle) 638 { 639 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 640 int ret = 1; 641 642 ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) & 643 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 644 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 645 646 return ret; 647 } 648 649 static int jpeg_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 650 { 651 struct amdgpu_device *adev = ip_block->adev; 652 653 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, 654 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 655 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 656 } 657 658 static int jpeg_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 659 enum amd_clockgating_state state) 660 { 661 struct amdgpu_device *adev = ip_block->adev; 662 bool enable = state == AMD_CG_STATE_GATE; 663 664 if (enable) { 665 if (!jpeg_v4_0_is_idle(adev)) 666 return -EBUSY; 667 jpeg_v4_0_enable_clock_gating(adev); 668 } else { 669 jpeg_v4_0_disable_clock_gating(adev); 670 } 671 672 return 0; 673 } 674 675 static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 676 enum amd_powergating_state state) 677 { 678 struct amdgpu_device *adev = ip_block->adev; 679 int ret; 680 681 if (amdgpu_sriov_vf(adev)) { 682 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; 683 return 0; 684 } 685 686 if (state == adev->jpeg.cur_state) 687 return 0; 688 689 if (state == AMD_PG_STATE_GATE) 690 ret = jpeg_v4_0_stop(adev); 691 else 692 ret = jpeg_v4_0_start(adev); 693 694 if (!ret) 695 adev->jpeg.cur_state = state; 696 697 return ret; 698 } 699 700 static int jpeg_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev, 701 struct amdgpu_irq_src *source, 702 unsigned int type, 703 enum amdgpu_interrupt_state state) 704 { 705 return 0; 706 } 707 708 static int jpeg_v4_0_process_interrupt(struct amdgpu_device *adev, 709 struct amdgpu_irq_src *source, 710 struct amdgpu_iv_entry *entry) 711 { 712 DRM_DEBUG("IH: JPEG TRAP\n"); 713 714 switch (entry->src_id) { 715 case VCN_4_0__SRCID__JPEG_DECODE: 716 amdgpu_fence_process(adev->jpeg.inst->ring_dec); 717 break; 718 default: 719 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 720 entry->src_id, entry->src_data[0]); 721 break; 722 } 723 724 return 0; 725 } 726 727 static const struct amd_ip_funcs jpeg_v4_0_ip_funcs = { 728 .name = "jpeg_v4_0", 729 .early_init = jpeg_v4_0_early_init, 730 .sw_init = jpeg_v4_0_sw_init, 731 .sw_fini = jpeg_v4_0_sw_fini, 732 .hw_init = jpeg_v4_0_hw_init, 733 .hw_fini = jpeg_v4_0_hw_fini, 734 .suspend = jpeg_v4_0_suspend, 735 .resume = jpeg_v4_0_resume, 736 .is_idle = jpeg_v4_0_is_idle, 737 .wait_for_idle = jpeg_v4_0_wait_for_idle, 738 .set_clockgating_state = jpeg_v4_0_set_clockgating_state, 739 .set_powergating_state = jpeg_v4_0_set_powergating_state, 740 .dump_ip_state = amdgpu_jpeg_dump_ip_state, 741 .print_ip_state = amdgpu_jpeg_print_ip_state, 742 }; 743 744 static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = { 745 .type = AMDGPU_RING_TYPE_VCN_JPEG, 746 .align_mask = 0xf, 747 .get_rptr = jpeg_v4_0_dec_ring_get_rptr, 748 .get_wptr = jpeg_v4_0_dec_ring_get_wptr, 749 .set_wptr = jpeg_v4_0_dec_ring_set_wptr, 750 .parse_cs = jpeg_v2_dec_ring_parse_cs, 751 .emit_frame_size = 752 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 753 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 754 8 + /* jpeg_v4_0_dec_ring_emit_vm_flush */ 755 18 + 18 + /* jpeg_v4_0_dec_ring_emit_fence x2 vm fence */ 756 8 + 16, 757 .emit_ib_size = 22, /* jpeg_v4_0_dec_ring_emit_ib */ 758 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 759 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 760 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 761 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 762 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 763 .insert_nop = jpeg_v2_0_dec_ring_nop, 764 .insert_start = jpeg_v2_0_dec_ring_insert_start, 765 .insert_end = jpeg_v2_0_dec_ring_insert_end, 766 .pad_ib = amdgpu_ring_generic_pad_ib, 767 .begin_use = amdgpu_jpeg_ring_begin_use, 768 .end_use = amdgpu_jpeg_ring_end_use, 769 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 770 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 771 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 772 }; 773 774 static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev) 775 { 776 adev->jpeg.inst->ring_dec->funcs = &jpeg_v4_0_dec_ring_vm_funcs; 777 } 778 779 static const struct amdgpu_irq_src_funcs jpeg_v4_0_irq_funcs = { 780 .process = jpeg_v4_0_process_interrupt, 781 }; 782 783 static const struct amdgpu_irq_src_funcs jpeg_v4_0_ras_irq_funcs = { 784 .set = jpeg_v4_0_set_ras_interrupt_state, 785 .process = amdgpu_jpeg_process_poison_irq, 786 }; 787 788 static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev) 789 { 790 adev->jpeg.inst->irq.num_types = 1; 791 adev->jpeg.inst->irq.funcs = &jpeg_v4_0_irq_funcs; 792 793 adev->jpeg.inst->ras_poison_irq.num_types = 1; 794 adev->jpeg.inst->ras_poison_irq.funcs = &jpeg_v4_0_ras_irq_funcs; 795 } 796 797 const struct amdgpu_ip_block_version jpeg_v4_0_ip_block = { 798 .type = AMD_IP_BLOCK_TYPE_JPEG, 799 .major = 4, 800 .minor = 0, 801 .rev = 0, 802 .funcs = &jpeg_v4_0_ip_funcs, 803 }; 804 805 static uint32_t jpeg_v4_0_query_poison_by_instance(struct amdgpu_device *adev, 806 uint32_t instance, uint32_t sub_block) 807 { 808 uint32_t poison_stat = 0, reg_value = 0; 809 810 switch (sub_block) { 811 case AMDGPU_JPEG_V4_0_JPEG0: 812 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG0_STATUS); 813 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF); 814 break; 815 case AMDGPU_JPEG_V4_0_JPEG1: 816 reg_value = RREG32_SOC15(JPEG, instance, regUVD_RAS_JPEG1_STATUS); 817 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF); 818 break; 819 default: 820 break; 821 } 822 823 if (poison_stat) 824 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", 825 instance, sub_block); 826 827 return poison_stat; 828 } 829 830 static bool jpeg_v4_0_query_ras_poison_status(struct amdgpu_device *adev) 831 { 832 uint32_t inst = 0, sub = 0, poison_stat = 0; 833 834 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) 835 for (sub = 0; sub < AMDGPU_JPEG_V4_0_MAX_SUB_BLOCK; sub++) 836 poison_stat += 837 jpeg_v4_0_query_poison_by_instance(adev, inst, sub); 838 839 return !!poison_stat; 840 } 841 842 const struct amdgpu_ras_block_hw_ops jpeg_v4_0_ras_hw_ops = { 843 .query_poison_status = jpeg_v4_0_query_ras_poison_status, 844 }; 845 846 static struct amdgpu_jpeg_ras jpeg_v4_0_ras = { 847 .ras_block = { 848 .hw_ops = &jpeg_v4_0_ras_hw_ops, 849 .ras_late_init = amdgpu_jpeg_ras_late_init, 850 }, 851 }; 852 853 static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev) 854 { 855 switch (amdgpu_ip_version(adev, JPEG_HWIP, 0)) { 856 case IP_VERSION(4, 0, 0): 857 adev->jpeg.ras = &jpeg_v4_0_ras; 858 break; 859 default: 860 break; 861 } 862 } 863