1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v2_0.h" 30 31 #include "vcn/vcn_3_0_0_offset.h" 32 #include "vcn/vcn_3_0_0_sh_mask.h" 33 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 34 35 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 36 37 static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 38 static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev); 39 static int jpeg_v3_0_set_powergating_state(void *handle, 40 enum amd_powergating_state state); 41 42 /** 43 * jpeg_v3_0_early_init - set function pointers 44 * 45 * @handle: amdgpu_device pointer 46 * 47 * Set ring and irq function pointers 48 */ 49 static int jpeg_v3_0_early_init(void *handle) 50 { 51 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 52 if (adev->asic_type == CHIP_SIENNA_CICHLID) { 53 u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING); 54 55 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 56 return -ENOENT; 57 } 58 adev->jpeg.num_jpeg_inst = 1; 59 60 jpeg_v3_0_set_dec_ring_funcs(adev); 61 jpeg_v3_0_set_irq_funcs(adev); 62 63 return 0; 64 } 65 66 /** 67 * jpeg_v3_0_sw_init - sw init for JPEG block 68 * 69 * @handle: amdgpu_device pointer 70 * 71 * Load firmware and sw initialization 72 */ 73 static int jpeg_v3_0_sw_init(void *handle) 74 { 75 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 76 struct amdgpu_ring *ring; 77 int r; 78 79 /* JPEG TRAP */ 80 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 81 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 82 if (r) 83 return r; 84 85 r = amdgpu_jpeg_sw_init(adev); 86 if (r) 87 return r; 88 89 r = amdgpu_jpeg_resume(adev); 90 if (r) 91 return r; 92 93 ring = &adev->jpeg.inst->ring_dec; 94 ring->use_doorbell = true; 95 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 96 sprintf(ring->name, "jpeg_dec"); 97 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 98 AMDGPU_RING_PRIO_DEFAULT); 99 if (r) 100 return r; 101 102 adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 103 adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); 104 105 return 0; 106 } 107 108 /** 109 * jpeg_v3_0_sw_fini - sw fini for JPEG block 110 * 111 * @handle: amdgpu_device pointer 112 * 113 * JPEG suspend and free up sw allocation 114 */ 115 static int jpeg_v3_0_sw_fini(void *handle) 116 { 117 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 118 int r; 119 120 r = amdgpu_jpeg_suspend(adev); 121 if (r) 122 return r; 123 124 r = amdgpu_jpeg_sw_fini(adev); 125 126 return r; 127 } 128 129 /** 130 * jpeg_v3_0_hw_init - start and test JPEG block 131 * 132 * @handle: amdgpu_device pointer 133 * 134 */ 135 static int jpeg_v3_0_hw_init(void *handle) 136 { 137 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 138 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 139 int r; 140 141 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 142 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 143 144 r = amdgpu_ring_test_helper(ring); 145 if (r) 146 return r; 147 148 DRM_INFO("JPEG decode initialized successfully.\n"); 149 150 return 0; 151 } 152 153 /** 154 * jpeg_v3_0_hw_fini - stop the hardware block 155 * 156 * @handle: amdgpu_device pointer 157 * 158 * Stop the JPEG block, mark ring as not ready any more 159 */ 160 static int jpeg_v3_0_hw_fini(void *handle) 161 { 162 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 163 struct amdgpu_ring *ring; 164 165 ring = &adev->jpeg.inst->ring_dec; 166 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 167 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS)) 168 jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 169 170 ring->sched.ready = false; 171 172 return 0; 173 } 174 175 /** 176 * jpeg_v3_0_suspend - suspend JPEG block 177 * 178 * @handle: amdgpu_device pointer 179 * 180 * HW fini and suspend JPEG block 181 */ 182 static int jpeg_v3_0_suspend(void *handle) 183 { 184 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 185 int r; 186 187 r = jpeg_v3_0_hw_fini(adev); 188 if (r) 189 return r; 190 191 r = amdgpu_jpeg_suspend(adev); 192 193 return r; 194 } 195 196 /** 197 * jpeg_v3_0_resume - resume JPEG block 198 * 199 * @handle: amdgpu_device pointer 200 * 201 * Resume firmware and hw init JPEG block 202 */ 203 static int jpeg_v3_0_resume(void *handle) 204 { 205 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 206 int r; 207 208 r = amdgpu_jpeg_resume(adev); 209 if (r) 210 return r; 211 212 r = jpeg_v3_0_hw_init(adev); 213 214 return r; 215 } 216 217 static void jpeg_v3_0_disable_clock_gating(struct amdgpu_device* adev) 218 { 219 uint32_t data = 0; 220 221 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 222 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 223 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 224 else 225 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 226 227 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 228 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 229 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 230 231 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 232 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 233 | JPEG_CGC_GATE__JPEG2_DEC_MASK 234 | JPEG_CGC_GATE__JPEG_ENC_MASK 235 | JPEG_CGC_GATE__JMCIF_MASK 236 | JPEG_CGC_GATE__JRBBM_MASK); 237 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 238 239 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 240 data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 241 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 242 | JPEG_CGC_CTRL__JMCIF_MODE_MASK 243 | JPEG_CGC_CTRL__JRBBM_MODE_MASK); 244 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 245 } 246 247 static void jpeg_v3_0_enable_clock_gating(struct amdgpu_device* adev) 248 { 249 uint32_t data = 0; 250 251 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 252 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 253 |JPEG_CGC_GATE__JPEG2_DEC_MASK 254 |JPEG_CGC_GATE__JPEG_ENC_MASK 255 |JPEG_CGC_GATE__JMCIF_MASK 256 |JPEG_CGC_GATE__JRBBM_MASK); 257 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 258 } 259 260 static int jpeg_v3_0_disable_static_power_gating(struct amdgpu_device *adev) 261 { 262 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 263 uint32_t data = 0; 264 int r = 0; 265 266 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 267 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 268 269 r = SOC15_WAIT_ON_RREG(JPEG, 0, 270 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 271 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 272 273 if (r) { 274 DRM_ERROR("amdgpu: JPEG disable power gating failed\n"); 275 return r; 276 } 277 } 278 279 /* disable anti hang mechanism */ 280 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0, 281 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 282 283 /* keep the JPEG in static PG mode */ 284 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0, 285 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); 286 287 return 0; 288 } 289 290 static int jpeg_v3_0_enable_static_power_gating(struct amdgpu_device* adev) 291 { 292 /* enable anti hang mechanism */ 293 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 294 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 295 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 296 297 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 298 uint32_t data = 0; 299 int r = 0; 300 301 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 302 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 303 304 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, 305 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 306 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 307 308 if (r) { 309 DRM_ERROR("amdgpu: JPEG enable power gating failed\n"); 310 return r; 311 } 312 } 313 314 return 0; 315 } 316 317 /** 318 * jpeg_v3_0_start - start JPEG block 319 * 320 * @adev: amdgpu_device pointer 321 * 322 * Setup and start the JPEG block 323 */ 324 static int jpeg_v3_0_start(struct amdgpu_device *adev) 325 { 326 struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec; 327 int r; 328 329 if (adev->pm.dpm_enabled) 330 amdgpu_dpm_enable_jpeg(adev, true); 331 332 /* disable power gating */ 333 r = jpeg_v3_0_disable_static_power_gating(adev); 334 if (r) 335 return r; 336 337 /* JPEG disable CGC */ 338 jpeg_v3_0_disable_clock_gating(adev); 339 340 /* MJPEG global tiling registers */ 341 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, 342 adev->gfx.config.gb_addr_config); 343 WREG32_SOC15(JPEG, 0, mmJPEG_ENC_GFX10_ADDR_CONFIG, 344 adev->gfx.config.gb_addr_config); 345 346 /* enable JMI channel */ 347 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0, 348 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 349 350 /* enable System Interrupt for JRBC */ 351 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN), 352 JPEG_SYS_INT_EN__DJRBC_MASK, 353 ~JPEG_SYS_INT_EN__DJRBC_MASK); 354 355 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 356 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 357 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 358 lower_32_bits(ring->gpu_addr)); 359 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 360 upper_32_bits(ring->gpu_addr)); 361 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); 362 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); 363 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); 364 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); 365 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 366 367 return 0; 368 } 369 370 /** 371 * jpeg_v3_0_stop - stop JPEG block 372 * 373 * @adev: amdgpu_device pointer 374 * 375 * stop the JPEG block 376 */ 377 static int jpeg_v3_0_stop(struct amdgpu_device *adev) 378 { 379 int r; 380 381 /* reset JMI */ 382 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 383 UVD_JMI_CNTL__SOFT_RESET_MASK, 384 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 385 386 jpeg_v3_0_enable_clock_gating(adev); 387 388 /* enable power gating */ 389 r = jpeg_v3_0_enable_static_power_gating(adev); 390 if (r) 391 return r; 392 393 if (adev->pm.dpm_enabled) 394 amdgpu_dpm_enable_jpeg(adev, false); 395 396 return 0; 397 } 398 399 /** 400 * jpeg_v3_0_dec_ring_get_rptr - get read pointer 401 * 402 * @ring: amdgpu_ring pointer 403 * 404 * Returns the current hardware read pointer 405 */ 406 static uint64_t jpeg_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 407 { 408 struct amdgpu_device *adev = ring->adev; 409 410 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); 411 } 412 413 /** 414 * jpeg_v3_0_dec_ring_get_wptr - get write pointer 415 * 416 * @ring: amdgpu_ring pointer 417 * 418 * Returns the current hardware write pointer 419 */ 420 static uint64_t jpeg_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 421 { 422 struct amdgpu_device *adev = ring->adev; 423 424 if (ring->use_doorbell) 425 return adev->wb.wb[ring->wptr_offs]; 426 else 427 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 428 } 429 430 /** 431 * jpeg_v3_0_dec_ring_set_wptr - set write pointer 432 * 433 * @ring: amdgpu_ring pointer 434 * 435 * Commits the write pointer to the hardware 436 */ 437 static void jpeg_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 438 { 439 struct amdgpu_device *adev = ring->adev; 440 441 if (ring->use_doorbell) { 442 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 443 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 444 } else { 445 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 446 } 447 } 448 449 static bool jpeg_v3_0_is_idle(void *handle) 450 { 451 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 452 int ret = 1; 453 454 ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) & 455 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 456 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 457 458 return ret; 459 } 460 461 static int jpeg_v3_0_wait_for_idle(void *handle) 462 { 463 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 464 int ret; 465 466 ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, 467 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 468 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 469 if (ret) 470 return ret; 471 472 return ret; 473 } 474 475 static int jpeg_v3_0_set_clockgating_state(void *handle, 476 enum amd_clockgating_state state) 477 { 478 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 479 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 480 481 if (enable) { 482 if (!jpeg_v3_0_is_idle(handle)) 483 return -EBUSY; 484 jpeg_v3_0_enable_clock_gating(adev); 485 } else { 486 jpeg_v3_0_disable_clock_gating(adev); 487 } 488 489 return 0; 490 } 491 492 static int jpeg_v3_0_set_powergating_state(void *handle, 493 enum amd_powergating_state state) 494 { 495 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 496 int ret; 497 498 if(state == adev->jpeg.cur_state) 499 return 0; 500 501 if (state == AMD_PG_STATE_GATE) 502 ret = jpeg_v3_0_stop(adev); 503 else 504 ret = jpeg_v3_0_start(adev); 505 506 if(!ret) 507 adev->jpeg.cur_state = state; 508 509 return ret; 510 } 511 512 static int jpeg_v3_0_set_interrupt_state(struct amdgpu_device *adev, 513 struct amdgpu_irq_src *source, 514 unsigned type, 515 enum amdgpu_interrupt_state state) 516 { 517 return 0; 518 } 519 520 static int jpeg_v3_0_process_interrupt(struct amdgpu_device *adev, 521 struct amdgpu_irq_src *source, 522 struct amdgpu_iv_entry *entry) 523 { 524 DRM_DEBUG("IH: JPEG TRAP\n"); 525 526 switch (entry->src_id) { 527 case VCN_2_0__SRCID__JPEG_DECODE: 528 amdgpu_fence_process(&adev->jpeg.inst->ring_dec); 529 break; 530 default: 531 DRM_ERROR("Unhandled interrupt: %d %d\n", 532 entry->src_id, entry->src_data[0]); 533 break; 534 } 535 536 return 0; 537 } 538 539 static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = { 540 .name = "jpeg_v3_0", 541 .early_init = jpeg_v3_0_early_init, 542 .late_init = NULL, 543 .sw_init = jpeg_v3_0_sw_init, 544 .sw_fini = jpeg_v3_0_sw_fini, 545 .hw_init = jpeg_v3_0_hw_init, 546 .hw_fini = jpeg_v3_0_hw_fini, 547 .suspend = jpeg_v3_0_suspend, 548 .resume = jpeg_v3_0_resume, 549 .is_idle = jpeg_v3_0_is_idle, 550 .wait_for_idle = jpeg_v3_0_wait_for_idle, 551 .check_soft_reset = NULL, 552 .pre_soft_reset = NULL, 553 .soft_reset = NULL, 554 .post_soft_reset = NULL, 555 .set_clockgating_state = jpeg_v3_0_set_clockgating_state, 556 .set_powergating_state = jpeg_v3_0_set_powergating_state, 557 }; 558 559 static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = { 560 .type = AMDGPU_RING_TYPE_VCN_JPEG, 561 .align_mask = 0xf, 562 .vmhub = AMDGPU_MMHUB_0, 563 .get_rptr = jpeg_v3_0_dec_ring_get_rptr, 564 .get_wptr = jpeg_v3_0_dec_ring_get_wptr, 565 .set_wptr = jpeg_v3_0_dec_ring_set_wptr, 566 .emit_frame_size = 567 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 568 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 569 8 + /* jpeg_v3_0_dec_ring_emit_vm_flush */ 570 18 + 18 + /* jpeg_v3_0_dec_ring_emit_fence x2 vm fence */ 571 8 + 16, 572 .emit_ib_size = 22, /* jpeg_v3_0_dec_ring_emit_ib */ 573 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 574 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 575 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 576 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 577 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 578 .insert_nop = jpeg_v2_0_dec_ring_nop, 579 .insert_start = jpeg_v2_0_dec_ring_insert_start, 580 .insert_end = jpeg_v2_0_dec_ring_insert_end, 581 .pad_ib = amdgpu_ring_generic_pad_ib, 582 .begin_use = amdgpu_jpeg_ring_begin_use, 583 .end_use = amdgpu_jpeg_ring_end_use, 584 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 585 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 586 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 587 }; 588 589 static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 590 { 591 adev->jpeg.inst->ring_dec.funcs = &jpeg_v3_0_dec_ring_vm_funcs; 592 DRM_INFO("JPEG decode is enabled in VM mode\n"); 593 } 594 595 static const struct amdgpu_irq_src_funcs jpeg_v3_0_irq_funcs = { 596 .set = jpeg_v3_0_set_interrupt_state, 597 .process = jpeg_v3_0_process_interrupt, 598 }; 599 600 static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev) 601 { 602 adev->jpeg.inst->irq.num_types = 1; 603 adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs; 604 } 605 606 const struct amdgpu_ip_block_version jpeg_v3_0_ip_block = 607 { 608 .type = AMD_IP_BLOCK_TYPE_JPEG, 609 .major = 3, 610 .minor = 0, 611 .rev = 0, 612 .funcs = &jpeg_v3_0_ip_funcs, 613 }; 614