1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_pm.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "jpeg_v2_0.h" 30 31 #include "vcn/vcn_3_0_0_offset.h" 32 #include "vcn/vcn_3_0_0_sh_mask.h" 33 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 34 35 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 36 37 static const struct amdgpu_hwip_reg_entry jpeg_reg_list_3_0[] = { 38 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 39 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT), 40 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR), 41 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR), 42 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL), 43 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE), 44 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS), 45 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE), 46 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG), 47 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE), 48 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE), 49 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH), 50 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH), 51 }; 52 53 static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 54 static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev); 55 static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 56 enum amd_powergating_state state); 57 58 /** 59 * jpeg_v3_0_early_init - set function pointers 60 * 61 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 62 * 63 * Set ring and irq function pointers 64 */ 65 static int jpeg_v3_0_early_init(struct amdgpu_ip_block *ip_block) 66 { 67 struct amdgpu_device *adev = ip_block->adev; 68 69 u32 harvest; 70 71 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 72 case IP_VERSION(3, 1, 1): 73 case IP_VERSION(3, 1, 2): 74 break; 75 default: 76 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING); 77 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 78 return -ENOENT; 79 break; 80 } 81 82 adev->jpeg.num_jpeg_inst = 1; 83 adev->jpeg.num_jpeg_rings = 1; 84 85 jpeg_v3_0_set_dec_ring_funcs(adev); 86 jpeg_v3_0_set_irq_funcs(adev); 87 88 return 0; 89 } 90 91 /** 92 * jpeg_v3_0_sw_init - sw init for JPEG block 93 * 94 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 95 * 96 * Load firmware and sw initialization 97 */ 98 static int jpeg_v3_0_sw_init(struct amdgpu_ip_block *ip_block) 99 { 100 struct amdgpu_device *adev = ip_block->adev; 101 struct amdgpu_ring *ring; 102 int r; 103 104 /* JPEG TRAP */ 105 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 106 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 107 if (r) 108 return r; 109 110 r = amdgpu_jpeg_sw_init(adev); 111 if (r) 112 return r; 113 114 r = amdgpu_jpeg_resume(adev); 115 if (r) 116 return r; 117 118 ring = adev->jpeg.inst->ring_dec; 119 ring->use_doorbell = true; 120 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 121 ring->vm_hub = AMDGPU_MMHUB0(0); 122 sprintf(ring->name, "jpeg_dec"); 123 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 124 AMDGPU_RING_PRIO_DEFAULT, NULL); 125 if (r) 126 return r; 127 128 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 129 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); 130 131 r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_3_0, ARRAY_SIZE(jpeg_reg_list_3_0)); 132 if (r) 133 return r; 134 135 return 0; 136 } 137 138 /** 139 * jpeg_v3_0_sw_fini - sw fini for JPEG block 140 * 141 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 142 * 143 * JPEG suspend and free up sw allocation 144 */ 145 static int jpeg_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) 146 { 147 struct amdgpu_device *adev = ip_block->adev; 148 int r; 149 150 r = amdgpu_jpeg_suspend(adev); 151 if (r) 152 return r; 153 154 r = amdgpu_jpeg_sw_fini(adev); 155 156 return r; 157 } 158 159 /** 160 * jpeg_v3_0_hw_init - start and test JPEG block 161 * 162 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 163 * 164 */ 165 static int jpeg_v3_0_hw_init(struct amdgpu_ip_block *ip_block) 166 { 167 struct amdgpu_device *adev = ip_block->adev; 168 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 169 170 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 171 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 172 173 return amdgpu_ring_test_helper(ring); 174 } 175 176 /** 177 * jpeg_v3_0_hw_fini - stop the hardware block 178 * 179 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 180 * 181 * Stop the JPEG block, mark ring as not ready any more 182 */ 183 static int jpeg_v3_0_hw_fini(struct amdgpu_ip_block *ip_block) 184 { 185 struct amdgpu_device *adev = ip_block->adev; 186 187 cancel_delayed_work_sync(&adev->jpeg.idle_work); 188 189 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 190 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS)) 191 jpeg_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 192 193 return 0; 194 } 195 196 /** 197 * jpeg_v3_0_suspend - suspend JPEG block 198 * 199 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 200 * 201 * HW fini and suspend JPEG block 202 */ 203 static int jpeg_v3_0_suspend(struct amdgpu_ip_block *ip_block) 204 { 205 int r; 206 207 r = jpeg_v3_0_hw_fini(ip_block); 208 if (r) 209 return r; 210 211 r = amdgpu_jpeg_suspend(ip_block->adev); 212 213 return r; 214 } 215 216 /** 217 * jpeg_v3_0_resume - resume JPEG block 218 * 219 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 220 * 221 * Resume firmware and hw init JPEG block 222 */ 223 static int jpeg_v3_0_resume(struct amdgpu_ip_block *ip_block) 224 { 225 int r; 226 227 r = amdgpu_jpeg_resume(ip_block->adev); 228 if (r) 229 return r; 230 231 r = jpeg_v3_0_hw_init(ip_block); 232 233 return r; 234 } 235 236 static void jpeg_v3_0_disable_clock_gating(struct amdgpu_device *adev) 237 { 238 uint32_t data = 0; 239 240 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 241 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 242 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 243 else 244 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 245 246 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 247 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 248 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 249 250 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 251 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 252 | JPEG_CGC_GATE__JPEG2_DEC_MASK 253 | JPEG_CGC_GATE__JPEG_ENC_MASK 254 | JPEG_CGC_GATE__JMCIF_MASK 255 | JPEG_CGC_GATE__JRBBM_MASK); 256 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 257 258 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 259 data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 260 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 261 | JPEG_CGC_CTRL__JMCIF_MODE_MASK 262 | JPEG_CGC_CTRL__JRBBM_MODE_MASK); 263 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 264 } 265 266 static void jpeg_v3_0_enable_clock_gating(struct amdgpu_device *adev) 267 { 268 uint32_t data = 0; 269 270 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 271 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 272 |JPEG_CGC_GATE__JPEG2_DEC_MASK 273 |JPEG_CGC_GATE__JPEG_ENC_MASK 274 |JPEG_CGC_GATE__JMCIF_MASK 275 |JPEG_CGC_GATE__JRBBM_MASK); 276 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 277 } 278 279 static int jpeg_v3_0_disable_static_power_gating(struct amdgpu_device *adev) 280 { 281 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 282 uint32_t data = 0; 283 int r = 0; 284 285 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 286 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 287 288 r = SOC15_WAIT_ON_RREG(JPEG, 0, 289 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 290 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 291 292 if (r) { 293 DRM_ERROR("amdgpu: JPEG disable power gating failed\n"); 294 return r; 295 } 296 } 297 298 /* disable anti hang mechanism */ 299 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0, 300 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 301 302 /* keep the JPEG in static PG mode */ 303 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0, 304 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); 305 306 return 0; 307 } 308 309 static int jpeg_v3_0_enable_static_power_gating(struct amdgpu_device *adev) 310 { 311 /* enable anti hang mechanism */ 312 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 313 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 314 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 315 316 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 317 uint32_t data = 0; 318 int r = 0; 319 320 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 321 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 322 323 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, 324 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 325 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 326 327 if (r) { 328 DRM_ERROR("amdgpu: JPEG enable power gating failed\n"); 329 return r; 330 } 331 } 332 333 return 0; 334 } 335 336 /** 337 * jpeg_v3_0_start - start JPEG block 338 * 339 * @adev: amdgpu_device pointer 340 * 341 * Setup and start the JPEG block 342 */ 343 static int jpeg_v3_0_start(struct amdgpu_device *adev) 344 { 345 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 346 int r; 347 348 if (adev->pm.dpm_enabled) 349 amdgpu_dpm_enable_jpeg(adev, true); 350 351 /* disable power gating */ 352 r = jpeg_v3_0_disable_static_power_gating(adev); 353 if (r) 354 return r; 355 356 /* JPEG disable CGC */ 357 jpeg_v3_0_disable_clock_gating(adev); 358 359 /* MJPEG global tiling registers */ 360 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, 361 adev->gfx.config.gb_addr_config); 362 WREG32_SOC15(JPEG, 0, mmJPEG_ENC_GFX10_ADDR_CONFIG, 363 adev->gfx.config.gb_addr_config); 364 365 /* enable JMI channel */ 366 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0, 367 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 368 369 /* enable System Interrupt for JRBC */ 370 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN), 371 JPEG_SYS_INT_EN__DJRBC_MASK, 372 ~JPEG_SYS_INT_EN__DJRBC_MASK); 373 374 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 375 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 376 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 377 lower_32_bits(ring->gpu_addr)); 378 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 379 upper_32_bits(ring->gpu_addr)); 380 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); 381 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); 382 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); 383 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); 384 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 385 386 return 0; 387 } 388 389 /** 390 * jpeg_v3_0_stop - stop JPEG block 391 * 392 * @adev: amdgpu_device pointer 393 * 394 * stop the JPEG block 395 */ 396 static int jpeg_v3_0_stop(struct amdgpu_device *adev) 397 { 398 int r; 399 400 /* reset JMI */ 401 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 402 UVD_JMI_CNTL__SOFT_RESET_MASK, 403 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 404 405 jpeg_v3_0_enable_clock_gating(adev); 406 407 /* enable power gating */ 408 r = jpeg_v3_0_enable_static_power_gating(adev); 409 if (r) 410 return r; 411 412 if (adev->pm.dpm_enabled) 413 amdgpu_dpm_enable_jpeg(adev, false); 414 415 return 0; 416 } 417 418 /** 419 * jpeg_v3_0_dec_ring_get_rptr - get read pointer 420 * 421 * @ring: amdgpu_ring pointer 422 * 423 * Returns the current hardware read pointer 424 */ 425 static uint64_t jpeg_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 426 { 427 struct amdgpu_device *adev = ring->adev; 428 429 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); 430 } 431 432 /** 433 * jpeg_v3_0_dec_ring_get_wptr - get write pointer 434 * 435 * @ring: amdgpu_ring pointer 436 * 437 * Returns the current hardware write pointer 438 */ 439 static uint64_t jpeg_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 440 { 441 struct amdgpu_device *adev = ring->adev; 442 443 if (ring->use_doorbell) 444 return *ring->wptr_cpu_addr; 445 else 446 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 447 } 448 449 /** 450 * jpeg_v3_0_dec_ring_set_wptr - set write pointer 451 * 452 * @ring: amdgpu_ring pointer 453 * 454 * Commits the write pointer to the hardware 455 */ 456 static void jpeg_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 457 { 458 struct amdgpu_device *adev = ring->adev; 459 460 if (ring->use_doorbell) { 461 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 462 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 463 } else { 464 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 465 } 466 } 467 468 static bool jpeg_v3_0_is_idle(void *handle) 469 { 470 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 471 int ret = 1; 472 473 ret &= (((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) & 474 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 475 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 476 477 return ret; 478 } 479 480 static int jpeg_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 481 { 482 struct amdgpu_device *adev = ip_block->adev; 483 484 return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, 485 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 486 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 487 } 488 489 static int jpeg_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 490 enum amd_clockgating_state state) 491 { 492 struct amdgpu_device *adev = ip_block->adev; 493 bool enable = state == AMD_CG_STATE_GATE; 494 495 if (enable) { 496 if (!jpeg_v3_0_is_idle(adev)) 497 return -EBUSY; 498 jpeg_v3_0_enable_clock_gating(adev); 499 } else { 500 jpeg_v3_0_disable_clock_gating(adev); 501 } 502 503 return 0; 504 } 505 506 static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 507 enum amd_powergating_state state) 508 { 509 struct amdgpu_device *adev = ip_block->adev; 510 int ret; 511 512 if(state == adev->jpeg.cur_state) 513 return 0; 514 515 if (state == AMD_PG_STATE_GATE) 516 ret = jpeg_v3_0_stop(adev); 517 else 518 ret = jpeg_v3_0_start(adev); 519 520 if(!ret) 521 adev->jpeg.cur_state = state; 522 523 return ret; 524 } 525 526 static int jpeg_v3_0_set_interrupt_state(struct amdgpu_device *adev, 527 struct amdgpu_irq_src *source, 528 unsigned type, 529 enum amdgpu_interrupt_state state) 530 { 531 return 0; 532 } 533 534 static int jpeg_v3_0_process_interrupt(struct amdgpu_device *adev, 535 struct amdgpu_irq_src *source, 536 struct amdgpu_iv_entry *entry) 537 { 538 DRM_DEBUG("IH: JPEG TRAP\n"); 539 540 switch (entry->src_id) { 541 case VCN_2_0__SRCID__JPEG_DECODE: 542 amdgpu_fence_process(adev->jpeg.inst->ring_dec); 543 break; 544 default: 545 DRM_ERROR("Unhandled interrupt: %d %d\n", 546 entry->src_id, entry->src_data[0]); 547 break; 548 } 549 550 return 0; 551 } 552 553 static const struct amd_ip_funcs jpeg_v3_0_ip_funcs = { 554 .name = "jpeg_v3_0", 555 .early_init = jpeg_v3_0_early_init, 556 .sw_init = jpeg_v3_0_sw_init, 557 .sw_fini = jpeg_v3_0_sw_fini, 558 .hw_init = jpeg_v3_0_hw_init, 559 .hw_fini = jpeg_v3_0_hw_fini, 560 .suspend = jpeg_v3_0_suspend, 561 .resume = jpeg_v3_0_resume, 562 .is_idle = jpeg_v3_0_is_idle, 563 .wait_for_idle = jpeg_v3_0_wait_for_idle, 564 .set_clockgating_state = jpeg_v3_0_set_clockgating_state, 565 .set_powergating_state = jpeg_v3_0_set_powergating_state, 566 .dump_ip_state = amdgpu_jpeg_dump_ip_state, 567 .print_ip_state = amdgpu_jpeg_print_ip_state, 568 }; 569 570 static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = { 571 .type = AMDGPU_RING_TYPE_VCN_JPEG, 572 .align_mask = 0xf, 573 .get_rptr = jpeg_v3_0_dec_ring_get_rptr, 574 .get_wptr = jpeg_v3_0_dec_ring_get_wptr, 575 .set_wptr = jpeg_v3_0_dec_ring_set_wptr, 576 .parse_cs = jpeg_v2_dec_ring_parse_cs, 577 .emit_frame_size = 578 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 579 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 580 8 + /* jpeg_v3_0_dec_ring_emit_vm_flush */ 581 18 + 18 + /* jpeg_v3_0_dec_ring_emit_fence x2 vm fence */ 582 8 + 16, 583 .emit_ib_size = 22, /* jpeg_v3_0_dec_ring_emit_ib */ 584 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 585 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 586 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 587 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 588 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 589 .insert_nop = jpeg_v2_0_dec_ring_nop, 590 .insert_start = jpeg_v2_0_dec_ring_insert_start, 591 .insert_end = jpeg_v2_0_dec_ring_insert_end, 592 .pad_ib = amdgpu_ring_generic_pad_ib, 593 .begin_use = amdgpu_jpeg_ring_begin_use, 594 .end_use = amdgpu_jpeg_ring_end_use, 595 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 596 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 597 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 598 }; 599 600 static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 601 { 602 adev->jpeg.inst->ring_dec->funcs = &jpeg_v3_0_dec_ring_vm_funcs; 603 } 604 605 static const struct amdgpu_irq_src_funcs jpeg_v3_0_irq_funcs = { 606 .set = jpeg_v3_0_set_interrupt_state, 607 .process = jpeg_v3_0_process_interrupt, 608 }; 609 610 static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev) 611 { 612 adev->jpeg.inst->irq.num_types = 1; 613 adev->jpeg.inst->irq.funcs = &jpeg_v3_0_irq_funcs; 614 } 615 616 const struct amdgpu_ip_block_version jpeg_v3_0_ip_block = 617 { 618 .type = AMD_IP_BLOCK_TYPE_JPEG, 619 .major = 3, 620 .minor = 0, 621 .rev = 0, 622 .funcs = &jpeg_v3_0_ip_funcs, 623 }; 624