1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "soc15.h" 27 #include "soc15d.h" 28 #include "jpeg_v2_0.h" 29 30 #include "vcn/vcn_2_5_offset.h" 31 #include "vcn/vcn_2_5_sh_mask.h" 32 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 33 34 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 35 36 #define JPEG25_MAX_HW_INSTANCES_ARCTURUS 2 37 38 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); 39 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev); 40 static int jpeg_v2_5_set_powergating_state(void *handle, 41 enum amd_powergating_state state); 42 43 static int amdgpu_ih_clientid_jpeg[] = { 44 SOC15_IH_CLIENTID_VCN, 45 SOC15_IH_CLIENTID_VCN1 46 }; 47 48 /** 49 * jpeg_v2_5_early_init - set function pointers 50 * 51 * @handle: amdgpu_device pointer 52 * 53 * Set ring and irq function pointers 54 */ 55 static int jpeg_v2_5_early_init(void *handle) 56 { 57 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 58 u32 harvest; 59 int i; 60 61 adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS; 62 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 63 harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING); 64 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 65 adev->jpeg.harvest_config |= 1 << i; 66 } 67 if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 | 68 AMDGPU_JPEG_HARVEST_JPEG1)) 69 return -ENOENT; 70 71 jpeg_v2_5_set_dec_ring_funcs(adev); 72 jpeg_v2_5_set_irq_funcs(adev); 73 74 return 0; 75 } 76 77 /** 78 * jpeg_v2_5_sw_init - sw init for JPEG block 79 * 80 * @handle: amdgpu_device pointer 81 * 82 * Load firmware and sw initialization 83 */ 84 static int jpeg_v2_5_sw_init(void *handle) 85 { 86 struct amdgpu_ring *ring; 87 int i, r; 88 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 89 90 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 91 if (adev->jpeg.harvest_config & (1 << i)) 92 continue; 93 94 /* JPEG TRAP */ 95 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i], 96 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq); 97 if (r) 98 return r; 99 } 100 101 r = amdgpu_jpeg_sw_init(adev); 102 if (r) 103 return r; 104 105 r = amdgpu_jpeg_resume(adev); 106 if (r) 107 return r; 108 109 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 110 if (adev->jpeg.harvest_config & (1 << i)) 111 continue; 112 113 ring = &adev->jpeg.inst[i].ring_dec; 114 ring->use_doorbell = true; 115 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i; 116 sprintf(ring->name, "jpeg_dec_%d", i); 117 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, 118 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 119 if (r) 120 return r; 121 122 adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 123 adev->jpeg.inst[i].external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH); 124 } 125 126 return 0; 127 } 128 129 /** 130 * jpeg_v2_5_sw_fini - sw fini for JPEG block 131 * 132 * @handle: amdgpu_device pointer 133 * 134 * JPEG suspend and free up sw allocation 135 */ 136 static int jpeg_v2_5_sw_fini(void *handle) 137 { 138 int r; 139 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 140 141 r = amdgpu_jpeg_suspend(adev); 142 if (r) 143 return r; 144 145 r = amdgpu_jpeg_sw_fini(adev); 146 147 return r; 148 } 149 150 /** 151 * jpeg_v2_5_hw_init - start and test JPEG block 152 * 153 * @handle: amdgpu_device pointer 154 * 155 */ 156 static int jpeg_v2_5_hw_init(void *handle) 157 { 158 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 159 struct amdgpu_ring *ring; 160 int i, r; 161 162 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 163 if (adev->jpeg.harvest_config & (1 << i)) 164 continue; 165 166 ring = &adev->jpeg.inst[i].ring_dec; 167 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 168 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i); 169 170 r = amdgpu_ring_test_helper(ring); 171 if (r) 172 return r; 173 } 174 175 DRM_INFO("JPEG decode initialized successfully.\n"); 176 177 return 0; 178 } 179 180 /** 181 * jpeg_v2_5_hw_fini - stop the hardware block 182 * 183 * @handle: amdgpu_device pointer 184 * 185 * Stop the JPEG block, mark ring as not ready any more 186 */ 187 static int jpeg_v2_5_hw_fini(void *handle) 188 { 189 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 190 int i; 191 192 cancel_delayed_work_sync(&adev->vcn.idle_work); 193 194 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 195 if (adev->jpeg.harvest_config & (1 << i)) 196 continue; 197 198 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 199 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS)) 200 jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE); 201 } 202 203 return 0; 204 } 205 206 /** 207 * jpeg_v2_5_suspend - suspend JPEG block 208 * 209 * @handle: amdgpu_device pointer 210 * 211 * HW fini and suspend JPEG block 212 */ 213 static int jpeg_v2_5_suspend(void *handle) 214 { 215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 216 int r; 217 218 r = jpeg_v2_5_hw_fini(adev); 219 if (r) 220 return r; 221 222 r = amdgpu_jpeg_suspend(adev); 223 224 return r; 225 } 226 227 /** 228 * jpeg_v2_5_resume - resume JPEG block 229 * 230 * @handle: amdgpu_device pointer 231 * 232 * Resume firmware and hw init JPEG block 233 */ 234 static int jpeg_v2_5_resume(void *handle) 235 { 236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 237 int r; 238 239 r = amdgpu_jpeg_resume(adev); 240 if (r) 241 return r; 242 243 r = jpeg_v2_5_hw_init(adev); 244 245 return r; 246 } 247 248 static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst) 249 { 250 uint32_t data; 251 252 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); 253 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 254 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 255 else 256 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 257 258 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 259 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 260 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); 261 262 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); 263 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 264 | JPEG_CGC_GATE__JPEG2_DEC_MASK 265 | JPEG_CGC_GATE__JMCIF_MASK 266 | JPEG_CGC_GATE__JRBBM_MASK); 267 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); 268 269 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); 270 data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 271 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 272 | JPEG_CGC_CTRL__JMCIF_MODE_MASK 273 | JPEG_CGC_CTRL__JRBBM_MODE_MASK); 274 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); 275 } 276 277 static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst) 278 { 279 uint32_t data; 280 281 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); 282 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 283 |JPEG_CGC_GATE__JPEG2_DEC_MASK 284 |JPEG_CGC_GATE__JPEG_ENC_MASK 285 |JPEG_CGC_GATE__JMCIF_MASK 286 |JPEG_CGC_GATE__JRBBM_MASK); 287 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); 288 } 289 290 /** 291 * jpeg_v2_5_start - start JPEG block 292 * 293 * @adev: amdgpu_device pointer 294 * 295 * Setup and start the JPEG block 296 */ 297 static int jpeg_v2_5_start(struct amdgpu_device *adev) 298 { 299 struct amdgpu_ring *ring; 300 int i; 301 302 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 303 if (adev->jpeg.harvest_config & (1 << i)) 304 continue; 305 306 ring = &adev->jpeg.inst[i].ring_dec; 307 /* disable anti hang mechanism */ 308 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0, 309 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 310 311 /* JPEG disable CGC */ 312 jpeg_v2_5_disable_clock_gating(adev, i); 313 314 /* MJPEG global tiling registers */ 315 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG, 316 adev->gfx.config.gb_addr_config); 317 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG, 318 adev->gfx.config.gb_addr_config); 319 320 /* enable JMI channel */ 321 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0, 322 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 323 324 /* enable System Interrupt for JRBC */ 325 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN), 326 JPEG_SYS_INT_EN__DJRBC_MASK, 327 ~JPEG_SYS_INT_EN__DJRBC_MASK); 328 329 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0); 330 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 331 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 332 lower_32_bits(ring->gpu_addr)); 333 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 334 upper_32_bits(ring->gpu_addr)); 335 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0); 336 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0); 337 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L); 338 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); 339 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR); 340 } 341 342 return 0; 343 } 344 345 /** 346 * jpeg_v2_5_stop - stop JPEG block 347 * 348 * @adev: amdgpu_device pointer 349 * 350 * stop the JPEG block 351 */ 352 static int jpeg_v2_5_stop(struct amdgpu_device *adev) 353 { 354 int i; 355 356 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 357 if (adev->jpeg.harvest_config & (1 << i)) 358 continue; 359 360 /* reset JMI */ 361 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 362 UVD_JMI_CNTL__SOFT_RESET_MASK, 363 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 364 365 jpeg_v2_5_enable_clock_gating(adev, i); 366 367 /* enable anti hang mechanism */ 368 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 369 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 370 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 371 } 372 373 return 0; 374 } 375 376 /** 377 * jpeg_v2_5_dec_ring_get_rptr - get read pointer 378 * 379 * @ring: amdgpu_ring pointer 380 * 381 * Returns the current hardware read pointer 382 */ 383 static uint64_t jpeg_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring) 384 { 385 struct amdgpu_device *adev = ring->adev; 386 387 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR); 388 } 389 390 /** 391 * jpeg_v2_5_dec_ring_get_wptr - get write pointer 392 * 393 * @ring: amdgpu_ring pointer 394 * 395 * Returns the current hardware write pointer 396 */ 397 static uint64_t jpeg_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring) 398 { 399 struct amdgpu_device *adev = ring->adev; 400 401 if (ring->use_doorbell) 402 return adev->wb.wb[ring->wptr_offs]; 403 else 404 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR); 405 } 406 407 /** 408 * jpeg_v2_5_dec_ring_set_wptr - set write pointer 409 * 410 * @ring: amdgpu_ring pointer 411 * 412 * Commits the write pointer to the hardware 413 */ 414 static void jpeg_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) 415 { 416 struct amdgpu_device *adev = ring->adev; 417 418 if (ring->use_doorbell) { 419 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 420 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 421 } else { 422 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 423 } 424 } 425 426 /** 427 * jpeg_v2_6_dec_ring_insert_start - insert a start command 428 * 429 * @ring: amdgpu_ring pointer 430 * 431 * Write a start command to the ring. 432 */ 433 static void jpeg_v2_6_dec_ring_insert_start(struct amdgpu_ring *ring) 434 { 435 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 436 0, 0, PACKETJ_TYPE0)); 437 amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 438 439 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 440 0, 0, PACKETJ_TYPE0)); 441 amdgpu_ring_write(ring, 0x80000000 | (1 << (ring->me * 2 + 14))); 442 } 443 444 /** 445 * jpeg_v2_6_dec_ring_insert_end - insert a end command 446 * 447 * @ring: amdgpu_ring pointer 448 * 449 * Write a end command to the ring. 450 */ 451 static void jpeg_v2_6_dec_ring_insert_end(struct amdgpu_ring *ring) 452 { 453 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 454 0, 0, PACKETJ_TYPE0)); 455 amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 456 457 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 458 0, 0, PACKETJ_TYPE0)); 459 amdgpu_ring_write(ring, (1 << (ring->me * 2 + 14))); 460 } 461 462 static bool jpeg_v2_5_is_idle(void *handle) 463 { 464 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 465 int i, ret = 1; 466 467 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 468 if (adev->jpeg.harvest_config & (1 << i)) 469 continue; 470 471 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) & 472 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 473 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 474 } 475 476 return ret; 477 } 478 479 static int jpeg_v2_5_wait_for_idle(void *handle) 480 { 481 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 482 int i, ret; 483 484 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 485 if (adev->jpeg.harvest_config & (1 << i)) 486 continue; 487 488 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS, 489 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 490 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 491 if (ret) 492 return ret; 493 } 494 495 return 0; 496 } 497 498 static int jpeg_v2_5_set_clockgating_state(void *handle, 499 enum amd_clockgating_state state) 500 { 501 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 502 bool enable = (state == AMD_CG_STATE_GATE); 503 int i; 504 505 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 506 if (adev->jpeg.harvest_config & (1 << i)) 507 continue; 508 509 if (enable) { 510 if (!jpeg_v2_5_is_idle(handle)) 511 return -EBUSY; 512 jpeg_v2_5_enable_clock_gating(adev, i); 513 } else { 514 jpeg_v2_5_disable_clock_gating(adev, i); 515 } 516 } 517 518 return 0; 519 } 520 521 static int jpeg_v2_5_set_powergating_state(void *handle, 522 enum amd_powergating_state state) 523 { 524 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 525 int ret; 526 527 if(state == adev->jpeg.cur_state) 528 return 0; 529 530 if (state == AMD_PG_STATE_GATE) 531 ret = jpeg_v2_5_stop(adev); 532 else 533 ret = jpeg_v2_5_start(adev); 534 535 if(!ret) 536 adev->jpeg.cur_state = state; 537 538 return ret; 539 } 540 541 static int jpeg_v2_5_set_interrupt_state(struct amdgpu_device *adev, 542 struct amdgpu_irq_src *source, 543 unsigned type, 544 enum amdgpu_interrupt_state state) 545 { 546 return 0; 547 } 548 549 static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev, 550 struct amdgpu_irq_src *source, 551 struct amdgpu_iv_entry *entry) 552 { 553 uint32_t ip_instance; 554 555 switch (entry->client_id) { 556 case SOC15_IH_CLIENTID_VCN: 557 ip_instance = 0; 558 break; 559 case SOC15_IH_CLIENTID_VCN1: 560 ip_instance = 1; 561 break; 562 default: 563 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 564 return 0; 565 } 566 567 DRM_DEBUG("IH: JPEG TRAP\n"); 568 569 switch (entry->src_id) { 570 case VCN_2_0__SRCID__JPEG_DECODE: 571 amdgpu_fence_process(&adev->jpeg.inst[ip_instance].ring_dec); 572 break; 573 default: 574 DRM_ERROR("Unhandled interrupt: %d %d\n", 575 entry->src_id, entry->src_data[0]); 576 break; 577 } 578 579 return 0; 580 } 581 582 static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = { 583 .name = "jpeg_v2_5", 584 .early_init = jpeg_v2_5_early_init, 585 .late_init = NULL, 586 .sw_init = jpeg_v2_5_sw_init, 587 .sw_fini = jpeg_v2_5_sw_fini, 588 .hw_init = jpeg_v2_5_hw_init, 589 .hw_fini = jpeg_v2_5_hw_fini, 590 .suspend = jpeg_v2_5_suspend, 591 .resume = jpeg_v2_5_resume, 592 .is_idle = jpeg_v2_5_is_idle, 593 .wait_for_idle = jpeg_v2_5_wait_for_idle, 594 .check_soft_reset = NULL, 595 .pre_soft_reset = NULL, 596 .soft_reset = NULL, 597 .post_soft_reset = NULL, 598 .set_clockgating_state = jpeg_v2_5_set_clockgating_state, 599 .set_powergating_state = jpeg_v2_5_set_powergating_state, 600 }; 601 602 static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = { 603 .name = "jpeg_v2_6", 604 .early_init = jpeg_v2_5_early_init, 605 .late_init = NULL, 606 .sw_init = jpeg_v2_5_sw_init, 607 .sw_fini = jpeg_v2_5_sw_fini, 608 .hw_init = jpeg_v2_5_hw_init, 609 .hw_fini = jpeg_v2_5_hw_fini, 610 .suspend = jpeg_v2_5_suspend, 611 .resume = jpeg_v2_5_resume, 612 .is_idle = jpeg_v2_5_is_idle, 613 .wait_for_idle = jpeg_v2_5_wait_for_idle, 614 .check_soft_reset = NULL, 615 .pre_soft_reset = NULL, 616 .soft_reset = NULL, 617 .post_soft_reset = NULL, 618 .set_clockgating_state = jpeg_v2_5_set_clockgating_state, 619 .set_powergating_state = jpeg_v2_5_set_powergating_state, 620 }; 621 622 static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = { 623 .type = AMDGPU_RING_TYPE_VCN_JPEG, 624 .align_mask = 0xf, 625 .vmhub = AMDGPU_MMHUB_1, 626 .get_rptr = jpeg_v2_5_dec_ring_get_rptr, 627 .get_wptr = jpeg_v2_5_dec_ring_get_wptr, 628 .set_wptr = jpeg_v2_5_dec_ring_set_wptr, 629 .emit_frame_size = 630 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 631 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 632 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */ 633 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */ 634 8 + 16, 635 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */ 636 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 637 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 638 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 639 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 640 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 641 .insert_nop = jpeg_v2_0_dec_ring_nop, 642 .insert_start = jpeg_v2_0_dec_ring_insert_start, 643 .insert_end = jpeg_v2_0_dec_ring_insert_end, 644 .pad_ib = amdgpu_ring_generic_pad_ib, 645 .begin_use = amdgpu_jpeg_ring_begin_use, 646 .end_use = amdgpu_jpeg_ring_end_use, 647 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 648 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 649 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 650 }; 651 652 static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = { 653 .type = AMDGPU_RING_TYPE_VCN_JPEG, 654 .align_mask = 0xf, 655 .vmhub = AMDGPU_MMHUB_0, 656 .get_rptr = jpeg_v2_5_dec_ring_get_rptr, 657 .get_wptr = jpeg_v2_5_dec_ring_get_wptr, 658 .set_wptr = jpeg_v2_5_dec_ring_set_wptr, 659 .emit_frame_size = 660 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 661 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 662 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */ 663 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */ 664 8 + 16, 665 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */ 666 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 667 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 668 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 669 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 670 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 671 .insert_nop = jpeg_v2_0_dec_ring_nop, 672 .insert_start = jpeg_v2_6_dec_ring_insert_start, 673 .insert_end = jpeg_v2_6_dec_ring_insert_end, 674 .pad_ib = amdgpu_ring_generic_pad_ib, 675 .begin_use = amdgpu_jpeg_ring_begin_use, 676 .end_use = amdgpu_jpeg_ring_end_use, 677 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 678 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 679 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 680 }; 681 682 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) 683 { 684 int i; 685 686 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 687 if (adev->jpeg.harvest_config & (1 << i)) 688 continue; 689 if (adev->asic_type == CHIP_ARCTURUS) 690 adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs; 691 else /* CHIP_ALDEBARAN */ 692 adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_6_dec_ring_vm_funcs; 693 adev->jpeg.inst[i].ring_dec.me = i; 694 DRM_INFO("JPEG(%d) JPEG decode is enabled in VM mode\n", i); 695 } 696 } 697 698 static const struct amdgpu_irq_src_funcs jpeg_v2_5_irq_funcs = { 699 .set = jpeg_v2_5_set_interrupt_state, 700 .process = jpeg_v2_5_process_interrupt, 701 }; 702 703 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev) 704 { 705 int i; 706 707 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 708 if (adev->jpeg.harvest_config & (1 << i)) 709 continue; 710 711 adev->jpeg.inst[i].irq.num_types = 1; 712 adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs; 713 } 714 } 715 716 const struct amdgpu_ip_block_version jpeg_v2_5_ip_block = 717 { 718 .type = AMD_IP_BLOCK_TYPE_JPEG, 719 .major = 2, 720 .minor = 5, 721 .rev = 0, 722 .funcs = &jpeg_v2_5_ip_funcs, 723 }; 724 725 const struct amdgpu_ip_block_version jpeg_v2_6_ip_block = 726 { 727 .type = AMD_IP_BLOCK_TYPE_JPEG, 728 .major = 2, 729 .minor = 6, 730 .rev = 0, 731 .funcs = &jpeg_v2_6_ip_funcs, 732 }; 733