1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "soc15.h" 27 #include "soc15d.h" 28 #include "jpeg_v2_0.h" 29 #include "jpeg_v2_5.h" 30 31 #include "vcn/vcn_2_5_offset.h" 32 #include "vcn/vcn_2_5_sh_mask.h" 33 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 34 35 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f 36 37 #define JPEG25_MAX_HW_INSTANCES_ARCTURUS 2 38 39 static const struct amdgpu_hwip_reg_entry jpeg_reg_list_2_5[] = { 40 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 41 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT), 42 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR), 43 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR), 44 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL), 45 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE), 46 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS), 47 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE), 48 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG), 49 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE), 50 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE), 51 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH), 52 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH), 53 }; 54 55 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); 56 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev); 57 static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block, 58 enum amd_powergating_state state); 59 static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev); 60 61 static int amdgpu_ih_clientid_jpeg[] = { 62 SOC15_IH_CLIENTID_VCN, 63 SOC15_IH_CLIENTID_VCN1 64 }; 65 66 /** 67 * jpeg_v2_5_early_init - set function pointers 68 * 69 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 70 * 71 * Set ring and irq function pointers 72 */ 73 static int jpeg_v2_5_early_init(struct amdgpu_ip_block *ip_block) 74 { 75 struct amdgpu_device *adev = ip_block->adev; 76 u32 harvest; 77 int i; 78 79 adev->jpeg.num_jpeg_rings = 1; 80 adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS; 81 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 82 harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING); 83 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 84 adev->jpeg.harvest_config |= 1 << i; 85 } 86 if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 | 87 AMDGPU_JPEG_HARVEST_JPEG1)) 88 return -ENOENT; 89 90 jpeg_v2_5_set_dec_ring_funcs(adev); 91 jpeg_v2_5_set_irq_funcs(adev); 92 jpeg_v2_5_set_ras_funcs(adev); 93 94 return 0; 95 } 96 97 /** 98 * jpeg_v2_5_sw_init - sw init for JPEG block 99 * 100 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 101 * 102 * Load firmware and sw initialization 103 */ 104 static int jpeg_v2_5_sw_init(struct amdgpu_ip_block *ip_block) 105 { 106 struct amdgpu_ring *ring; 107 int i, r; 108 struct amdgpu_device *adev = ip_block->adev; 109 110 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 111 if (adev->jpeg.harvest_config & (1 << i)) 112 continue; 113 114 /* JPEG TRAP */ 115 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i], 116 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq); 117 if (r) 118 return r; 119 120 /* JPEG DJPEG POISON EVENT */ 121 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i], 122 VCN_2_6__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq); 123 if (r) 124 return r; 125 126 /* JPEG EJPEG POISON EVENT */ 127 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i], 128 VCN_2_6__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].ras_poison_irq); 129 if (r) 130 return r; 131 } 132 133 r = amdgpu_jpeg_sw_init(adev); 134 if (r) 135 return r; 136 137 r = amdgpu_jpeg_resume(adev); 138 if (r) 139 return r; 140 141 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 142 if (adev->jpeg.harvest_config & (1 << i)) 143 continue; 144 145 ring = adev->jpeg.inst[i].ring_dec; 146 ring->use_doorbell = true; 147 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(2, 5, 0)) 148 ring->vm_hub = AMDGPU_MMHUB1(0); 149 else 150 ring->vm_hub = AMDGPU_MMHUB0(0); 151 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i; 152 sprintf(ring->name, "jpeg_dec_%d", i); 153 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, 154 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 155 if (r) 156 return r; 157 158 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 159 adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH); 160 } 161 162 r = amdgpu_jpeg_ras_sw_init(adev); 163 if (r) 164 return r; 165 166 r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_2_5, ARRAY_SIZE(jpeg_reg_list_2_5)); 167 if (r) 168 return r; 169 170 return 0; 171 } 172 173 /** 174 * jpeg_v2_5_sw_fini - sw fini for JPEG block 175 * 176 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 177 * 178 * JPEG suspend and free up sw allocation 179 */ 180 static int jpeg_v2_5_sw_fini(struct amdgpu_ip_block *ip_block) 181 { 182 int r; 183 struct amdgpu_device *adev = ip_block->adev; 184 185 r = amdgpu_jpeg_suspend(adev); 186 if (r) 187 return r; 188 189 r = amdgpu_jpeg_sw_fini(adev); 190 191 return r; 192 } 193 194 /** 195 * jpeg_v2_5_hw_init - start and test JPEG block 196 * 197 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 198 * 199 */ 200 static int jpeg_v2_5_hw_init(struct amdgpu_ip_block *ip_block) 201 { 202 struct amdgpu_device *adev = ip_block->adev; 203 struct amdgpu_ring *ring; 204 int i, r; 205 206 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 207 if (adev->jpeg.harvest_config & (1 << i)) 208 continue; 209 210 ring = adev->jpeg.inst[i].ring_dec; 211 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 212 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i); 213 214 r = amdgpu_ring_test_helper(ring); 215 if (r) 216 return r; 217 } 218 219 return 0; 220 } 221 222 /** 223 * jpeg_v2_5_hw_fini - stop the hardware block 224 * 225 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 226 * 227 * Stop the JPEG block, mark ring as not ready any more 228 */ 229 static int jpeg_v2_5_hw_fini(struct amdgpu_ip_block *ip_block) 230 { 231 struct amdgpu_device *adev = ip_block->adev; 232 int i; 233 234 cancel_delayed_work_sync(&adev->jpeg.idle_work); 235 236 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 237 if (adev->jpeg.harvest_config & (1 << i)) 238 continue; 239 240 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 241 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS)) 242 jpeg_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 243 244 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) 245 amdgpu_irq_put(adev, &adev->jpeg.inst[i].ras_poison_irq, 0); 246 } 247 248 return 0; 249 } 250 251 /** 252 * jpeg_v2_5_suspend - suspend JPEG block 253 * 254 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 255 * 256 * HW fini and suspend JPEG block 257 */ 258 static int jpeg_v2_5_suspend(struct amdgpu_ip_block *ip_block) 259 { 260 int r; 261 262 r = jpeg_v2_5_hw_fini(ip_block); 263 if (r) 264 return r; 265 266 r = amdgpu_jpeg_suspend(ip_block->adev); 267 268 return r; 269 } 270 271 /** 272 * jpeg_v2_5_resume - resume JPEG block 273 * 274 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 275 * 276 * Resume firmware and hw init JPEG block 277 */ 278 static int jpeg_v2_5_resume(struct amdgpu_ip_block *ip_block) 279 { 280 int r; 281 282 r = amdgpu_jpeg_resume(ip_block->adev); 283 if (r) 284 return r; 285 286 r = jpeg_v2_5_hw_init(ip_block); 287 288 return r; 289 } 290 291 static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst) 292 { 293 uint32_t data; 294 295 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); 296 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 297 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 298 else 299 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 300 301 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 302 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 303 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); 304 305 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); 306 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 307 | JPEG_CGC_GATE__JPEG2_DEC_MASK 308 | JPEG_CGC_GATE__JMCIF_MASK 309 | JPEG_CGC_GATE__JRBBM_MASK); 310 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); 311 312 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL); 313 data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 314 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 315 | JPEG_CGC_CTRL__JMCIF_MODE_MASK 316 | JPEG_CGC_CTRL__JRBBM_MODE_MASK); 317 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); 318 } 319 320 static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst) 321 { 322 uint32_t data; 323 324 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE); 325 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 326 |JPEG_CGC_GATE__JPEG2_DEC_MASK 327 |JPEG_CGC_GATE__JPEG_ENC_MASK 328 |JPEG_CGC_GATE__JMCIF_MASK 329 |JPEG_CGC_GATE__JRBBM_MASK); 330 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); 331 } 332 333 /** 334 * jpeg_v2_5_start - start JPEG block 335 * 336 * @adev: amdgpu_device pointer 337 * 338 * Setup and start the JPEG block 339 */ 340 static int jpeg_v2_5_start(struct amdgpu_device *adev) 341 { 342 struct amdgpu_ring *ring; 343 int i; 344 345 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 346 if (adev->jpeg.harvest_config & (1 << i)) 347 continue; 348 349 ring = adev->jpeg.inst[i].ring_dec; 350 /* disable anti hang mechanism */ 351 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0, 352 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 353 354 /* JPEG disable CGC */ 355 jpeg_v2_5_disable_clock_gating(adev, i); 356 357 /* MJPEG global tiling registers */ 358 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG, 359 adev->gfx.config.gb_addr_config); 360 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG, 361 adev->gfx.config.gb_addr_config); 362 363 /* enable JMI channel */ 364 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0, 365 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 366 367 /* enable System Interrupt for JRBC */ 368 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN), 369 JPEG_SYS_INT_EN__DJRBC_MASK, 370 ~JPEG_SYS_INT_EN__DJRBC_MASK); 371 372 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0); 373 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 374 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 375 lower_32_bits(ring->gpu_addr)); 376 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 377 upper_32_bits(ring->gpu_addr)); 378 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0); 379 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0); 380 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L); 381 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); 382 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR); 383 } 384 385 return 0; 386 } 387 388 /** 389 * jpeg_v2_5_stop - stop JPEG block 390 * 391 * @adev: amdgpu_device pointer 392 * 393 * stop the JPEG block 394 */ 395 static int jpeg_v2_5_stop(struct amdgpu_device *adev) 396 { 397 int i; 398 399 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 400 if (adev->jpeg.harvest_config & (1 << i)) 401 continue; 402 403 /* reset JMI */ 404 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 405 UVD_JMI_CNTL__SOFT_RESET_MASK, 406 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 407 408 jpeg_v2_5_enable_clock_gating(adev, i); 409 410 /* enable anti hang mechanism */ 411 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 412 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, 413 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); 414 } 415 416 return 0; 417 } 418 419 /** 420 * jpeg_v2_5_dec_ring_get_rptr - get read pointer 421 * 422 * @ring: amdgpu_ring pointer 423 * 424 * Returns the current hardware read pointer 425 */ 426 static uint64_t jpeg_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring) 427 { 428 struct amdgpu_device *adev = ring->adev; 429 430 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR); 431 } 432 433 /** 434 * jpeg_v2_5_dec_ring_get_wptr - get write pointer 435 * 436 * @ring: amdgpu_ring pointer 437 * 438 * Returns the current hardware write pointer 439 */ 440 static uint64_t jpeg_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring) 441 { 442 struct amdgpu_device *adev = ring->adev; 443 444 if (ring->use_doorbell) 445 return *ring->wptr_cpu_addr; 446 else 447 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR); 448 } 449 450 /** 451 * jpeg_v2_5_dec_ring_set_wptr - set write pointer 452 * 453 * @ring: amdgpu_ring pointer 454 * 455 * Commits the write pointer to the hardware 456 */ 457 static void jpeg_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) 458 { 459 struct amdgpu_device *adev = ring->adev; 460 461 if (ring->use_doorbell) { 462 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 463 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 464 } else { 465 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 466 } 467 } 468 469 /** 470 * jpeg_v2_6_dec_ring_insert_start - insert a start command 471 * 472 * @ring: amdgpu_ring pointer 473 * 474 * Write a start command to the ring. 475 */ 476 static void jpeg_v2_6_dec_ring_insert_start(struct amdgpu_ring *ring) 477 { 478 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 479 0, 0, PACKETJ_TYPE0)); 480 amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 481 482 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 483 0, 0, PACKETJ_TYPE0)); 484 amdgpu_ring_write(ring, 0x80000000 | (1 << (ring->me * 2 + 14))); 485 } 486 487 /** 488 * jpeg_v2_6_dec_ring_insert_end - insert a end command 489 * 490 * @ring: amdgpu_ring pointer 491 * 492 * Write a end command to the ring. 493 */ 494 static void jpeg_v2_6_dec_ring_insert_end(struct amdgpu_ring *ring) 495 { 496 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 497 0, 0, PACKETJ_TYPE0)); 498 amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ 499 500 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 501 0, 0, PACKETJ_TYPE0)); 502 amdgpu_ring_write(ring, (1 << (ring->me * 2 + 14))); 503 } 504 505 static bool jpeg_v2_5_is_idle(void *handle) 506 { 507 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 508 int i, ret = 1; 509 510 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 511 if (adev->jpeg.harvest_config & (1 << i)) 512 continue; 513 514 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) & 515 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 516 UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); 517 } 518 519 return ret; 520 } 521 522 static int jpeg_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block) 523 { 524 struct amdgpu_device *adev = ip_block->adev; 525 int i, ret; 526 527 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 528 if (adev->jpeg.harvest_config & (1 << i)) 529 continue; 530 531 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS, 532 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 533 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 534 if (ret) 535 return ret; 536 } 537 538 return 0; 539 } 540 541 static int jpeg_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block, 542 enum amd_clockgating_state state) 543 { 544 struct amdgpu_device *adev = ip_block->adev; 545 bool enable = (state == AMD_CG_STATE_GATE); 546 int i; 547 548 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 549 if (adev->jpeg.harvest_config & (1 << i)) 550 continue; 551 552 if (enable) { 553 if (!jpeg_v2_5_is_idle(adev)) 554 return -EBUSY; 555 jpeg_v2_5_enable_clock_gating(adev, i); 556 } else { 557 jpeg_v2_5_disable_clock_gating(adev, i); 558 } 559 } 560 561 return 0; 562 } 563 564 static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block, 565 enum amd_powergating_state state) 566 { 567 struct amdgpu_device *adev = ip_block->adev; 568 int ret; 569 570 if (state == adev->jpeg.cur_state) 571 return 0; 572 573 if (state == AMD_PG_STATE_GATE) 574 ret = jpeg_v2_5_stop(adev); 575 else 576 ret = jpeg_v2_5_start(adev); 577 578 if (!ret) 579 adev->jpeg.cur_state = state; 580 581 return ret; 582 } 583 584 static int jpeg_v2_5_set_interrupt_state(struct amdgpu_device *adev, 585 struct amdgpu_irq_src *source, 586 unsigned type, 587 enum amdgpu_interrupt_state state) 588 { 589 return 0; 590 } 591 592 static int jpeg_v2_6_set_ras_interrupt_state(struct amdgpu_device *adev, 593 struct amdgpu_irq_src *source, 594 unsigned int type, 595 enum amdgpu_interrupt_state state) 596 { 597 return 0; 598 } 599 600 static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev, 601 struct amdgpu_irq_src *source, 602 struct amdgpu_iv_entry *entry) 603 { 604 uint32_t ip_instance; 605 606 switch (entry->client_id) { 607 case SOC15_IH_CLIENTID_VCN: 608 ip_instance = 0; 609 break; 610 case SOC15_IH_CLIENTID_VCN1: 611 ip_instance = 1; 612 break; 613 default: 614 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 615 return 0; 616 } 617 618 DRM_DEBUG("IH: JPEG TRAP\n"); 619 620 switch (entry->src_id) { 621 case VCN_2_0__SRCID__JPEG_DECODE: 622 amdgpu_fence_process(adev->jpeg.inst[ip_instance].ring_dec); 623 break; 624 default: 625 DRM_ERROR("Unhandled interrupt: %d %d\n", 626 entry->src_id, entry->src_data[0]); 627 break; 628 } 629 630 return 0; 631 } 632 633 static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = { 634 .name = "jpeg_v2_5", 635 .early_init = jpeg_v2_5_early_init, 636 .sw_init = jpeg_v2_5_sw_init, 637 .sw_fini = jpeg_v2_5_sw_fini, 638 .hw_init = jpeg_v2_5_hw_init, 639 .hw_fini = jpeg_v2_5_hw_fini, 640 .suspend = jpeg_v2_5_suspend, 641 .resume = jpeg_v2_5_resume, 642 .is_idle = jpeg_v2_5_is_idle, 643 .wait_for_idle = jpeg_v2_5_wait_for_idle, 644 .set_clockgating_state = jpeg_v2_5_set_clockgating_state, 645 .set_powergating_state = jpeg_v2_5_set_powergating_state, 646 .dump_ip_state = amdgpu_jpeg_dump_ip_state, 647 .print_ip_state = amdgpu_jpeg_print_ip_state, 648 }; 649 650 static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = { 651 .name = "jpeg_v2_6", 652 .early_init = jpeg_v2_5_early_init, 653 .sw_init = jpeg_v2_5_sw_init, 654 .sw_fini = jpeg_v2_5_sw_fini, 655 .hw_init = jpeg_v2_5_hw_init, 656 .hw_fini = jpeg_v2_5_hw_fini, 657 .suspend = jpeg_v2_5_suspend, 658 .resume = jpeg_v2_5_resume, 659 .is_idle = jpeg_v2_5_is_idle, 660 .wait_for_idle = jpeg_v2_5_wait_for_idle, 661 .set_clockgating_state = jpeg_v2_5_set_clockgating_state, 662 .set_powergating_state = jpeg_v2_5_set_powergating_state, 663 .dump_ip_state = amdgpu_jpeg_dump_ip_state, 664 .print_ip_state = amdgpu_jpeg_print_ip_state, 665 }; 666 667 static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = { 668 .type = AMDGPU_RING_TYPE_VCN_JPEG, 669 .align_mask = 0xf, 670 .get_rptr = jpeg_v2_5_dec_ring_get_rptr, 671 .get_wptr = jpeg_v2_5_dec_ring_get_wptr, 672 .set_wptr = jpeg_v2_5_dec_ring_set_wptr, 673 .parse_cs = jpeg_v2_dec_ring_parse_cs, 674 .emit_frame_size = 675 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 676 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 677 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */ 678 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */ 679 8 + 16, 680 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */ 681 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 682 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 683 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 684 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 685 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 686 .insert_nop = jpeg_v2_0_dec_ring_nop, 687 .insert_start = jpeg_v2_0_dec_ring_insert_start, 688 .insert_end = jpeg_v2_0_dec_ring_insert_end, 689 .pad_ib = amdgpu_ring_generic_pad_ib, 690 .begin_use = amdgpu_jpeg_ring_begin_use, 691 .end_use = amdgpu_jpeg_ring_end_use, 692 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 693 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 694 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 695 }; 696 697 static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = { 698 .type = AMDGPU_RING_TYPE_VCN_JPEG, 699 .align_mask = 0xf, 700 .get_rptr = jpeg_v2_5_dec_ring_get_rptr, 701 .get_wptr = jpeg_v2_5_dec_ring_get_wptr, 702 .set_wptr = jpeg_v2_5_dec_ring_set_wptr, 703 .parse_cs = jpeg_v2_dec_ring_parse_cs, 704 .emit_frame_size = 705 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 706 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 707 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */ 708 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */ 709 8 + 16, 710 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */ 711 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 712 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 713 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 714 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 715 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 716 .insert_nop = jpeg_v2_0_dec_ring_nop, 717 .insert_start = jpeg_v2_6_dec_ring_insert_start, 718 .insert_end = jpeg_v2_6_dec_ring_insert_end, 719 .pad_ib = amdgpu_ring_generic_pad_ib, 720 .begin_use = amdgpu_jpeg_ring_begin_use, 721 .end_use = amdgpu_jpeg_ring_end_use, 722 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 723 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 724 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 725 }; 726 727 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) 728 { 729 int i; 730 731 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 732 if (adev->jpeg.harvest_config & (1 << i)) 733 continue; 734 if (adev->asic_type == CHIP_ARCTURUS) 735 adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_5_dec_ring_vm_funcs; 736 else /* CHIP_ALDEBARAN */ 737 adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_6_dec_ring_vm_funcs; 738 adev->jpeg.inst[i].ring_dec->me = i; 739 } 740 } 741 742 static const struct amdgpu_irq_src_funcs jpeg_v2_5_irq_funcs = { 743 .set = jpeg_v2_5_set_interrupt_state, 744 .process = jpeg_v2_5_process_interrupt, 745 }; 746 747 static const struct amdgpu_irq_src_funcs jpeg_v2_6_ras_irq_funcs = { 748 .set = jpeg_v2_6_set_ras_interrupt_state, 749 .process = amdgpu_jpeg_process_poison_irq, 750 }; 751 752 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev) 753 { 754 int i; 755 756 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 757 if (adev->jpeg.harvest_config & (1 << i)) 758 continue; 759 760 adev->jpeg.inst[i].irq.num_types = 1; 761 adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs; 762 763 adev->jpeg.inst[i].ras_poison_irq.num_types = 1; 764 adev->jpeg.inst[i].ras_poison_irq.funcs = &jpeg_v2_6_ras_irq_funcs; 765 } 766 } 767 768 const struct amdgpu_ip_block_version jpeg_v2_5_ip_block = { 769 .type = AMD_IP_BLOCK_TYPE_JPEG, 770 .major = 2, 771 .minor = 5, 772 .rev = 0, 773 .funcs = &jpeg_v2_5_ip_funcs, 774 }; 775 776 const struct amdgpu_ip_block_version jpeg_v2_6_ip_block = { 777 .type = AMD_IP_BLOCK_TYPE_JPEG, 778 .major = 2, 779 .minor = 6, 780 .rev = 0, 781 .funcs = &jpeg_v2_6_ip_funcs, 782 }; 783 784 static uint32_t jpeg_v2_6_query_poison_by_instance(struct amdgpu_device *adev, 785 uint32_t instance, uint32_t sub_block) 786 { 787 uint32_t poison_stat = 0, reg_value = 0; 788 789 switch (sub_block) { 790 case AMDGPU_JPEG_V2_6_JPEG0: 791 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG0_STATUS); 792 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF); 793 break; 794 case AMDGPU_JPEG_V2_6_JPEG1: 795 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG1_STATUS); 796 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF); 797 break; 798 default: 799 break; 800 } 801 802 if (poison_stat) 803 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n", 804 instance, sub_block); 805 806 return poison_stat; 807 } 808 809 static bool jpeg_v2_6_query_ras_poison_status(struct amdgpu_device *adev) 810 { 811 uint32_t inst = 0, sub = 0, poison_stat = 0; 812 813 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++) 814 for (sub = 0; sub < AMDGPU_JPEG_V2_6_MAX_SUB_BLOCK; sub++) 815 poison_stat += 816 jpeg_v2_6_query_poison_by_instance(adev, inst, sub); 817 818 return !!poison_stat; 819 } 820 821 const struct amdgpu_ras_block_hw_ops jpeg_v2_6_ras_hw_ops = { 822 .query_poison_status = jpeg_v2_6_query_ras_poison_status, 823 }; 824 825 static struct amdgpu_jpeg_ras jpeg_v2_6_ras = { 826 .ras_block = { 827 .hw_ops = &jpeg_v2_6_ras_hw_ops, 828 .ras_late_init = amdgpu_jpeg_ras_late_init, 829 }, 830 }; 831 832 static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev) 833 { 834 switch (amdgpu_ip_version(adev, JPEG_HWIP, 0)) { 835 case IP_VERSION(2, 6, 0): 836 adev->jpeg.ras = &jpeg_v2_6_ras; 837 break; 838 default: 839 break; 840 } 841 } 842