1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_cs.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "jpeg_v2_0.h" 31 32 #include "vcn/vcn_2_0_0_offset.h" 33 #include "vcn/vcn_2_0_0_sh_mask.h" 34 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 35 36 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); 37 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev); 38 static int jpeg_v2_0_set_powergating_state(void *handle, 39 enum amd_powergating_state state); 40 41 /** 42 * jpeg_v2_0_early_init - set function pointers 43 * 44 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 45 * 46 * Set ring and irq function pointers 47 */ 48 static int jpeg_v2_0_early_init(struct amdgpu_ip_block *ip_block) 49 { 50 struct amdgpu_device *adev = ip_block->adev; 51 52 adev->jpeg.num_jpeg_inst = 1; 53 adev->jpeg.num_jpeg_rings = 1; 54 55 jpeg_v2_0_set_dec_ring_funcs(adev); 56 jpeg_v2_0_set_irq_funcs(adev); 57 58 return 0; 59 } 60 61 /** 62 * jpeg_v2_0_sw_init - sw init for JPEG block 63 * 64 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 65 * 66 * Load firmware and sw initialization 67 */ 68 static int jpeg_v2_0_sw_init(struct amdgpu_ip_block *ip_block) 69 { 70 struct amdgpu_device *adev = ip_block->adev; 71 struct amdgpu_ring *ring; 72 int r; 73 74 /* JPEG TRAP */ 75 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 76 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 77 if (r) 78 return r; 79 80 r = amdgpu_jpeg_sw_init(adev); 81 if (r) 82 return r; 83 84 r = amdgpu_jpeg_resume(adev); 85 if (r) 86 return r; 87 88 ring = adev->jpeg.inst->ring_dec; 89 ring->use_doorbell = true; 90 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 91 ring->vm_hub = AMDGPU_MMHUB0(0); 92 sprintf(ring->name, "jpeg_dec"); 93 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 94 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 95 if (r) 96 return r; 97 98 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 99 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); 100 101 return 0; 102 } 103 104 /** 105 * jpeg_v2_0_sw_fini - sw fini for JPEG block 106 * 107 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 108 * 109 * JPEG suspend and free up sw allocation 110 */ 111 static int jpeg_v2_0_sw_fini(struct amdgpu_ip_block *ip_block) 112 { 113 int r; 114 struct amdgpu_device *adev = ip_block->adev; 115 116 r = amdgpu_jpeg_suspend(adev); 117 if (r) 118 return r; 119 120 r = amdgpu_jpeg_sw_fini(adev); 121 122 return r; 123 } 124 125 /** 126 * jpeg_v2_0_hw_init - start and test JPEG block 127 * 128 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 129 * 130 */ 131 static int jpeg_v2_0_hw_init(struct amdgpu_ip_block *ip_block) 132 { 133 struct amdgpu_device *adev = ip_block->adev; 134 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 135 136 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 137 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 138 139 return amdgpu_ring_test_helper(ring); 140 } 141 142 /** 143 * jpeg_v2_0_hw_fini - stop the hardware block 144 * 145 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 146 * 147 * Stop the JPEG block, mark ring as not ready any more 148 */ 149 static int jpeg_v2_0_hw_fini(struct amdgpu_ip_block *ip_block) 150 { 151 struct amdgpu_device *adev = ip_block->adev; 152 153 cancel_delayed_work_sync(&adev->jpeg.idle_work); 154 155 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 156 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS)) 157 jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 158 159 return 0; 160 } 161 162 /** 163 * jpeg_v2_0_suspend - suspend JPEG block 164 * 165 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 166 * 167 * HW fini and suspend JPEG block 168 */ 169 static int jpeg_v2_0_suspend(struct amdgpu_ip_block *ip_block) 170 { 171 int r; 172 173 r = jpeg_v2_0_hw_fini(ip_block); 174 if (r) 175 return r; 176 177 r = amdgpu_jpeg_suspend(ip_block->adev); 178 179 return r; 180 } 181 182 /** 183 * jpeg_v2_0_resume - resume JPEG block 184 * 185 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 186 * 187 * Resume firmware and hw init JPEG block 188 */ 189 static int jpeg_v2_0_resume(struct amdgpu_ip_block *ip_block) 190 { 191 int r; 192 193 r = amdgpu_jpeg_resume(ip_block->adev); 194 if (r) 195 return r; 196 197 r = jpeg_v2_0_hw_init(ip_block); 198 199 return r; 200 } 201 202 static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev) 203 { 204 uint32_t data; 205 int r = 0; 206 207 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 208 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 209 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 210 211 r = SOC15_WAIT_ON_RREG(JPEG, 0, 212 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 213 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 214 215 if (r) { 216 DRM_ERROR("amdgpu: JPEG disable power gating failed\n"); 217 return r; 218 } 219 } 220 221 /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */ 222 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1; 223 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); 224 225 return 0; 226 } 227 228 static int jpeg_v2_0_enable_power_gating(struct amdgpu_device *adev) 229 { 230 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 231 uint32_t data; 232 int r = 0; 233 234 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)); 235 data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK; 236 data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF; 237 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); 238 239 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 240 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 241 242 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, 243 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 244 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 245 246 if (r) { 247 DRM_ERROR("amdgpu: JPEG enable power gating failed\n"); 248 return r; 249 } 250 } 251 252 return 0; 253 } 254 255 static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device *adev) 256 { 257 uint32_t data; 258 259 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 260 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 261 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 262 else 263 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 264 265 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 266 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 267 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 268 269 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 270 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 271 | JPEG_CGC_GATE__JPEG2_DEC_MASK 272 | JPEG_CGC_GATE__JPEG_ENC_MASK 273 | JPEG_CGC_GATE__JMCIF_MASK 274 | JPEG_CGC_GATE__JRBBM_MASK); 275 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 276 } 277 278 static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device *adev) 279 { 280 uint32_t data; 281 282 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 283 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 284 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 285 else 286 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 287 288 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 289 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 290 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 291 292 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 293 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 294 |JPEG_CGC_GATE__JPEG2_DEC_MASK 295 |JPEG_CGC_GATE__JPEG_ENC_MASK 296 |JPEG_CGC_GATE__JMCIF_MASK 297 |JPEG_CGC_GATE__JRBBM_MASK); 298 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 299 } 300 301 /** 302 * jpeg_v2_0_start - start JPEG block 303 * 304 * @adev: amdgpu_device pointer 305 * 306 * Setup and start the JPEG block 307 */ 308 static int jpeg_v2_0_start(struct amdgpu_device *adev) 309 { 310 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 311 int r; 312 313 if (adev->pm.dpm_enabled) 314 amdgpu_dpm_enable_jpeg(adev, true); 315 316 /* disable power gating */ 317 r = jpeg_v2_0_disable_power_gating(adev); 318 if (r) 319 return r; 320 321 /* JPEG disable CGC */ 322 jpeg_v2_0_disable_clock_gating(adev); 323 324 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 325 326 /* enable JMI channel */ 327 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0, 328 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 329 330 /* enable System Interrupt for JRBC */ 331 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN), 332 JPEG_SYS_INT_EN__DJRBC_MASK, 333 ~JPEG_SYS_INT_EN__DJRBC_MASK); 334 335 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 336 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 337 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 338 lower_32_bits(ring->gpu_addr)); 339 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 340 upper_32_bits(ring->gpu_addr)); 341 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); 342 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); 343 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); 344 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); 345 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 346 347 return 0; 348 } 349 350 /** 351 * jpeg_v2_0_stop - stop JPEG block 352 * 353 * @adev: amdgpu_device pointer 354 * 355 * stop the JPEG block 356 */ 357 static int jpeg_v2_0_stop(struct amdgpu_device *adev) 358 { 359 int r; 360 361 /* reset JMI */ 362 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 363 UVD_JMI_CNTL__SOFT_RESET_MASK, 364 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 365 366 /* enable JPEG CGC */ 367 jpeg_v2_0_enable_clock_gating(adev); 368 369 /* enable power gating */ 370 r = jpeg_v2_0_enable_power_gating(adev); 371 if (r) 372 return r; 373 374 if (adev->pm.dpm_enabled) 375 amdgpu_dpm_enable_jpeg(adev, false); 376 377 return 0; 378 } 379 380 /** 381 * jpeg_v2_0_dec_ring_get_rptr - get read pointer 382 * 383 * @ring: amdgpu_ring pointer 384 * 385 * Returns the current hardware read pointer 386 */ 387 static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 388 { 389 struct amdgpu_device *adev = ring->adev; 390 391 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); 392 } 393 394 /** 395 * jpeg_v2_0_dec_ring_get_wptr - get write pointer 396 * 397 * @ring: amdgpu_ring pointer 398 * 399 * Returns the current hardware write pointer 400 */ 401 static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 402 { 403 struct amdgpu_device *adev = ring->adev; 404 405 if (ring->use_doorbell) 406 return *ring->wptr_cpu_addr; 407 else 408 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 409 } 410 411 /** 412 * jpeg_v2_0_dec_ring_set_wptr - set write pointer 413 * 414 * @ring: amdgpu_ring pointer 415 * 416 * Commits the write pointer to the hardware 417 */ 418 static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 419 { 420 struct amdgpu_device *adev = ring->adev; 421 422 if (ring->use_doorbell) { 423 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 424 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 425 } else { 426 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 427 } 428 } 429 430 /** 431 * jpeg_v2_0_dec_ring_insert_start - insert a start command 432 * 433 * @ring: amdgpu_ring pointer 434 * 435 * Write a start command to the ring. 436 */ 437 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 438 { 439 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 440 0, 0, PACKETJ_TYPE0)); 441 amdgpu_ring_write(ring, 0x68e04); 442 443 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 444 0, 0, PACKETJ_TYPE0)); 445 amdgpu_ring_write(ring, 0x80010000); 446 } 447 448 /** 449 * jpeg_v2_0_dec_ring_insert_end - insert a end command 450 * 451 * @ring: amdgpu_ring pointer 452 * 453 * Write a end command to the ring. 454 */ 455 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) 456 { 457 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 458 0, 0, PACKETJ_TYPE0)); 459 amdgpu_ring_write(ring, 0x68e04); 460 461 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 462 0, 0, PACKETJ_TYPE0)); 463 amdgpu_ring_write(ring, 0x00010000); 464 } 465 466 /** 467 * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command 468 * 469 * @ring: amdgpu_ring pointer 470 * @addr: address 471 * @seq: sequence number 472 * @flags: fence related flags 473 * 474 * Write a fence and a trap command to the ring. 475 */ 476 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 477 unsigned flags) 478 { 479 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 480 481 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 482 0, 0, PACKETJ_TYPE0)); 483 amdgpu_ring_write(ring, seq); 484 485 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 486 0, 0, PACKETJ_TYPE0)); 487 amdgpu_ring_write(ring, seq); 488 489 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 490 0, 0, PACKETJ_TYPE0)); 491 amdgpu_ring_write(ring, lower_32_bits(addr)); 492 493 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 494 0, 0, PACKETJ_TYPE0)); 495 amdgpu_ring_write(ring, upper_32_bits(addr)); 496 497 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 498 0, 0, PACKETJ_TYPE0)); 499 amdgpu_ring_write(ring, 0x8); 500 501 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 502 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 503 amdgpu_ring_write(ring, 0); 504 505 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 506 0, 0, PACKETJ_TYPE0)); 507 amdgpu_ring_write(ring, 0x3fbc); 508 509 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 510 0, 0, PACKETJ_TYPE0)); 511 amdgpu_ring_write(ring, 0x1); 512 513 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 514 amdgpu_ring_write(ring, 0); 515 } 516 517 /** 518 * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer 519 * 520 * @ring: amdgpu_ring pointer 521 * @job: job to retrieve vmid from 522 * @ib: indirect buffer to execute 523 * @flags: unused 524 * 525 * Write ring commands to execute the indirect buffer. 526 */ 527 void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 528 struct amdgpu_job *job, 529 struct amdgpu_ib *ib, 530 uint32_t flags) 531 { 532 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 533 534 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET, 535 0, 0, PACKETJ_TYPE0)); 536 amdgpu_ring_write(ring, (vmid << JPEG_IH_CTRL__IH_VMID__SHIFT)); 537 538 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 539 0, 0, PACKETJ_TYPE0)); 540 541 if (ring->funcs->parse_cs) 542 amdgpu_ring_write(ring, 0); 543 else 544 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 545 546 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 547 0, 0, PACKETJ_TYPE0)); 548 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 549 550 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 551 0, 0, PACKETJ_TYPE0)); 552 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 553 554 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 555 0, 0, PACKETJ_TYPE0)); 556 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 557 558 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 559 0, 0, PACKETJ_TYPE0)); 560 amdgpu_ring_write(ring, ib->length_dw); 561 562 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 563 0, 0, PACKETJ_TYPE0)); 564 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 565 566 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 567 0, 0, PACKETJ_TYPE0)); 568 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 569 570 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 571 amdgpu_ring_write(ring, 0); 572 573 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 574 0, 0, PACKETJ_TYPE0)); 575 amdgpu_ring_write(ring, 0x01400200); 576 577 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 578 0, 0, PACKETJ_TYPE0)); 579 amdgpu_ring_write(ring, 0x2); 580 581 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET, 582 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 583 amdgpu_ring_write(ring, 0x2); 584 } 585 586 void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 587 uint32_t val, uint32_t mask) 588 { 589 uint32_t reg_offset = (reg << 2); 590 591 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 592 0, 0, PACKETJ_TYPE0)); 593 amdgpu_ring_write(ring, 0x01400200); 594 595 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 596 0, 0, PACKETJ_TYPE0)); 597 amdgpu_ring_write(ring, val); 598 599 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 600 0, 0, PACKETJ_TYPE0)); 601 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 602 amdgpu_ring_write(ring, 0); 603 amdgpu_ring_write(ring, 604 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 605 } else { 606 amdgpu_ring_write(ring, reg_offset); 607 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 608 0, 0, PACKETJ_TYPE3)); 609 } 610 amdgpu_ring_write(ring, mask); 611 } 612 613 void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 614 unsigned vmid, uint64_t pd_addr) 615 { 616 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 617 uint32_t data0, data1, mask; 618 619 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 620 621 /* wait for register write */ 622 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 623 data1 = lower_32_bits(pd_addr); 624 mask = 0xffffffff; 625 jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 626 } 627 628 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 629 { 630 uint32_t reg_offset = (reg << 2); 631 632 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 633 0, 0, PACKETJ_TYPE0)); 634 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 635 amdgpu_ring_write(ring, 0); 636 amdgpu_ring_write(ring, 637 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 638 } else { 639 amdgpu_ring_write(ring, reg_offset); 640 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 641 0, 0, PACKETJ_TYPE0)); 642 } 643 amdgpu_ring_write(ring, val); 644 } 645 646 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) 647 { 648 int i; 649 650 WARN_ON(ring->wptr % 2 || count % 2); 651 652 for (i = 0; i < count / 2; i++) { 653 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 654 amdgpu_ring_write(ring, 0); 655 } 656 } 657 658 static bool jpeg_v2_0_is_idle(void *handle) 659 { 660 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 661 662 return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) & 663 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 664 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 665 } 666 667 static int jpeg_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 668 { 669 struct amdgpu_device *adev = ip_block->adev; 670 int ret; 671 672 ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 673 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 674 675 return ret; 676 } 677 678 static int jpeg_v2_0_set_clockgating_state(void *handle, 679 enum amd_clockgating_state state) 680 { 681 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 682 bool enable = (state == AMD_CG_STATE_GATE); 683 684 if (enable) { 685 if (!jpeg_v2_0_is_idle(handle)) 686 return -EBUSY; 687 jpeg_v2_0_enable_clock_gating(adev); 688 } else { 689 jpeg_v2_0_disable_clock_gating(adev); 690 } 691 692 return 0; 693 } 694 695 static int jpeg_v2_0_set_powergating_state(void *handle, 696 enum amd_powergating_state state) 697 { 698 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 699 int ret; 700 701 if (state == adev->jpeg.cur_state) 702 return 0; 703 704 if (state == AMD_PG_STATE_GATE) 705 ret = jpeg_v2_0_stop(adev); 706 else 707 ret = jpeg_v2_0_start(adev); 708 709 if (!ret) 710 adev->jpeg.cur_state = state; 711 712 return ret; 713 } 714 715 static int jpeg_v2_0_set_interrupt_state(struct amdgpu_device *adev, 716 struct amdgpu_irq_src *source, 717 unsigned type, 718 enum amdgpu_interrupt_state state) 719 { 720 return 0; 721 } 722 723 static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev, 724 struct amdgpu_irq_src *source, 725 struct amdgpu_iv_entry *entry) 726 { 727 DRM_DEBUG("IH: JPEG TRAP\n"); 728 729 switch (entry->src_id) { 730 case VCN_2_0__SRCID__JPEG_DECODE: 731 amdgpu_fence_process(adev->jpeg.inst->ring_dec); 732 break; 733 default: 734 DRM_ERROR("Unhandled interrupt: %d %d\n", 735 entry->src_id, entry->src_data[0]); 736 break; 737 } 738 739 return 0; 740 } 741 742 static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = { 743 .name = "jpeg_v2_0", 744 .early_init = jpeg_v2_0_early_init, 745 .sw_init = jpeg_v2_0_sw_init, 746 .sw_fini = jpeg_v2_0_sw_fini, 747 .hw_init = jpeg_v2_0_hw_init, 748 .hw_fini = jpeg_v2_0_hw_fini, 749 .suspend = jpeg_v2_0_suspend, 750 .resume = jpeg_v2_0_resume, 751 .is_idle = jpeg_v2_0_is_idle, 752 .wait_for_idle = jpeg_v2_0_wait_for_idle, 753 .set_clockgating_state = jpeg_v2_0_set_clockgating_state, 754 .set_powergating_state = jpeg_v2_0_set_powergating_state, 755 }; 756 757 static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = { 758 .type = AMDGPU_RING_TYPE_VCN_JPEG, 759 .align_mask = 0xf, 760 .get_rptr = jpeg_v2_0_dec_ring_get_rptr, 761 .get_wptr = jpeg_v2_0_dec_ring_get_wptr, 762 .set_wptr = jpeg_v2_0_dec_ring_set_wptr, 763 .parse_cs = jpeg_v2_dec_ring_parse_cs, 764 .emit_frame_size = 765 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 766 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 767 8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */ 768 18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */ 769 8 + 16, 770 .emit_ib_size = 24, /* jpeg_v2_0_dec_ring_emit_ib */ 771 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 772 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 773 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 774 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 775 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 776 .insert_nop = jpeg_v2_0_dec_ring_nop, 777 .insert_start = jpeg_v2_0_dec_ring_insert_start, 778 .insert_end = jpeg_v2_0_dec_ring_insert_end, 779 .pad_ib = amdgpu_ring_generic_pad_ib, 780 .begin_use = amdgpu_jpeg_ring_begin_use, 781 .end_use = amdgpu_jpeg_ring_end_use, 782 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 783 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 784 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 785 }; 786 787 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev) 788 { 789 adev->jpeg.inst->ring_dec->funcs = &jpeg_v2_0_dec_ring_vm_funcs; 790 } 791 792 static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = { 793 .set = jpeg_v2_0_set_interrupt_state, 794 .process = jpeg_v2_0_process_interrupt, 795 }; 796 797 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev) 798 { 799 adev->jpeg.inst->irq.num_types = 1; 800 adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs; 801 } 802 803 const struct amdgpu_ip_block_version jpeg_v2_0_ip_block = { 804 .type = AMD_IP_BLOCK_TYPE_JPEG, 805 .major = 2, 806 .minor = 0, 807 .rev = 0, 808 .funcs = &jpeg_v2_0_ip_funcs, 809 }; 810 811 /** 812 * jpeg_v2_dec_ring_parse_cs - command submission parser 813 * 814 * @parser: Command submission parser context 815 * @job: the job to parse 816 * @ib: the IB to parse 817 * 818 * Parse the command stream, return -EINVAL for invalid packet, 819 * 0 otherwise 820 */ 821 int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser, 822 struct amdgpu_job *job, 823 struct amdgpu_ib *ib) 824 { 825 u32 i, reg, res, cond, type; 826 struct amdgpu_device *adev = parser->adev; 827 828 for (i = 0; i < ib->length_dw ; i += 2) { 829 reg = CP_PACKETJ_GET_REG(ib->ptr[i]); 830 res = CP_PACKETJ_GET_RES(ib->ptr[i]); 831 cond = CP_PACKETJ_GET_COND(ib->ptr[i]); 832 type = CP_PACKETJ_GET_TYPE(ib->ptr[i]); 833 834 if (res) /* only support 0 at the moment */ 835 return -EINVAL; 836 837 switch (type) { 838 case PACKETJ_TYPE0: 839 if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START || 840 reg > JPEG_REG_RANGE_END) { 841 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); 842 return -EINVAL; 843 } 844 break; 845 case PACKETJ_TYPE3: 846 if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START || 847 reg > JPEG_REG_RANGE_END) { 848 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); 849 return -EINVAL; 850 } 851 break; 852 case PACKETJ_TYPE6: 853 if (ib->ptr[i] == CP_PACKETJ_NOP) 854 continue; 855 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); 856 return -EINVAL; 857 default: 858 dev_err(adev->dev, "Unknown packet type %d !\n", type); 859 return -EINVAL; 860 } 861 } 862 863 return 0; 864 } 865