1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_cs.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "jpeg_v2_0.h" 31 32 #include "vcn/vcn_2_0_0_offset.h" 33 #include "vcn/vcn_2_0_0_sh_mask.h" 34 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 35 36 static const struct amdgpu_hwip_reg_entry jpeg_reg_list_2_0[] = { 37 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 38 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT), 39 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR), 40 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR), 41 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL), 42 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE), 43 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS), 44 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE), 45 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG), 46 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE), 47 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE), 48 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH), 49 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH), 50 }; 51 52 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); 53 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev); 54 static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 55 enum amd_powergating_state state); 56 57 /** 58 * jpeg_v2_0_early_init - set function pointers 59 * 60 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 61 * 62 * Set ring and irq function pointers 63 */ 64 static int jpeg_v2_0_early_init(struct amdgpu_ip_block *ip_block) 65 { 66 struct amdgpu_device *adev = ip_block->adev; 67 68 adev->jpeg.num_jpeg_inst = 1; 69 adev->jpeg.num_jpeg_rings = 1; 70 71 jpeg_v2_0_set_dec_ring_funcs(adev); 72 jpeg_v2_0_set_irq_funcs(adev); 73 74 return 0; 75 } 76 77 /** 78 * jpeg_v2_0_sw_init - sw init for JPEG block 79 * 80 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 81 * 82 * Load firmware and sw initialization 83 */ 84 static int jpeg_v2_0_sw_init(struct amdgpu_ip_block *ip_block) 85 { 86 struct amdgpu_device *adev = ip_block->adev; 87 struct amdgpu_ring *ring; 88 int r; 89 90 /* JPEG TRAP */ 91 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 92 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 93 if (r) 94 return r; 95 96 r = amdgpu_jpeg_sw_init(adev); 97 if (r) 98 return r; 99 100 r = amdgpu_jpeg_resume(adev); 101 if (r) 102 return r; 103 104 ring = adev->jpeg.inst->ring_dec; 105 ring->use_doorbell = true; 106 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 107 ring->vm_hub = AMDGPU_MMHUB0(0); 108 sprintf(ring->name, "jpeg_dec"); 109 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 110 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 111 if (r) 112 return r; 113 114 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 115 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); 116 117 r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_2_0, ARRAY_SIZE(jpeg_reg_list_2_0)); 118 if (r) 119 return r; 120 121 return 0; 122 } 123 124 /** 125 * jpeg_v2_0_sw_fini - sw fini for JPEG block 126 * 127 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 128 * 129 * JPEG suspend and free up sw allocation 130 */ 131 static int jpeg_v2_0_sw_fini(struct amdgpu_ip_block *ip_block) 132 { 133 int r; 134 struct amdgpu_device *adev = ip_block->adev; 135 136 r = amdgpu_jpeg_suspend(adev); 137 if (r) 138 return r; 139 140 r = amdgpu_jpeg_sw_fini(adev); 141 142 return r; 143 } 144 145 /** 146 * jpeg_v2_0_hw_init - start and test JPEG block 147 * 148 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 149 * 150 */ 151 static int jpeg_v2_0_hw_init(struct amdgpu_ip_block *ip_block) 152 { 153 struct amdgpu_device *adev = ip_block->adev; 154 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 155 156 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 157 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 158 159 return amdgpu_ring_test_helper(ring); 160 } 161 162 /** 163 * jpeg_v2_0_hw_fini - stop the hardware block 164 * 165 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 166 * 167 * Stop the JPEG block, mark ring as not ready any more 168 */ 169 static int jpeg_v2_0_hw_fini(struct amdgpu_ip_block *ip_block) 170 { 171 struct amdgpu_device *adev = ip_block->adev; 172 173 cancel_delayed_work_sync(&adev->jpeg.idle_work); 174 175 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 176 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS)) 177 jpeg_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 178 179 return 0; 180 } 181 182 /** 183 * jpeg_v2_0_suspend - suspend JPEG block 184 * 185 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 186 * 187 * HW fini and suspend JPEG block 188 */ 189 static int jpeg_v2_0_suspend(struct amdgpu_ip_block *ip_block) 190 { 191 int r; 192 193 r = jpeg_v2_0_hw_fini(ip_block); 194 if (r) 195 return r; 196 197 r = amdgpu_jpeg_suspend(ip_block->adev); 198 199 return r; 200 } 201 202 /** 203 * jpeg_v2_0_resume - resume JPEG block 204 * 205 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 206 * 207 * Resume firmware and hw init JPEG block 208 */ 209 static int jpeg_v2_0_resume(struct amdgpu_ip_block *ip_block) 210 { 211 int r; 212 213 r = amdgpu_jpeg_resume(ip_block->adev); 214 if (r) 215 return r; 216 217 r = jpeg_v2_0_hw_init(ip_block); 218 219 return r; 220 } 221 222 static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev) 223 { 224 uint32_t data; 225 int r = 0; 226 227 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 228 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 229 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 230 231 r = SOC15_WAIT_ON_RREG(JPEG, 0, 232 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 233 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 234 235 if (r) { 236 DRM_ERROR("amdgpu: JPEG disable power gating failed\n"); 237 return r; 238 } 239 } 240 241 /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */ 242 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1; 243 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); 244 245 return 0; 246 } 247 248 static int jpeg_v2_0_enable_power_gating(struct amdgpu_device *adev) 249 { 250 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 251 uint32_t data; 252 int r = 0; 253 254 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)); 255 data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK; 256 data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF; 257 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); 258 259 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 260 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 261 262 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, 263 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 264 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 265 266 if (r) { 267 DRM_ERROR("amdgpu: JPEG enable power gating failed\n"); 268 return r; 269 } 270 } 271 272 return 0; 273 } 274 275 static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device *adev) 276 { 277 uint32_t data; 278 279 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 280 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 281 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 282 else 283 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 284 285 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 286 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 287 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 288 289 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 290 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 291 | JPEG_CGC_GATE__JPEG2_DEC_MASK 292 | JPEG_CGC_GATE__JPEG_ENC_MASK 293 | JPEG_CGC_GATE__JMCIF_MASK 294 | JPEG_CGC_GATE__JRBBM_MASK); 295 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 296 } 297 298 static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device *adev) 299 { 300 uint32_t data; 301 302 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 303 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 304 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 305 else 306 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 307 308 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 309 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 310 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 311 312 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 313 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 314 |JPEG_CGC_GATE__JPEG2_DEC_MASK 315 |JPEG_CGC_GATE__JPEG_ENC_MASK 316 |JPEG_CGC_GATE__JMCIF_MASK 317 |JPEG_CGC_GATE__JRBBM_MASK); 318 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 319 } 320 321 /** 322 * jpeg_v2_0_start - start JPEG block 323 * 324 * @adev: amdgpu_device pointer 325 * 326 * Setup and start the JPEG block 327 */ 328 static int jpeg_v2_0_start(struct amdgpu_device *adev) 329 { 330 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 331 int r; 332 333 if (adev->pm.dpm_enabled) 334 amdgpu_dpm_enable_jpeg(adev, true); 335 336 /* disable power gating */ 337 r = jpeg_v2_0_disable_power_gating(adev); 338 if (r) 339 return r; 340 341 /* JPEG disable CGC */ 342 jpeg_v2_0_disable_clock_gating(adev); 343 344 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 345 346 /* enable JMI channel */ 347 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0, 348 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 349 350 /* enable System Interrupt for JRBC */ 351 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN), 352 JPEG_SYS_INT_EN__DJRBC_MASK, 353 ~JPEG_SYS_INT_EN__DJRBC_MASK); 354 355 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 356 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 357 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 358 lower_32_bits(ring->gpu_addr)); 359 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 360 upper_32_bits(ring->gpu_addr)); 361 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); 362 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); 363 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); 364 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); 365 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 366 367 return 0; 368 } 369 370 /** 371 * jpeg_v2_0_stop - stop JPEG block 372 * 373 * @adev: amdgpu_device pointer 374 * 375 * stop the JPEG block 376 */ 377 static int jpeg_v2_0_stop(struct amdgpu_device *adev) 378 { 379 int r; 380 381 /* reset JMI */ 382 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 383 UVD_JMI_CNTL__SOFT_RESET_MASK, 384 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 385 386 /* enable JPEG CGC */ 387 jpeg_v2_0_enable_clock_gating(adev); 388 389 /* enable power gating */ 390 r = jpeg_v2_0_enable_power_gating(adev); 391 if (r) 392 return r; 393 394 if (adev->pm.dpm_enabled) 395 amdgpu_dpm_enable_jpeg(adev, false); 396 397 return 0; 398 } 399 400 /** 401 * jpeg_v2_0_dec_ring_get_rptr - get read pointer 402 * 403 * @ring: amdgpu_ring pointer 404 * 405 * Returns the current hardware read pointer 406 */ 407 static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 408 { 409 struct amdgpu_device *adev = ring->adev; 410 411 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); 412 } 413 414 /** 415 * jpeg_v2_0_dec_ring_get_wptr - get write pointer 416 * 417 * @ring: amdgpu_ring pointer 418 * 419 * Returns the current hardware write pointer 420 */ 421 static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 422 { 423 struct amdgpu_device *adev = ring->adev; 424 425 if (ring->use_doorbell) 426 return *ring->wptr_cpu_addr; 427 else 428 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 429 } 430 431 /** 432 * jpeg_v2_0_dec_ring_set_wptr - set write pointer 433 * 434 * @ring: amdgpu_ring pointer 435 * 436 * Commits the write pointer to the hardware 437 */ 438 static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 439 { 440 struct amdgpu_device *adev = ring->adev; 441 442 if (ring->use_doorbell) { 443 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 444 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 445 } else { 446 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 447 } 448 } 449 450 /** 451 * jpeg_v2_0_dec_ring_insert_start - insert a start command 452 * 453 * @ring: amdgpu_ring pointer 454 * 455 * Write a start command to the ring. 456 */ 457 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 458 { 459 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 460 0, 0, PACKETJ_TYPE0)); 461 amdgpu_ring_write(ring, 0x68e04); 462 463 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 464 0, 0, PACKETJ_TYPE0)); 465 amdgpu_ring_write(ring, 0x80010000); 466 } 467 468 /** 469 * jpeg_v2_0_dec_ring_insert_end - insert a end command 470 * 471 * @ring: amdgpu_ring pointer 472 * 473 * Write a end command to the ring. 474 */ 475 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) 476 { 477 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 478 0, 0, PACKETJ_TYPE0)); 479 amdgpu_ring_write(ring, 0x68e04); 480 481 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 482 0, 0, PACKETJ_TYPE0)); 483 amdgpu_ring_write(ring, 0x00010000); 484 } 485 486 /** 487 * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command 488 * 489 * @ring: amdgpu_ring pointer 490 * @addr: address 491 * @seq: sequence number 492 * @flags: fence related flags 493 * 494 * Write a fence and a trap command to the ring. 495 */ 496 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 497 unsigned flags) 498 { 499 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 500 501 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 502 0, 0, PACKETJ_TYPE0)); 503 amdgpu_ring_write(ring, seq); 504 505 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 506 0, 0, PACKETJ_TYPE0)); 507 amdgpu_ring_write(ring, seq); 508 509 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 510 0, 0, PACKETJ_TYPE0)); 511 amdgpu_ring_write(ring, lower_32_bits(addr)); 512 513 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 514 0, 0, PACKETJ_TYPE0)); 515 amdgpu_ring_write(ring, upper_32_bits(addr)); 516 517 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 518 0, 0, PACKETJ_TYPE0)); 519 amdgpu_ring_write(ring, 0x8); 520 521 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 522 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 523 amdgpu_ring_write(ring, 0); 524 525 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 526 0, 0, PACKETJ_TYPE0)); 527 amdgpu_ring_write(ring, 0x3fbc); 528 529 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 530 0, 0, PACKETJ_TYPE0)); 531 amdgpu_ring_write(ring, 0x1); 532 533 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 534 amdgpu_ring_write(ring, 0); 535 } 536 537 /** 538 * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer 539 * 540 * @ring: amdgpu_ring pointer 541 * @job: job to retrieve vmid from 542 * @ib: indirect buffer to execute 543 * @flags: unused 544 * 545 * Write ring commands to execute the indirect buffer. 546 */ 547 void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 548 struct amdgpu_job *job, 549 struct amdgpu_ib *ib, 550 uint32_t flags) 551 { 552 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 553 554 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET, 555 0, 0, PACKETJ_TYPE0)); 556 amdgpu_ring_write(ring, (vmid << JPEG_IH_CTRL__IH_VMID__SHIFT)); 557 558 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 559 0, 0, PACKETJ_TYPE0)); 560 561 if (ring->funcs->parse_cs) 562 amdgpu_ring_write(ring, 0); 563 else 564 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 565 566 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 567 0, 0, PACKETJ_TYPE0)); 568 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 569 570 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 571 0, 0, PACKETJ_TYPE0)); 572 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 573 574 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 575 0, 0, PACKETJ_TYPE0)); 576 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 577 578 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 579 0, 0, PACKETJ_TYPE0)); 580 amdgpu_ring_write(ring, ib->length_dw); 581 582 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 583 0, 0, PACKETJ_TYPE0)); 584 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 585 586 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 587 0, 0, PACKETJ_TYPE0)); 588 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 589 590 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 591 amdgpu_ring_write(ring, 0); 592 593 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 594 0, 0, PACKETJ_TYPE0)); 595 amdgpu_ring_write(ring, 0x01400200); 596 597 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 598 0, 0, PACKETJ_TYPE0)); 599 amdgpu_ring_write(ring, 0x2); 600 601 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET, 602 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 603 amdgpu_ring_write(ring, 0x2); 604 } 605 606 void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 607 uint32_t val, uint32_t mask) 608 { 609 uint32_t reg_offset = (reg << 2); 610 611 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 612 0, 0, PACKETJ_TYPE0)); 613 amdgpu_ring_write(ring, 0x01400200); 614 615 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 616 0, 0, PACKETJ_TYPE0)); 617 amdgpu_ring_write(ring, val); 618 619 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 620 0, 0, PACKETJ_TYPE0)); 621 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 622 amdgpu_ring_write(ring, 0); 623 amdgpu_ring_write(ring, 624 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 625 } else { 626 amdgpu_ring_write(ring, reg_offset); 627 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 628 0, 0, PACKETJ_TYPE3)); 629 } 630 amdgpu_ring_write(ring, mask); 631 } 632 633 void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 634 unsigned vmid, uint64_t pd_addr) 635 { 636 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 637 uint32_t data0, data1, mask; 638 639 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 640 641 /* wait for register write */ 642 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 643 data1 = lower_32_bits(pd_addr); 644 mask = 0xffffffff; 645 jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 646 } 647 648 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 649 { 650 uint32_t reg_offset = (reg << 2); 651 652 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 653 0, 0, PACKETJ_TYPE0)); 654 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 655 amdgpu_ring_write(ring, 0); 656 amdgpu_ring_write(ring, 657 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 658 } else { 659 amdgpu_ring_write(ring, reg_offset); 660 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 661 0, 0, PACKETJ_TYPE0)); 662 } 663 amdgpu_ring_write(ring, val); 664 } 665 666 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) 667 { 668 int i; 669 670 WARN_ON(ring->wptr % 2 || count % 2); 671 672 for (i = 0; i < count / 2; i++) { 673 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 674 amdgpu_ring_write(ring, 0); 675 } 676 } 677 678 static bool jpeg_v2_0_is_idle(void *handle) 679 { 680 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 681 682 return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) & 683 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 684 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 685 } 686 687 static int jpeg_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 688 { 689 struct amdgpu_device *adev = ip_block->adev; 690 int ret; 691 692 ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 693 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 694 695 return ret; 696 } 697 698 static int jpeg_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 699 enum amd_clockgating_state state) 700 { 701 struct amdgpu_device *adev = ip_block->adev; 702 bool enable = (state == AMD_CG_STATE_GATE); 703 704 if (enable) { 705 if (!jpeg_v2_0_is_idle(adev)) 706 return -EBUSY; 707 jpeg_v2_0_enable_clock_gating(adev); 708 } else { 709 jpeg_v2_0_disable_clock_gating(adev); 710 } 711 712 return 0; 713 } 714 715 static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 716 enum amd_powergating_state state) 717 { 718 struct amdgpu_device *adev = ip_block->adev; 719 int ret; 720 721 if (state == adev->jpeg.cur_state) 722 return 0; 723 724 if (state == AMD_PG_STATE_GATE) 725 ret = jpeg_v2_0_stop(adev); 726 else 727 ret = jpeg_v2_0_start(adev); 728 729 if (!ret) 730 adev->jpeg.cur_state = state; 731 732 return ret; 733 } 734 735 static int jpeg_v2_0_set_interrupt_state(struct amdgpu_device *adev, 736 struct amdgpu_irq_src *source, 737 unsigned type, 738 enum amdgpu_interrupt_state state) 739 { 740 return 0; 741 } 742 743 static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev, 744 struct amdgpu_irq_src *source, 745 struct amdgpu_iv_entry *entry) 746 { 747 DRM_DEBUG("IH: JPEG TRAP\n"); 748 749 switch (entry->src_id) { 750 case VCN_2_0__SRCID__JPEG_DECODE: 751 amdgpu_fence_process(adev->jpeg.inst->ring_dec); 752 break; 753 default: 754 DRM_ERROR("Unhandled interrupt: %d %d\n", 755 entry->src_id, entry->src_data[0]); 756 break; 757 } 758 759 return 0; 760 } 761 762 static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = { 763 .name = "jpeg_v2_0", 764 .early_init = jpeg_v2_0_early_init, 765 .sw_init = jpeg_v2_0_sw_init, 766 .sw_fini = jpeg_v2_0_sw_fini, 767 .hw_init = jpeg_v2_0_hw_init, 768 .hw_fini = jpeg_v2_0_hw_fini, 769 .suspend = jpeg_v2_0_suspend, 770 .resume = jpeg_v2_0_resume, 771 .is_idle = jpeg_v2_0_is_idle, 772 .wait_for_idle = jpeg_v2_0_wait_for_idle, 773 .set_clockgating_state = jpeg_v2_0_set_clockgating_state, 774 .set_powergating_state = jpeg_v2_0_set_powergating_state, 775 .dump_ip_state = amdgpu_jpeg_dump_ip_state, 776 .print_ip_state = amdgpu_jpeg_print_ip_state, 777 }; 778 779 static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = { 780 .type = AMDGPU_RING_TYPE_VCN_JPEG, 781 .align_mask = 0xf, 782 .get_rptr = jpeg_v2_0_dec_ring_get_rptr, 783 .get_wptr = jpeg_v2_0_dec_ring_get_wptr, 784 .set_wptr = jpeg_v2_0_dec_ring_set_wptr, 785 .parse_cs = jpeg_v2_dec_ring_parse_cs, 786 .emit_frame_size = 787 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 788 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 789 8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */ 790 18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */ 791 8 + 16, 792 .emit_ib_size = 24, /* jpeg_v2_0_dec_ring_emit_ib */ 793 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 794 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 795 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 796 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 797 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 798 .insert_nop = jpeg_v2_0_dec_ring_nop, 799 .insert_start = jpeg_v2_0_dec_ring_insert_start, 800 .insert_end = jpeg_v2_0_dec_ring_insert_end, 801 .pad_ib = amdgpu_ring_generic_pad_ib, 802 .begin_use = amdgpu_jpeg_ring_begin_use, 803 .end_use = amdgpu_jpeg_ring_end_use, 804 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 805 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 806 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 807 }; 808 809 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev) 810 { 811 adev->jpeg.inst->ring_dec->funcs = &jpeg_v2_0_dec_ring_vm_funcs; 812 } 813 814 static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = { 815 .set = jpeg_v2_0_set_interrupt_state, 816 .process = jpeg_v2_0_process_interrupt, 817 }; 818 819 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev) 820 { 821 adev->jpeg.inst->irq.num_types = 1; 822 adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs; 823 } 824 825 const struct amdgpu_ip_block_version jpeg_v2_0_ip_block = { 826 .type = AMD_IP_BLOCK_TYPE_JPEG, 827 .major = 2, 828 .minor = 0, 829 .rev = 0, 830 .funcs = &jpeg_v2_0_ip_funcs, 831 }; 832 833 /** 834 * jpeg_v2_dec_ring_parse_cs - command submission parser 835 * 836 * @parser: Command submission parser context 837 * @job: the job to parse 838 * @ib: the IB to parse 839 * 840 * Parse the command stream, return -EINVAL for invalid packet, 841 * 0 otherwise 842 */ 843 int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser, 844 struct amdgpu_job *job, 845 struct amdgpu_ib *ib) 846 { 847 u32 i, reg, res, cond, type; 848 struct amdgpu_device *adev = parser->adev; 849 850 for (i = 0; i < ib->length_dw ; i += 2) { 851 reg = CP_PACKETJ_GET_REG(ib->ptr[i]); 852 res = CP_PACKETJ_GET_RES(ib->ptr[i]); 853 cond = CP_PACKETJ_GET_COND(ib->ptr[i]); 854 type = CP_PACKETJ_GET_TYPE(ib->ptr[i]); 855 856 if (res) /* only support 0 at the moment */ 857 return -EINVAL; 858 859 switch (type) { 860 case PACKETJ_TYPE0: 861 if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START || 862 reg > JPEG_REG_RANGE_END) { 863 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); 864 return -EINVAL; 865 } 866 break; 867 case PACKETJ_TYPE3: 868 if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START || 869 reg > JPEG_REG_RANGE_END) { 870 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); 871 return -EINVAL; 872 } 873 break; 874 case PACKETJ_TYPE6: 875 if (ib->ptr[i] == CP_PACKETJ_NOP) 876 continue; 877 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); 878 return -EINVAL; 879 default: 880 dev_err(adev->dev, "Unknown packet type %d !\n", type); 881 return -EINVAL; 882 } 883 } 884 885 return 0; 886 } 887