1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_jpeg.h" 26 #include "amdgpu_cs.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "jpeg_v2_0.h" 31 32 #include "vcn/vcn_2_0_0_offset.h" 33 #include "vcn/vcn_2_0_0_sh_mask.h" 34 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 35 36 static const struct amdgpu_hwip_reg_entry jpeg_reg_list_2_0[] = { 37 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 38 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT), 39 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR), 40 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR), 41 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL), 42 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE), 43 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS), 44 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE), 45 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG), 46 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE), 47 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE), 48 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH), 49 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH), 50 }; 51 52 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); 53 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev); 54 static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 55 enum amd_powergating_state state); 56 57 /** 58 * jpeg_v2_0_early_init - set function pointers 59 * 60 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 61 * 62 * Set ring and irq function pointers 63 */ 64 static int jpeg_v2_0_early_init(struct amdgpu_ip_block *ip_block) 65 { 66 struct amdgpu_device *adev = ip_block->adev; 67 68 adev->jpeg.num_jpeg_inst = 1; 69 adev->jpeg.num_jpeg_rings = 1; 70 71 jpeg_v2_0_set_dec_ring_funcs(adev); 72 jpeg_v2_0_set_irq_funcs(adev); 73 74 return 0; 75 } 76 77 /** 78 * jpeg_v2_0_sw_init - sw init for JPEG block 79 * 80 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 81 * 82 * Load firmware and sw initialization 83 */ 84 static int jpeg_v2_0_sw_init(struct amdgpu_ip_block *ip_block) 85 { 86 struct amdgpu_device *adev = ip_block->adev; 87 struct amdgpu_ring *ring; 88 int r; 89 90 /* JPEG TRAP */ 91 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 92 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); 93 if (r) 94 return r; 95 96 r = amdgpu_jpeg_sw_init(adev); 97 if (r) 98 return r; 99 100 r = amdgpu_jpeg_resume(adev); 101 if (r) 102 return r; 103 104 ring = adev->jpeg.inst->ring_dec; 105 ring->use_doorbell = true; 106 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 107 ring->vm_hub = AMDGPU_MMHUB0(0); 108 sprintf(ring->name, "jpeg_dec"); 109 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 110 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 111 if (r) 112 return r; 113 114 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET; 115 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH); 116 117 r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_2_0, ARRAY_SIZE(jpeg_reg_list_2_0)); 118 if (r) 119 return r; 120 121 adev->jpeg.supported_reset = 122 amdgpu_get_soft_full_reset_mask(adev->jpeg.inst[0].ring_dec); 123 if (!amdgpu_sriov_vf(adev)) 124 adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 125 r = amdgpu_jpeg_sysfs_reset_mask_init(adev); 126 127 return r; 128 } 129 130 /** 131 * jpeg_v2_0_sw_fini - sw fini for JPEG block 132 * 133 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 134 * 135 * JPEG suspend and free up sw allocation 136 */ 137 static int jpeg_v2_0_sw_fini(struct amdgpu_ip_block *ip_block) 138 { 139 int r; 140 struct amdgpu_device *adev = ip_block->adev; 141 142 r = amdgpu_jpeg_suspend(adev); 143 if (r) 144 return r; 145 146 amdgpu_jpeg_sysfs_reset_mask_fini(adev); 147 148 r = amdgpu_jpeg_sw_fini(adev); 149 150 return r; 151 } 152 153 /** 154 * jpeg_v2_0_hw_init - start and test JPEG block 155 * 156 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 157 * 158 */ 159 static int jpeg_v2_0_hw_init(struct amdgpu_ip_block *ip_block) 160 { 161 struct amdgpu_device *adev = ip_block->adev; 162 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 163 164 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 165 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); 166 167 return amdgpu_ring_test_helper(ring); 168 } 169 170 /** 171 * jpeg_v2_0_hw_fini - stop the hardware block 172 * 173 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 174 * 175 * Stop the JPEG block, mark ring as not ready any more 176 */ 177 static int jpeg_v2_0_hw_fini(struct amdgpu_ip_block *ip_block) 178 { 179 struct amdgpu_device *adev = ip_block->adev; 180 181 cancel_delayed_work_sync(&adev->jpeg.idle_work); 182 183 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && 184 RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS)) 185 jpeg_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 186 187 return 0; 188 } 189 190 /** 191 * jpeg_v2_0_suspend - suspend JPEG block 192 * 193 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 194 * 195 * HW fini and suspend JPEG block 196 */ 197 static int jpeg_v2_0_suspend(struct amdgpu_ip_block *ip_block) 198 { 199 int r; 200 201 r = jpeg_v2_0_hw_fini(ip_block); 202 if (r) 203 return r; 204 205 r = amdgpu_jpeg_suspend(ip_block->adev); 206 207 return r; 208 } 209 210 /** 211 * jpeg_v2_0_resume - resume JPEG block 212 * 213 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 214 * 215 * Resume firmware and hw init JPEG block 216 */ 217 static int jpeg_v2_0_resume(struct amdgpu_ip_block *ip_block) 218 { 219 int r; 220 221 r = amdgpu_jpeg_resume(ip_block->adev); 222 if (r) 223 return r; 224 225 r = jpeg_v2_0_hw_init(ip_block); 226 227 return r; 228 } 229 230 static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev) 231 { 232 uint32_t data; 233 int r = 0; 234 235 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 236 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 237 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 238 239 r = SOC15_WAIT_ON_RREG(JPEG, 0, 240 mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON, 241 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 242 243 if (r) { 244 DRM_ERROR("amdgpu: JPEG disable power gating failed\n"); 245 return r; 246 } 247 } 248 249 /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */ 250 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1; 251 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); 252 253 return 0; 254 } 255 256 static int jpeg_v2_0_enable_power_gating(struct amdgpu_device *adev) 257 { 258 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { 259 uint32_t data; 260 int r = 0; 261 262 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)); 263 data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK; 264 data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF; 265 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data); 266 267 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT; 268 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data); 269 270 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, 271 (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT), 272 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); 273 274 if (r) { 275 DRM_ERROR("amdgpu: JPEG enable power gating failed\n"); 276 return r; 277 } 278 } 279 280 return 0; 281 } 282 283 static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device *adev) 284 { 285 uint32_t data; 286 287 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 288 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 289 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 290 else 291 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 292 293 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 294 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 295 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 296 297 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 298 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK 299 | JPEG_CGC_GATE__JPEG2_DEC_MASK 300 | JPEG_CGC_GATE__JPEG_ENC_MASK 301 | JPEG_CGC_GATE__JMCIF_MASK 302 | JPEG_CGC_GATE__JRBBM_MASK); 303 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 304 } 305 306 static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device *adev) 307 { 308 uint32_t data; 309 310 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL); 311 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) 312 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 313 else 314 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 315 316 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 317 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 318 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); 319 320 data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE); 321 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK 322 |JPEG_CGC_GATE__JPEG2_DEC_MASK 323 |JPEG_CGC_GATE__JPEG_ENC_MASK 324 |JPEG_CGC_GATE__JMCIF_MASK 325 |JPEG_CGC_GATE__JRBBM_MASK); 326 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); 327 } 328 329 /** 330 * jpeg_v2_0_start - start JPEG block 331 * 332 * @adev: amdgpu_device pointer 333 * 334 * Setup and start the JPEG block 335 */ 336 static int jpeg_v2_0_start(struct amdgpu_device *adev) 337 { 338 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; 339 int r; 340 341 if (adev->pm.dpm_enabled) 342 amdgpu_dpm_enable_jpeg(adev, true); 343 344 /* disable power gating */ 345 r = jpeg_v2_0_disable_power_gating(adev); 346 if (r) 347 return r; 348 349 /* JPEG disable CGC */ 350 jpeg_v2_0_disable_clock_gating(adev); 351 352 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 353 354 /* enable JMI channel */ 355 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0, 356 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 357 358 /* enable System Interrupt for JRBC */ 359 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN), 360 JPEG_SYS_INT_EN__DJRBC_MASK, 361 ~JPEG_SYS_INT_EN__DJRBC_MASK); 362 363 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 364 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); 365 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 366 lower_32_bits(ring->gpu_addr)); 367 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 368 upper_32_bits(ring->gpu_addr)); 369 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0); 370 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0); 371 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); 372 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4); 373 ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 374 375 return 0; 376 } 377 378 /** 379 * jpeg_v2_0_stop - stop JPEG block 380 * 381 * @adev: amdgpu_device pointer 382 * 383 * stop the JPEG block 384 */ 385 static int jpeg_v2_0_stop(struct amdgpu_device *adev) 386 { 387 int r; 388 389 /* reset JMI */ 390 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 391 UVD_JMI_CNTL__SOFT_RESET_MASK, 392 ~UVD_JMI_CNTL__SOFT_RESET_MASK); 393 394 /* enable JPEG CGC */ 395 jpeg_v2_0_enable_clock_gating(adev); 396 397 /* enable power gating */ 398 r = jpeg_v2_0_enable_power_gating(adev); 399 if (r) 400 return r; 401 402 if (adev->pm.dpm_enabled) 403 amdgpu_dpm_enable_jpeg(adev, false); 404 405 return 0; 406 } 407 408 /** 409 * jpeg_v2_0_dec_ring_get_rptr - get read pointer 410 * 411 * @ring: amdgpu_ring pointer 412 * 413 * Returns the current hardware read pointer 414 */ 415 static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 416 { 417 struct amdgpu_device *adev = ring->adev; 418 419 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR); 420 } 421 422 /** 423 * jpeg_v2_0_dec_ring_get_wptr - get write pointer 424 * 425 * @ring: amdgpu_ring pointer 426 * 427 * Returns the current hardware write pointer 428 */ 429 static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 430 { 431 struct amdgpu_device *adev = ring->adev; 432 433 if (ring->use_doorbell) 434 return *ring->wptr_cpu_addr; 435 else 436 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR); 437 } 438 439 /** 440 * jpeg_v2_0_dec_ring_set_wptr - set write pointer 441 * 442 * @ring: amdgpu_ring pointer 443 * 444 * Commits the write pointer to the hardware 445 */ 446 static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 447 { 448 struct amdgpu_device *adev = ring->adev; 449 450 if (ring->use_doorbell) { 451 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 452 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 453 } else { 454 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); 455 } 456 } 457 458 /** 459 * jpeg_v2_0_dec_ring_insert_start - insert a start command 460 * 461 * @ring: amdgpu_ring pointer 462 * 463 * Write a start command to the ring. 464 */ 465 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 466 { 467 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 468 0, 0, PACKETJ_TYPE0)); 469 amdgpu_ring_write(ring, 0x68e04); 470 471 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 472 0, 0, PACKETJ_TYPE0)); 473 amdgpu_ring_write(ring, 0x80010000); 474 } 475 476 /** 477 * jpeg_v2_0_dec_ring_insert_end - insert a end command 478 * 479 * @ring: amdgpu_ring pointer 480 * 481 * Write a end command to the ring. 482 */ 483 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) 484 { 485 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 486 0, 0, PACKETJ_TYPE0)); 487 amdgpu_ring_write(ring, 0x68e04); 488 489 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 490 0, 0, PACKETJ_TYPE0)); 491 amdgpu_ring_write(ring, 0x00010000); 492 } 493 494 /** 495 * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command 496 * 497 * @ring: amdgpu_ring pointer 498 * @addr: address 499 * @seq: sequence number 500 * @flags: fence related flags 501 * 502 * Write a fence and a trap command to the ring. 503 */ 504 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 505 unsigned flags) 506 { 507 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 508 509 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET, 510 0, 0, PACKETJ_TYPE0)); 511 amdgpu_ring_write(ring, seq); 512 513 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET, 514 0, 0, PACKETJ_TYPE0)); 515 amdgpu_ring_write(ring, seq); 516 517 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET, 518 0, 0, PACKETJ_TYPE0)); 519 amdgpu_ring_write(ring, lower_32_bits(addr)); 520 521 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET, 522 0, 0, PACKETJ_TYPE0)); 523 amdgpu_ring_write(ring, upper_32_bits(addr)); 524 525 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 526 0, 0, PACKETJ_TYPE0)); 527 amdgpu_ring_write(ring, 0x8); 528 529 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET, 530 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); 531 amdgpu_ring_write(ring, 0); 532 533 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 534 0, 0, PACKETJ_TYPE0)); 535 amdgpu_ring_write(ring, 0x3fbc); 536 537 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 538 0, 0, PACKETJ_TYPE0)); 539 amdgpu_ring_write(ring, 0x1); 540 541 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); 542 amdgpu_ring_write(ring, 0); 543 } 544 545 /** 546 * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer 547 * 548 * @ring: amdgpu_ring pointer 549 * @job: job to retrieve vmid from 550 * @ib: indirect buffer to execute 551 * @flags: unused 552 * 553 * Write ring commands to execute the indirect buffer. 554 */ 555 void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 556 struct amdgpu_job *job, 557 struct amdgpu_ib *ib, 558 uint32_t flags) 559 { 560 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 561 562 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET, 563 0, 0, PACKETJ_TYPE0)); 564 amdgpu_ring_write(ring, (vmid << JPEG_IH_CTRL__IH_VMID__SHIFT)); 565 566 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 567 0, 0, PACKETJ_TYPE0)); 568 569 if (ring->funcs->parse_cs) 570 amdgpu_ring_write(ring, 0); 571 else 572 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 573 574 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 575 0, 0, PACKETJ_TYPE0)); 576 amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); 577 578 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET, 579 0, 0, PACKETJ_TYPE0)); 580 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 581 582 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET, 583 0, 0, PACKETJ_TYPE0)); 584 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 585 586 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET, 587 0, 0, PACKETJ_TYPE0)); 588 amdgpu_ring_write(ring, ib->length_dw); 589 590 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET, 591 0, 0, PACKETJ_TYPE0)); 592 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); 593 594 amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET, 595 0, 0, PACKETJ_TYPE0)); 596 amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr)); 597 598 amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2)); 599 amdgpu_ring_write(ring, 0); 600 601 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 602 0, 0, PACKETJ_TYPE0)); 603 amdgpu_ring_write(ring, 0x01400200); 604 605 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 606 0, 0, PACKETJ_TYPE0)); 607 amdgpu_ring_write(ring, 0x2); 608 609 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET, 610 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3)); 611 amdgpu_ring_write(ring, 0x2); 612 } 613 614 void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 615 uint32_t val, uint32_t mask) 616 { 617 uint32_t reg_offset = (reg << 2); 618 619 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET, 620 0, 0, PACKETJ_TYPE0)); 621 amdgpu_ring_write(ring, 0x01400200); 622 623 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET, 624 0, 0, PACKETJ_TYPE0)); 625 amdgpu_ring_write(ring, val); 626 627 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 628 0, 0, PACKETJ_TYPE0)); 629 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 630 amdgpu_ring_write(ring, 0); 631 amdgpu_ring_write(ring, 632 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); 633 } else { 634 amdgpu_ring_write(ring, reg_offset); 635 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 636 0, 0, PACKETJ_TYPE3)); 637 } 638 amdgpu_ring_write(ring, mask); 639 } 640 641 void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 642 unsigned vmid, uint64_t pd_addr) 643 { 644 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 645 uint32_t data0, data1, mask; 646 647 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 648 649 /* wait for register write */ 650 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 651 data1 = lower_32_bits(pd_addr); 652 mask = 0xffffffff; 653 jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 654 } 655 656 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 657 { 658 uint32_t reg_offset = (reg << 2); 659 660 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 661 0, 0, PACKETJ_TYPE0)); 662 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { 663 amdgpu_ring_write(ring, 0); 664 amdgpu_ring_write(ring, 665 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); 666 } else { 667 amdgpu_ring_write(ring, reg_offset); 668 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 669 0, 0, PACKETJ_TYPE0)); 670 } 671 amdgpu_ring_write(ring, val); 672 } 673 674 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count) 675 { 676 int i; 677 678 WARN_ON(ring->wptr % 2 || count % 2); 679 680 for (i = 0; i < count / 2; i++) { 681 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); 682 amdgpu_ring_write(ring, 0); 683 } 684 } 685 686 static bool jpeg_v2_0_is_idle(struct amdgpu_ip_block *ip_block) 687 { 688 struct amdgpu_device *adev = ip_block->adev; 689 690 return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) & 691 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == 692 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 693 } 694 695 static int jpeg_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 696 { 697 struct amdgpu_device *adev = ip_block->adev; 698 int ret; 699 700 ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, 701 UVD_JRBC_STATUS__RB_JOB_DONE_MASK); 702 703 return ret; 704 } 705 706 static int jpeg_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 707 enum amd_clockgating_state state) 708 { 709 struct amdgpu_device *adev = ip_block->adev; 710 bool enable = (state == AMD_CG_STATE_GATE); 711 712 if (enable) { 713 if (!jpeg_v2_0_is_idle(ip_block)) 714 return -EBUSY; 715 jpeg_v2_0_enable_clock_gating(adev); 716 } else { 717 jpeg_v2_0_disable_clock_gating(adev); 718 } 719 720 return 0; 721 } 722 723 static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 724 enum amd_powergating_state state) 725 { 726 struct amdgpu_device *adev = ip_block->adev; 727 int ret; 728 729 if (state == adev->jpeg.cur_state) 730 return 0; 731 732 if (state == AMD_PG_STATE_GATE) 733 ret = jpeg_v2_0_stop(adev); 734 else 735 ret = jpeg_v2_0_start(adev); 736 737 if (!ret) 738 adev->jpeg.cur_state = state; 739 740 return ret; 741 } 742 743 static int jpeg_v2_0_set_interrupt_state(struct amdgpu_device *adev, 744 struct amdgpu_irq_src *source, 745 unsigned type, 746 enum amdgpu_interrupt_state state) 747 { 748 return 0; 749 } 750 751 static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev, 752 struct amdgpu_irq_src *source, 753 struct amdgpu_iv_entry *entry) 754 { 755 DRM_DEBUG("IH: JPEG TRAP\n"); 756 757 switch (entry->src_id) { 758 case VCN_2_0__SRCID__JPEG_DECODE: 759 amdgpu_fence_process(adev->jpeg.inst->ring_dec); 760 break; 761 default: 762 DRM_ERROR("Unhandled interrupt: %d %d\n", 763 entry->src_id, entry->src_data[0]); 764 break; 765 } 766 767 return 0; 768 } 769 770 static int jpeg_v2_0_ring_reset(struct amdgpu_ring *ring, 771 unsigned int vmid, 772 struct amdgpu_fence *timedout_fence) 773 { 774 int r; 775 776 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 777 r = jpeg_v2_0_stop(ring->adev); 778 if (r) 779 return r; 780 r = jpeg_v2_0_start(ring->adev); 781 if (r) 782 return r; 783 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 784 } 785 786 static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = { 787 .name = "jpeg_v2_0", 788 .early_init = jpeg_v2_0_early_init, 789 .sw_init = jpeg_v2_0_sw_init, 790 .sw_fini = jpeg_v2_0_sw_fini, 791 .hw_init = jpeg_v2_0_hw_init, 792 .hw_fini = jpeg_v2_0_hw_fini, 793 .suspend = jpeg_v2_0_suspend, 794 .resume = jpeg_v2_0_resume, 795 .is_idle = jpeg_v2_0_is_idle, 796 .wait_for_idle = jpeg_v2_0_wait_for_idle, 797 .set_clockgating_state = jpeg_v2_0_set_clockgating_state, 798 .set_powergating_state = jpeg_v2_0_set_powergating_state, 799 .dump_ip_state = amdgpu_jpeg_dump_ip_state, 800 .print_ip_state = amdgpu_jpeg_print_ip_state, 801 }; 802 803 static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = { 804 .type = AMDGPU_RING_TYPE_VCN_JPEG, 805 .align_mask = 0xf, 806 .get_rptr = jpeg_v2_0_dec_ring_get_rptr, 807 .get_wptr = jpeg_v2_0_dec_ring_get_wptr, 808 .set_wptr = jpeg_v2_0_dec_ring_set_wptr, 809 .parse_cs = jpeg_v2_dec_ring_parse_cs, 810 .emit_frame_size = 811 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 812 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 813 8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */ 814 18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */ 815 8 + 16, 816 .emit_ib_size = 24, /* jpeg_v2_0_dec_ring_emit_ib */ 817 .emit_ib = jpeg_v2_0_dec_ring_emit_ib, 818 .emit_fence = jpeg_v2_0_dec_ring_emit_fence, 819 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush, 820 .test_ring = amdgpu_jpeg_dec_ring_test_ring, 821 .test_ib = amdgpu_jpeg_dec_ring_test_ib, 822 .insert_nop = jpeg_v2_0_dec_ring_nop, 823 .insert_start = jpeg_v2_0_dec_ring_insert_start, 824 .insert_end = jpeg_v2_0_dec_ring_insert_end, 825 .pad_ib = amdgpu_ring_generic_pad_ib, 826 .begin_use = amdgpu_jpeg_ring_begin_use, 827 .end_use = amdgpu_jpeg_ring_end_use, 828 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg, 829 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait, 830 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 831 .reset = jpeg_v2_0_ring_reset, 832 }; 833 834 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev) 835 { 836 adev->jpeg.inst->ring_dec->funcs = &jpeg_v2_0_dec_ring_vm_funcs; 837 } 838 839 static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = { 840 .set = jpeg_v2_0_set_interrupt_state, 841 .process = jpeg_v2_0_process_interrupt, 842 }; 843 844 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev) 845 { 846 adev->jpeg.inst->irq.num_types = 1; 847 adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs; 848 } 849 850 const struct amdgpu_ip_block_version jpeg_v2_0_ip_block = { 851 .type = AMD_IP_BLOCK_TYPE_JPEG, 852 .major = 2, 853 .minor = 0, 854 .rev = 0, 855 .funcs = &jpeg_v2_0_ip_funcs, 856 }; 857 858 /** 859 * jpeg_v2_dec_ring_parse_cs - command submission parser 860 * 861 * @parser: Command submission parser context 862 * @job: the job to parse 863 * @ib: the IB to parse 864 * 865 * Parse the command stream, return -EINVAL for invalid packet, 866 * 0 otherwise 867 */ 868 int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser, 869 struct amdgpu_job *job, 870 struct amdgpu_ib *ib) 871 { 872 u32 i, reg, res, cond, type; 873 struct amdgpu_device *adev = parser->adev; 874 875 for (i = 0; i < ib->length_dw ; i += 2) { 876 reg = CP_PACKETJ_GET_REG(ib->ptr[i]); 877 res = CP_PACKETJ_GET_RES(ib->ptr[i]); 878 cond = CP_PACKETJ_GET_COND(ib->ptr[i]); 879 type = CP_PACKETJ_GET_TYPE(ib->ptr[i]); 880 881 if (res) /* only support 0 at the moment */ 882 return -EINVAL; 883 884 switch (type) { 885 case PACKETJ_TYPE0: 886 if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START || 887 reg > JPEG_REG_RANGE_END) { 888 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); 889 return -EINVAL; 890 } 891 break; 892 case PACKETJ_TYPE3: 893 if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START || 894 reg > JPEG_REG_RANGE_END) { 895 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); 896 return -EINVAL; 897 } 898 break; 899 case PACKETJ_TYPE6: 900 if (ib->ptr[i] == CP_PACKETJ_NOP) 901 continue; 902 dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); 903 return -EINVAL; 904 default: 905 dev_err(adev->dev, "Unknown packet type %d !\n", type); 906 return -EINVAL; 907 } 908 } 909 910 return 0; 911 } 912