16ac27241SLeo Liu /*
26ac27241SLeo Liu * Copyright 2019 Advanced Micro Devices, Inc.
36ac27241SLeo Liu *
46ac27241SLeo Liu * Permission is hereby granted, free of charge, to any person obtaining a
56ac27241SLeo Liu * copy of this software and associated documentation files (the "Software"),
66ac27241SLeo Liu * to deal in the Software without restriction, including without limitation
76ac27241SLeo Liu * the rights to use, copy, modify, merge, publish, distribute, sublicense,
86ac27241SLeo Liu * and/or sell copies of the Software, and to permit persons to whom the
96ac27241SLeo Liu * Software is furnished to do so, subject to the following conditions:
106ac27241SLeo Liu *
116ac27241SLeo Liu * The above copyright notice and this permission notice shall be included in
126ac27241SLeo Liu * all copies or substantial portions of the Software.
136ac27241SLeo Liu *
146ac27241SLeo Liu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
156ac27241SLeo Liu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
166ac27241SLeo Liu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
176ac27241SLeo Liu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
186ac27241SLeo Liu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
196ac27241SLeo Liu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
206ac27241SLeo Liu * OTHER DEALINGS IN THE SOFTWARE.
216ac27241SLeo Liu *
226ac27241SLeo Liu */
236ac27241SLeo Liu
246ac27241SLeo Liu #include "amdgpu.h"
256ac27241SLeo Liu #include "amdgpu_jpeg.h"
26*3a23aa0bSDavid (Ming Qiang) Wu #include "amdgpu_cs.h"
276ac27241SLeo Liu #include "amdgpu_pm.h"
286ac27241SLeo Liu #include "soc15.h"
296ac27241SLeo Liu #include "soc15d.h"
304d189513SJames Zhu #include "jpeg_v2_0.h"
316ac27241SLeo Liu
326ac27241SLeo Liu #include "vcn/vcn_2_0_0_offset.h"
336ac27241SLeo Liu #include "vcn/vcn_2_0_0_sh_mask.h"
346ac27241SLeo Liu #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
356ac27241SLeo Liu
366ac27241SLeo Liu static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
376ac27241SLeo Liu static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
386ac27241SLeo Liu static int jpeg_v2_0_set_powergating_state(void *handle,
396ac27241SLeo Liu enum amd_powergating_state state);
406ac27241SLeo Liu
416ac27241SLeo Liu /**
426ac27241SLeo Liu * jpeg_v2_0_early_init - set function pointers
436ac27241SLeo Liu *
446ac27241SLeo Liu * @handle: amdgpu_device pointer
456ac27241SLeo Liu *
466ac27241SLeo Liu * Set ring and irq function pointers
476ac27241SLeo Liu */
jpeg_v2_0_early_init(void * handle)486ac27241SLeo Liu static int jpeg_v2_0_early_init(void *handle)
496ac27241SLeo Liu {
506ac27241SLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
516ac27241SLeo Liu
526ac27241SLeo Liu adev->jpeg.num_jpeg_inst = 1;
5328bb7f13SJames Zhu adev->jpeg.num_jpeg_rings = 1;
546ac27241SLeo Liu
556ac27241SLeo Liu jpeg_v2_0_set_dec_ring_funcs(adev);
566ac27241SLeo Liu jpeg_v2_0_set_irq_funcs(adev);
576ac27241SLeo Liu
586ac27241SLeo Liu return 0;
596ac27241SLeo Liu }
606ac27241SLeo Liu
616ac27241SLeo Liu /**
626ac27241SLeo Liu * jpeg_v2_0_sw_init - sw init for JPEG block
636ac27241SLeo Liu *
646ac27241SLeo Liu * @handle: amdgpu_device pointer
656ac27241SLeo Liu *
666ac27241SLeo Liu * Load firmware and sw initialization
676ac27241SLeo Liu */
jpeg_v2_0_sw_init(void * handle)686ac27241SLeo Liu static int jpeg_v2_0_sw_init(void *handle)
696ac27241SLeo Liu {
706ac27241SLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
716ac27241SLeo Liu struct amdgpu_ring *ring;
726ac27241SLeo Liu int r;
736ac27241SLeo Liu
746ac27241SLeo Liu /* JPEG TRAP */
756ac27241SLeo Liu r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
766ac27241SLeo Liu VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
776ac27241SLeo Liu if (r)
786ac27241SLeo Liu return r;
796ac27241SLeo Liu
806ac27241SLeo Liu r = amdgpu_jpeg_sw_init(adev);
816ac27241SLeo Liu if (r)
826ac27241SLeo Liu return r;
836ac27241SLeo Liu
846ac27241SLeo Liu r = amdgpu_jpeg_resume(adev);
856ac27241SLeo Liu if (r)
866ac27241SLeo Liu return r;
876ac27241SLeo Liu
88bc224553SJames Zhu ring = adev->jpeg.inst->ring_dec;
896ac27241SLeo Liu ring->use_doorbell = true;
906ac27241SLeo Liu ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
91f4caf584SHawking Zhang ring->vm_hub = AMDGPU_MMHUB0(0);
926ac27241SLeo Liu sprintf(ring->name, "jpeg_dec");
931c6d567bSNirmoy Das r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,
94c107171bSChristian König 0, AMDGPU_RING_PRIO_DEFAULT, NULL);
956ac27241SLeo Liu if (r)
966ac27241SLeo Liu return r;
976ac27241SLeo Liu
98bc224553SJames Zhu adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
99bc224553SJames Zhu adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
1006ac27241SLeo Liu
1016ac27241SLeo Liu return 0;
1026ac27241SLeo Liu }
1036ac27241SLeo Liu
1046ac27241SLeo Liu /**
1056ac27241SLeo Liu * jpeg_v2_0_sw_fini - sw fini for JPEG block
1066ac27241SLeo Liu *
1076ac27241SLeo Liu * @handle: amdgpu_device pointer
1086ac27241SLeo Liu *
1096ac27241SLeo Liu * JPEG suspend and free up sw allocation
1106ac27241SLeo Liu */
jpeg_v2_0_sw_fini(void * handle)1116ac27241SLeo Liu static int jpeg_v2_0_sw_fini(void *handle)
1126ac27241SLeo Liu {
1136ac27241SLeo Liu int r;
1146ac27241SLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1156ac27241SLeo Liu
1166ac27241SLeo Liu r = amdgpu_jpeg_suspend(adev);
1176ac27241SLeo Liu if (r)
1186ac27241SLeo Liu return r;
1196ac27241SLeo Liu
1206ac27241SLeo Liu r = amdgpu_jpeg_sw_fini(adev);
1216ac27241SLeo Liu
1226ac27241SLeo Liu return r;
1236ac27241SLeo Liu }
1246ac27241SLeo Liu
1256ac27241SLeo Liu /**
1266ac27241SLeo Liu * jpeg_v2_0_hw_init - start and test JPEG block
1276ac27241SLeo Liu *
1286ac27241SLeo Liu * @handle: amdgpu_device pointer
1296ac27241SLeo Liu *
1306ac27241SLeo Liu */
jpeg_v2_0_hw_init(void * handle)1316ac27241SLeo Liu static int jpeg_v2_0_hw_init(void *handle)
1326ac27241SLeo Liu {
1336ac27241SLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
134bc224553SJames Zhu struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
1356ac27241SLeo Liu
1366ac27241SLeo Liu adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
1376ac27241SLeo Liu (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
1386ac27241SLeo Liu
139ee3942d9SDavid (Ming Qiang) Wu return amdgpu_ring_test_helper(ring);
1406ac27241SLeo Liu }
1416ac27241SLeo Liu
1426ac27241SLeo Liu /**
1436ac27241SLeo Liu * jpeg_v2_0_hw_fini - stop the hardware block
1446ac27241SLeo Liu *
1456ac27241SLeo Liu * @handle: amdgpu_device pointer
1466ac27241SLeo Liu *
1476ac27241SLeo Liu * Stop the JPEG block, mark ring as not ready any more
1486ac27241SLeo Liu */
jpeg_v2_0_hw_fini(void * handle)1496ac27241SLeo Liu static int jpeg_v2_0_hw_fini(void *handle)
1506ac27241SLeo Liu {
1516ac27241SLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1526ac27241SLeo Liu
153ff48f6dbSJames Zhu cancel_delayed_work_sync(&adev->vcn.idle_work);
154ff48f6dbSJames Zhu
1556ac27241SLeo Liu if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
1566ac27241SLeo Liu RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
1576ac27241SLeo Liu jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
1586ac27241SLeo Liu
1596ac27241SLeo Liu return 0;
1606ac27241SLeo Liu }
1616ac27241SLeo Liu
1626ac27241SLeo Liu /**
1636ac27241SLeo Liu * jpeg_v2_0_suspend - suspend JPEG block
1646ac27241SLeo Liu *
1656ac27241SLeo Liu * @handle: amdgpu_device pointer
1666ac27241SLeo Liu *
1676ac27241SLeo Liu * HW fini and suspend JPEG block
1686ac27241SLeo Liu */
jpeg_v2_0_suspend(void * handle)1696ac27241SLeo Liu static int jpeg_v2_0_suspend(void *handle)
1706ac27241SLeo Liu {
1716ac27241SLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1726ac27241SLeo Liu int r;
1736ac27241SLeo Liu
1746ac27241SLeo Liu r = jpeg_v2_0_hw_fini(adev);
1756ac27241SLeo Liu if (r)
1766ac27241SLeo Liu return r;
1776ac27241SLeo Liu
1786ac27241SLeo Liu r = amdgpu_jpeg_suspend(adev);
1796ac27241SLeo Liu
1806ac27241SLeo Liu return r;
1816ac27241SLeo Liu }
1826ac27241SLeo Liu
1836ac27241SLeo Liu /**
1846ac27241SLeo Liu * jpeg_v2_0_resume - resume JPEG block
1856ac27241SLeo Liu *
1866ac27241SLeo Liu * @handle: amdgpu_device pointer
1876ac27241SLeo Liu *
1886ac27241SLeo Liu * Resume firmware and hw init JPEG block
1896ac27241SLeo Liu */
jpeg_v2_0_resume(void * handle)1906ac27241SLeo Liu static int jpeg_v2_0_resume(void *handle)
1916ac27241SLeo Liu {
1926ac27241SLeo Liu int r;
1936ac27241SLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1946ac27241SLeo Liu
1956ac27241SLeo Liu r = amdgpu_jpeg_resume(adev);
1966ac27241SLeo Liu if (r)
1976ac27241SLeo Liu return r;
1986ac27241SLeo Liu
1996ac27241SLeo Liu r = jpeg_v2_0_hw_init(adev);
2006ac27241SLeo Liu
2016ac27241SLeo Liu return r;
2026ac27241SLeo Liu }
2036ac27241SLeo Liu
jpeg_v2_0_disable_power_gating(struct amdgpu_device * adev)2046ac27241SLeo Liu static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)
2056ac27241SLeo Liu {
2066ac27241SLeo Liu uint32_t data;
2076ac27241SLeo Liu int r = 0;
2086ac27241SLeo Liu
209099d66e4SLeo Liu if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
2106ac27241SLeo Liu data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
2116ac27241SLeo Liu WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
2126ac27241SLeo Liu
213450da2efSJames Zhu r = SOC15_WAIT_ON_RREG(JPEG, 0,
2146ac27241SLeo Liu mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
215450da2efSJames Zhu UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
2166ac27241SLeo Liu
2176ac27241SLeo Liu if (r) {
2186ac27241SLeo Liu DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
2196ac27241SLeo Liu return r;
2206ac27241SLeo Liu }
221099d66e4SLeo Liu }
2226ac27241SLeo Liu
2236ac27241SLeo Liu /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
2246ac27241SLeo Liu data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
2256ac27241SLeo Liu WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
2266ac27241SLeo Liu
2276ac27241SLeo Liu return 0;
2286ac27241SLeo Liu }
2296ac27241SLeo Liu
jpeg_v2_0_enable_power_gating(struct amdgpu_device * adev)2306ac27241SLeo Liu static int jpeg_v2_0_enable_power_gating(struct amdgpu_device *adev)
2316ac27241SLeo Liu {
232099d66e4SLeo Liu if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
2336ac27241SLeo Liu uint32_t data;
2346ac27241SLeo Liu int r = 0;
2356ac27241SLeo Liu
2366ac27241SLeo Liu data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
2376ac27241SLeo Liu data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
2386ac27241SLeo Liu data |= 0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
2396ac27241SLeo Liu WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
2406ac27241SLeo Liu
2416ac27241SLeo Liu data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
2426ac27241SLeo Liu WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
2436ac27241SLeo Liu
244450da2efSJames Zhu r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
2456ac27241SLeo Liu (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
246450da2efSJames Zhu UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
2476ac27241SLeo Liu
2486ac27241SLeo Liu if (r) {
2496ac27241SLeo Liu DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
2506ac27241SLeo Liu return r;
2516ac27241SLeo Liu }
252099d66e4SLeo Liu }
2536ac27241SLeo Liu
2546ac27241SLeo Liu return 0;
2556ac27241SLeo Liu }
2566ac27241SLeo Liu
jpeg_v2_0_disable_clock_gating(struct amdgpu_device * adev)2576ac27241SLeo Liu static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device *adev)
2586ac27241SLeo Liu {
2596ac27241SLeo Liu uint32_t data;
2606ac27241SLeo Liu
2616ac27241SLeo Liu data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
262099d66e4SLeo Liu if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
2636ac27241SLeo Liu data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
264099d66e4SLeo Liu else
265099d66e4SLeo Liu data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
2666ac27241SLeo Liu
2676ac27241SLeo Liu data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
2686ac27241SLeo Liu data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
2696ac27241SLeo Liu WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
2706ac27241SLeo Liu
2716ac27241SLeo Liu data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
2726ac27241SLeo Liu data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
2736ac27241SLeo Liu | JPEG_CGC_GATE__JPEG2_DEC_MASK
2746ac27241SLeo Liu | JPEG_CGC_GATE__JPEG_ENC_MASK
2756ac27241SLeo Liu | JPEG_CGC_GATE__JMCIF_MASK
2766ac27241SLeo Liu | JPEG_CGC_GATE__JRBBM_MASK);
2776ac27241SLeo Liu WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
2786ac27241SLeo Liu }
2796ac27241SLeo Liu
jpeg_v2_0_enable_clock_gating(struct amdgpu_device * adev)2806ac27241SLeo Liu static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device *adev)
2816ac27241SLeo Liu {
2826ac27241SLeo Liu uint32_t data;
2836ac27241SLeo Liu
2846ac27241SLeo Liu data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
285099d66e4SLeo Liu if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
2866ac27241SLeo Liu data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
287099d66e4SLeo Liu else
288099d66e4SLeo Liu data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
2896ac27241SLeo Liu
2906ac27241SLeo Liu data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
2916ac27241SLeo Liu data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
2926ac27241SLeo Liu WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
2936ac27241SLeo Liu
2946ac27241SLeo Liu data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
2956ac27241SLeo Liu data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
2966ac27241SLeo Liu |JPEG_CGC_GATE__JPEG2_DEC_MASK
2976ac27241SLeo Liu |JPEG_CGC_GATE__JPEG_ENC_MASK
2986ac27241SLeo Liu |JPEG_CGC_GATE__JMCIF_MASK
2996ac27241SLeo Liu |JPEG_CGC_GATE__JRBBM_MASK);
3006ac27241SLeo Liu WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
3016ac27241SLeo Liu }
3026ac27241SLeo Liu
3036ac27241SLeo Liu /**
3046ac27241SLeo Liu * jpeg_v2_0_start - start JPEG block
3056ac27241SLeo Liu *
3066ac27241SLeo Liu * @adev: amdgpu_device pointer
3076ac27241SLeo Liu *
3086ac27241SLeo Liu * Setup and start the JPEG block
3096ac27241SLeo Liu */
jpeg_v2_0_start(struct amdgpu_device * adev)3106ac27241SLeo Liu static int jpeg_v2_0_start(struct amdgpu_device *adev)
3116ac27241SLeo Liu {
312bc224553SJames Zhu struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
3136ac27241SLeo Liu int r;
3146ac27241SLeo Liu
315474b6d29SLeo Liu if (adev->pm.dpm_enabled)
316474b6d29SLeo Liu amdgpu_dpm_enable_jpeg(adev, true);
317474b6d29SLeo Liu
3186ac27241SLeo Liu /* disable power gating */
3196ac27241SLeo Liu r = jpeg_v2_0_disable_power_gating(adev);
3206ac27241SLeo Liu if (r)
3216ac27241SLeo Liu return r;
3226ac27241SLeo Liu
3236ac27241SLeo Liu /* JPEG disable CGC */
3246ac27241SLeo Liu jpeg_v2_0_disable_clock_gating(adev);
3256ac27241SLeo Liu
3266ac27241SLeo Liu WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3276ac27241SLeo Liu
3286ac27241SLeo Liu /* enable JMI channel */
3296ac27241SLeo Liu WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
3306ac27241SLeo Liu ~UVD_JMI_CNTL__SOFT_RESET_MASK);
3316ac27241SLeo Liu
3326ac27241SLeo Liu /* enable System Interrupt for JRBC */
3336ac27241SLeo Liu WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
3346ac27241SLeo Liu JPEG_SYS_INT_EN__DJRBC_MASK,
3356ac27241SLeo Liu ~JPEG_SYS_INT_EN__DJRBC_MASK);
3366ac27241SLeo Liu
3376ac27241SLeo Liu WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
3386ac27241SLeo Liu WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
3396ac27241SLeo Liu WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
3406ac27241SLeo Liu lower_32_bits(ring->gpu_addr));
3416ac27241SLeo Liu WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
3426ac27241SLeo Liu upper_32_bits(ring->gpu_addr));
3436ac27241SLeo Liu WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
3446ac27241SLeo Liu WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
3456ac27241SLeo Liu WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
3466ac27241SLeo Liu WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
3476ac27241SLeo Liu ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
3486ac27241SLeo Liu
3496ac27241SLeo Liu return 0;
3506ac27241SLeo Liu }
3516ac27241SLeo Liu
3526ac27241SLeo Liu /**
3536ac27241SLeo Liu * jpeg_v2_0_stop - stop JPEG block
3546ac27241SLeo Liu *
3556ac27241SLeo Liu * @adev: amdgpu_device pointer
3566ac27241SLeo Liu *
3576ac27241SLeo Liu * stop the JPEG block
3586ac27241SLeo Liu */
jpeg_v2_0_stop(struct amdgpu_device * adev)3596ac27241SLeo Liu static int jpeg_v2_0_stop(struct amdgpu_device *adev)
3606ac27241SLeo Liu {
3616ac27241SLeo Liu int r;
3626ac27241SLeo Liu
3636ac27241SLeo Liu /* reset JMI */
3646ac27241SLeo Liu WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
3656ac27241SLeo Liu UVD_JMI_CNTL__SOFT_RESET_MASK,
3666ac27241SLeo Liu ~UVD_JMI_CNTL__SOFT_RESET_MASK);
3676ac27241SLeo Liu
3686ac27241SLeo Liu /* enable JPEG CGC */
3696ac27241SLeo Liu jpeg_v2_0_enable_clock_gating(adev);
3706ac27241SLeo Liu
3716ac27241SLeo Liu /* enable power gating */
3726ac27241SLeo Liu r = jpeg_v2_0_enable_power_gating(adev);
373474b6d29SLeo Liu if (r)
3746ac27241SLeo Liu return r;
375474b6d29SLeo Liu
376474b6d29SLeo Liu if (adev->pm.dpm_enabled)
377474b6d29SLeo Liu amdgpu_dpm_enable_jpeg(adev, false);
378474b6d29SLeo Liu
379474b6d29SLeo Liu return 0;
3806ac27241SLeo Liu }
3816ac27241SLeo Liu
3826ac27241SLeo Liu /**
3836ac27241SLeo Liu * jpeg_v2_0_dec_ring_get_rptr - get read pointer
3846ac27241SLeo Liu *
3856ac27241SLeo Liu * @ring: amdgpu_ring pointer
3866ac27241SLeo Liu *
3876ac27241SLeo Liu * Returns the current hardware read pointer
3886ac27241SLeo Liu */
jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring * ring)3896ac27241SLeo Liu static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
3906ac27241SLeo Liu {
3916ac27241SLeo Liu struct amdgpu_device *adev = ring->adev;
3926ac27241SLeo Liu
3936ac27241SLeo Liu return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
3946ac27241SLeo Liu }
3956ac27241SLeo Liu
3966ac27241SLeo Liu /**
3976ac27241SLeo Liu * jpeg_v2_0_dec_ring_get_wptr - get write pointer
3986ac27241SLeo Liu *
3996ac27241SLeo Liu * @ring: amdgpu_ring pointer
4006ac27241SLeo Liu *
4016ac27241SLeo Liu * Returns the current hardware write pointer
4026ac27241SLeo Liu */
jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring * ring)4036ac27241SLeo Liu static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
4046ac27241SLeo Liu {
4056ac27241SLeo Liu struct amdgpu_device *adev = ring->adev;
4066ac27241SLeo Liu
4076ac27241SLeo Liu if (ring->use_doorbell)
4083748424bSJack Xiao return *ring->wptr_cpu_addr;
4096ac27241SLeo Liu else
4106ac27241SLeo Liu return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
4116ac27241SLeo Liu }
4126ac27241SLeo Liu
4136ac27241SLeo Liu /**
4146ac27241SLeo Liu * jpeg_v2_0_dec_ring_set_wptr - set write pointer
4156ac27241SLeo Liu *
4166ac27241SLeo Liu * @ring: amdgpu_ring pointer
4176ac27241SLeo Liu *
4186ac27241SLeo Liu * Commits the write pointer to the hardware
4196ac27241SLeo Liu */
jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring * ring)4206ac27241SLeo Liu static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
4216ac27241SLeo Liu {
4226ac27241SLeo Liu struct amdgpu_device *adev = ring->adev;
4236ac27241SLeo Liu
4246ac27241SLeo Liu if (ring->use_doorbell) {
4253748424bSJack Xiao *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
4266ac27241SLeo Liu WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
4276ac27241SLeo Liu } else {
4286ac27241SLeo Liu WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
4296ac27241SLeo Liu }
4306ac27241SLeo Liu }
4316ac27241SLeo Liu
4326ac27241SLeo Liu /**
4336ac27241SLeo Liu * jpeg_v2_0_dec_ring_insert_start - insert a start command
4346ac27241SLeo Liu *
4356ac27241SLeo Liu * @ring: amdgpu_ring pointer
4366ac27241SLeo Liu *
4376ac27241SLeo Liu * Write a start command to the ring.
4386ac27241SLeo Liu */
jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring * ring)4396ac27241SLeo Liu void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
4406ac27241SLeo Liu {
4416ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
4426ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
4436ac27241SLeo Liu amdgpu_ring_write(ring, 0x68e04);
4446ac27241SLeo Liu
4456ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
4466ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
4476ac27241SLeo Liu amdgpu_ring_write(ring, 0x80010000);
4486ac27241SLeo Liu }
4496ac27241SLeo Liu
4506ac27241SLeo Liu /**
4516ac27241SLeo Liu * jpeg_v2_0_dec_ring_insert_end - insert a end command
4526ac27241SLeo Liu *
4536ac27241SLeo Liu * @ring: amdgpu_ring pointer
4546ac27241SLeo Liu *
4556ac27241SLeo Liu * Write a end command to the ring.
4566ac27241SLeo Liu */
jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring * ring)4576ac27241SLeo Liu void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
4586ac27241SLeo Liu {
4596ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
4606ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
4616ac27241SLeo Liu amdgpu_ring_write(ring, 0x68e04);
4626ac27241SLeo Liu
4636ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
4646ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
4656ac27241SLeo Liu amdgpu_ring_write(ring, 0x00010000);
4666ac27241SLeo Liu }
4676ac27241SLeo Liu
4686ac27241SLeo Liu /**
4696ac27241SLeo Liu * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command
4706ac27241SLeo Liu *
4716ac27241SLeo Liu * @ring: amdgpu_ring pointer
472f3d6280cSLee Jones * @addr: address
473f3d6280cSLee Jones * @seq: sequence number
474f3d6280cSLee Jones * @flags: fence related flags
4756ac27241SLeo Liu *
4766ac27241SLeo Liu * Write a fence and a trap command to the ring.
4776ac27241SLeo Liu */
jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)4786ac27241SLeo Liu void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
4796ac27241SLeo Liu unsigned flags)
4806ac27241SLeo Liu {
4816ac27241SLeo Liu WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4826ac27241SLeo Liu
4836ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
4846ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
4856ac27241SLeo Liu amdgpu_ring_write(ring, seq);
4866ac27241SLeo Liu
4876ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,
4886ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
4896ac27241SLeo Liu amdgpu_ring_write(ring, seq);
4906ac27241SLeo Liu
4916ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,
4926ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
4936ac27241SLeo Liu amdgpu_ring_write(ring, lower_32_bits(addr));
4946ac27241SLeo Liu
4956ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,
4966ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
4976ac27241SLeo Liu amdgpu_ring_write(ring, upper_32_bits(addr));
4986ac27241SLeo Liu
4996ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
5006ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
5016ac27241SLeo Liu amdgpu_ring_write(ring, 0x8);
5026ac27241SLeo Liu
5036ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
5046ac27241SLeo Liu 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
5056ac27241SLeo Liu amdgpu_ring_write(ring, 0);
5066ac27241SLeo Liu
5076ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
5086ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
5096ac27241SLeo Liu amdgpu_ring_write(ring, 0x3fbc);
5106ac27241SLeo Liu
5116ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
5126ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
5136ac27241SLeo Liu amdgpu_ring_write(ring, 0x1);
5146ac27241SLeo Liu
5156ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
5166ac27241SLeo Liu amdgpu_ring_write(ring, 0);
5176ac27241SLeo Liu }
5186ac27241SLeo Liu
5196ac27241SLeo Liu /**
5206ac27241SLeo Liu * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer
5216ac27241SLeo Liu *
5226ac27241SLeo Liu * @ring: amdgpu_ring pointer
523f3d6280cSLee Jones * @job: job to retrieve vmid from
5246ac27241SLeo Liu * @ib: indirect buffer to execute
525f3d6280cSLee Jones * @flags: unused
5266ac27241SLeo Liu *
5276ac27241SLeo Liu * Write ring commands to execute the indirect buffer.
5286ac27241SLeo Liu */
jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)5296ac27241SLeo Liu void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
5306ac27241SLeo Liu struct amdgpu_job *job,
5316ac27241SLeo Liu struct amdgpu_ib *ib,
5326ac27241SLeo Liu uint32_t flags)
5336ac27241SLeo Liu {
5346ac27241SLeo Liu unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5356ac27241SLeo Liu
536578eb317SMohammad Zafar Ziya amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET,
537578eb317SMohammad Zafar Ziya 0, 0, PACKETJ_TYPE0));
538578eb317SMohammad Zafar Ziya amdgpu_ring_write(ring, (vmid << JPEG_IH_CTRL__IH_VMID__SHIFT));
539578eb317SMohammad Zafar Ziya
5406ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
5416ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
542*3a23aa0bSDavid (Ming Qiang) Wu
543*3a23aa0bSDavid (Ming Qiang) Wu if (ring->funcs->parse_cs)
544*3a23aa0bSDavid (Ming Qiang) Wu amdgpu_ring_write(ring, 0);
545*3a23aa0bSDavid (Ming Qiang) Wu else
546e414a304SAlex Deucher amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));
5476ac27241SLeo Liu
5486ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
5496ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
550e414a304SAlex Deucher amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8)));
5516ac27241SLeo Liu
5526ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,
5536ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
5546ac27241SLeo Liu amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
5556ac27241SLeo Liu
5566ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,
5576ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
5586ac27241SLeo Liu amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5596ac27241SLeo Liu
5606ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,
5616ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
5626ac27241SLeo Liu amdgpu_ring_write(ring, ib->length_dw);
5636ac27241SLeo Liu
5646ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,
5656ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
5666ac27241SLeo Liu amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
5676ac27241SLeo Liu
5686ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,
5696ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
5706ac27241SLeo Liu amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
5716ac27241SLeo Liu
5726ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
5736ac27241SLeo Liu amdgpu_ring_write(ring, 0);
5746ac27241SLeo Liu
5756ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
5766ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
5776ac27241SLeo Liu amdgpu_ring_write(ring, 0x01400200);
5786ac27241SLeo Liu
5796ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
5806ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
5816ac27241SLeo Liu amdgpu_ring_write(ring, 0x2);
5826ac27241SLeo Liu
5836ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,
5846ac27241SLeo Liu 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
5856ac27241SLeo Liu amdgpu_ring_write(ring, 0x2);
5866ac27241SLeo Liu }
5876ac27241SLeo Liu
jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)5886ac27241SLeo Liu void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
5896ac27241SLeo Liu uint32_t val, uint32_t mask)
5906ac27241SLeo Liu {
5916ac27241SLeo Liu uint32_t reg_offset = (reg << 2);
5926ac27241SLeo Liu
5936ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
5946ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
5956ac27241SLeo Liu amdgpu_ring_write(ring, 0x01400200);
5966ac27241SLeo Liu
5976ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
5986ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
5996ac27241SLeo Liu amdgpu_ring_write(ring, val);
6006ac27241SLeo Liu
6016ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
6026ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
6036ac27241SLeo Liu if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
6046ac27241SLeo Liu amdgpu_ring_write(ring, 0);
6056ac27241SLeo Liu amdgpu_ring_write(ring,
6066ac27241SLeo Liu PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
6076ac27241SLeo Liu } else {
6086ac27241SLeo Liu amdgpu_ring_write(ring, reg_offset);
6096ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
6106ac27241SLeo Liu 0, 0, PACKETJ_TYPE3));
6116ac27241SLeo Liu }
6126ac27241SLeo Liu amdgpu_ring_write(ring, mask);
6136ac27241SLeo Liu }
6146ac27241SLeo Liu
jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)6156ac27241SLeo Liu void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
6166ac27241SLeo Liu unsigned vmid, uint64_t pd_addr)
6176ac27241SLeo Liu {
6180530553bSLe Ma struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
6196ac27241SLeo Liu uint32_t data0, data1, mask;
6206ac27241SLeo Liu
6216ac27241SLeo Liu pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
6226ac27241SLeo Liu
6236ac27241SLeo Liu /* wait for register write */
6249a69574bSHuang Rui data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
6256ac27241SLeo Liu data1 = lower_32_bits(pd_addr);
6266ac27241SLeo Liu mask = 0xffffffff;
6276ac27241SLeo Liu jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
6286ac27241SLeo Liu }
6296ac27241SLeo Liu
jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)6306ac27241SLeo Liu void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
6316ac27241SLeo Liu {
6326ac27241SLeo Liu uint32_t reg_offset = (reg << 2);
6336ac27241SLeo Liu
6346ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
6356ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
6366ac27241SLeo Liu if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
6376ac27241SLeo Liu amdgpu_ring_write(ring, 0);
6386ac27241SLeo Liu amdgpu_ring_write(ring,
6396ac27241SLeo Liu PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
6406ac27241SLeo Liu } else {
6416ac27241SLeo Liu amdgpu_ring_write(ring, reg_offset);
6426ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
6436ac27241SLeo Liu 0, 0, PACKETJ_TYPE0));
6446ac27241SLeo Liu }
6456ac27241SLeo Liu amdgpu_ring_write(ring, val);
6466ac27241SLeo Liu }
6476ac27241SLeo Liu
jpeg_v2_0_dec_ring_nop(struct amdgpu_ring * ring,uint32_t count)6486ac27241SLeo Liu void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
6496ac27241SLeo Liu {
6506ac27241SLeo Liu int i;
6516ac27241SLeo Liu
6526ac27241SLeo Liu WARN_ON(ring->wptr % 2 || count % 2);
6536ac27241SLeo Liu
6546ac27241SLeo Liu for (i = 0; i < count / 2; i++) {
6556ac27241SLeo Liu amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
6566ac27241SLeo Liu amdgpu_ring_write(ring, 0);
6576ac27241SLeo Liu }
6586ac27241SLeo Liu }
6596ac27241SLeo Liu
jpeg_v2_0_is_idle(void * handle)6606ac27241SLeo Liu static bool jpeg_v2_0_is_idle(void *handle)
6616ac27241SLeo Liu {
6626ac27241SLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6636ac27241SLeo Liu
6646ac27241SLeo Liu return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
6656ac27241SLeo Liu UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
6666ac27241SLeo Liu UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
6676ac27241SLeo Liu }
6686ac27241SLeo Liu
jpeg_v2_0_wait_for_idle(void * handle)6696ac27241SLeo Liu static int jpeg_v2_0_wait_for_idle(void *handle)
6706ac27241SLeo Liu {
6716ac27241SLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
672450da2efSJames Zhu int ret;
6736ac27241SLeo Liu
674450da2efSJames Zhu ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
675450da2efSJames Zhu UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
6766ac27241SLeo Liu
6776ac27241SLeo Liu return ret;
6786ac27241SLeo Liu }
6796ac27241SLeo Liu
jpeg_v2_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)6806ac27241SLeo Liu static int jpeg_v2_0_set_clockgating_state(void *handle,
6816ac27241SLeo Liu enum amd_clockgating_state state)
6826ac27241SLeo Liu {
6836ac27241SLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
684a9d4fe2fSNirmoy Das bool enable = (state == AMD_CG_STATE_GATE);
6856ac27241SLeo Liu
6866ac27241SLeo Liu if (enable) {
68723edf7f1SJames Zhu if (!jpeg_v2_0_is_idle(handle))
6886ac27241SLeo Liu return -EBUSY;
6896ac27241SLeo Liu jpeg_v2_0_enable_clock_gating(adev);
6906ac27241SLeo Liu } else {
6916ac27241SLeo Liu jpeg_v2_0_disable_clock_gating(adev);
6926ac27241SLeo Liu }
6936ac27241SLeo Liu
6946ac27241SLeo Liu return 0;
6956ac27241SLeo Liu }
6966ac27241SLeo Liu
jpeg_v2_0_set_powergating_state(void * handle,enum amd_powergating_state state)6976ac27241SLeo Liu static int jpeg_v2_0_set_powergating_state(void *handle,
6986ac27241SLeo Liu enum amd_powergating_state state)
6996ac27241SLeo Liu {
7006ac27241SLeo Liu struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7016ac27241SLeo Liu int ret;
7026ac27241SLeo Liu
7036ac27241SLeo Liu if (state == adev->jpeg.cur_state)
7046ac27241SLeo Liu return 0;
7056ac27241SLeo Liu
7066ac27241SLeo Liu if (state == AMD_PG_STATE_GATE)
7076ac27241SLeo Liu ret = jpeg_v2_0_stop(adev);
7086ac27241SLeo Liu else
7096ac27241SLeo Liu ret = jpeg_v2_0_start(adev);
7106ac27241SLeo Liu
7116ac27241SLeo Liu if (!ret)
7126ac27241SLeo Liu adev->jpeg.cur_state = state;
7136ac27241SLeo Liu
7146ac27241SLeo Liu return ret;
7156ac27241SLeo Liu }
7166ac27241SLeo Liu
jpeg_v2_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)7176ac27241SLeo Liu static int jpeg_v2_0_set_interrupt_state(struct amdgpu_device *adev,
7186ac27241SLeo Liu struct amdgpu_irq_src *source,
7196ac27241SLeo Liu unsigned type,
7206ac27241SLeo Liu enum amdgpu_interrupt_state state)
7216ac27241SLeo Liu {
7226ac27241SLeo Liu return 0;
7236ac27241SLeo Liu }
7246ac27241SLeo Liu
jpeg_v2_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)7256ac27241SLeo Liu static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev,
7266ac27241SLeo Liu struct amdgpu_irq_src *source,
7276ac27241SLeo Liu struct amdgpu_iv_entry *entry)
7286ac27241SLeo Liu {
7296ac27241SLeo Liu DRM_DEBUG("IH: JPEG TRAP\n");
7306ac27241SLeo Liu
7316ac27241SLeo Liu switch (entry->src_id) {
7326ac27241SLeo Liu case VCN_2_0__SRCID__JPEG_DECODE:
733bc224553SJames Zhu amdgpu_fence_process(adev->jpeg.inst->ring_dec);
7346ac27241SLeo Liu break;
7356ac27241SLeo Liu default:
7366ac27241SLeo Liu DRM_ERROR("Unhandled interrupt: %d %d\n",
7376ac27241SLeo Liu entry->src_id, entry->src_data[0]);
7386ac27241SLeo Liu break;
7396ac27241SLeo Liu }
7406ac27241SLeo Liu
7416ac27241SLeo Liu return 0;
7426ac27241SLeo Liu }
7436ac27241SLeo Liu
7446ac27241SLeo Liu static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
7456ac27241SLeo Liu .name = "jpeg_v2_0",
7466ac27241SLeo Liu .early_init = jpeg_v2_0_early_init,
7476ac27241SLeo Liu .late_init = NULL,
7486ac27241SLeo Liu .sw_init = jpeg_v2_0_sw_init,
7496ac27241SLeo Liu .sw_fini = jpeg_v2_0_sw_fini,
7506ac27241SLeo Liu .hw_init = jpeg_v2_0_hw_init,
7516ac27241SLeo Liu .hw_fini = jpeg_v2_0_hw_fini,
7526ac27241SLeo Liu .suspend = jpeg_v2_0_suspend,
7536ac27241SLeo Liu .resume = jpeg_v2_0_resume,
7546ac27241SLeo Liu .is_idle = jpeg_v2_0_is_idle,
7556ac27241SLeo Liu .wait_for_idle = jpeg_v2_0_wait_for_idle,
7566ac27241SLeo Liu .check_soft_reset = NULL,
7576ac27241SLeo Liu .pre_soft_reset = NULL,
7586ac27241SLeo Liu .soft_reset = NULL,
7596ac27241SLeo Liu .post_soft_reset = NULL,
7606ac27241SLeo Liu .set_clockgating_state = jpeg_v2_0_set_clockgating_state,
7616ac27241SLeo Liu .set_powergating_state = jpeg_v2_0_set_powergating_state,
762e21d253bSSunil Khatri .dump_ip_state = NULL,
76340356542SSunil Khatri .print_ip_state = NULL,
7646ac27241SLeo Liu };
7656ac27241SLeo Liu
7666ac27241SLeo Liu static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
7676ac27241SLeo Liu .type = AMDGPU_RING_TYPE_VCN_JPEG,
7686ac27241SLeo Liu .align_mask = 0xf,
7696ac27241SLeo Liu .get_rptr = jpeg_v2_0_dec_ring_get_rptr,
7706ac27241SLeo Liu .get_wptr = jpeg_v2_0_dec_ring_get_wptr,
7716ac27241SLeo Liu .set_wptr = jpeg_v2_0_dec_ring_set_wptr,
772*3a23aa0bSDavid (Ming Qiang) Wu .parse_cs = jpeg_v2_dec_ring_parse_cs,
7736ac27241SLeo Liu .emit_frame_size =
7746ac27241SLeo Liu SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
7756ac27241SLeo Liu SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
7766ac27241SLeo Liu 8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */
7776ac27241SLeo Liu 18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */
7786ac27241SLeo Liu 8 + 16,
779578eb317SMohammad Zafar Ziya .emit_ib_size = 24, /* jpeg_v2_0_dec_ring_emit_ib */
7806ac27241SLeo Liu .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
7816ac27241SLeo Liu .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
7826ac27241SLeo Liu .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
7836ac27241SLeo Liu .test_ring = amdgpu_jpeg_dec_ring_test_ring,
7846ac27241SLeo Liu .test_ib = amdgpu_jpeg_dec_ring_test_ib,
7856ac27241SLeo Liu .insert_nop = jpeg_v2_0_dec_ring_nop,
7866ac27241SLeo Liu .insert_start = jpeg_v2_0_dec_ring_insert_start,
7876ac27241SLeo Liu .insert_end = jpeg_v2_0_dec_ring_insert_end,
7886ac27241SLeo Liu .pad_ib = amdgpu_ring_generic_pad_ib,
7896ac27241SLeo Liu .begin_use = amdgpu_jpeg_ring_begin_use,
7906ac27241SLeo Liu .end_use = amdgpu_jpeg_ring_end_use,
7916ac27241SLeo Liu .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
7926ac27241SLeo Liu .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
7936ac27241SLeo Liu .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
7946ac27241SLeo Liu };
7956ac27241SLeo Liu
jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device * adev)7966ac27241SLeo Liu static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
7976ac27241SLeo Liu {
798bc224553SJames Zhu adev->jpeg.inst->ring_dec->funcs = &jpeg_v2_0_dec_ring_vm_funcs;
7996ac27241SLeo Liu }
8006ac27241SLeo Liu
8016ac27241SLeo Liu static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = {
8026ac27241SLeo Liu .set = jpeg_v2_0_set_interrupt_state,
8036ac27241SLeo Liu .process = jpeg_v2_0_process_interrupt,
8046ac27241SLeo Liu };
8056ac27241SLeo Liu
jpeg_v2_0_set_irq_funcs(struct amdgpu_device * adev)8066ac27241SLeo Liu static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev)
8076ac27241SLeo Liu {
8086ac27241SLeo Liu adev->jpeg.inst->irq.num_types = 1;
8096ac27241SLeo Liu adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;
8106ac27241SLeo Liu }
8116ac27241SLeo Liu
8127c29b402SRan Sun const struct amdgpu_ip_block_version jpeg_v2_0_ip_block = {
8136ac27241SLeo Liu .type = AMD_IP_BLOCK_TYPE_JPEG,
8146ac27241SLeo Liu .major = 2,
8156ac27241SLeo Liu .minor = 0,
8166ac27241SLeo Liu .rev = 0,
8176ac27241SLeo Liu .funcs = &jpeg_v2_0_ip_funcs,
8186ac27241SLeo Liu };
819*3a23aa0bSDavid (Ming Qiang) Wu
820*3a23aa0bSDavid (Ming Qiang) Wu /**
821*3a23aa0bSDavid (Ming Qiang) Wu * jpeg_v2_dec_ring_parse_cs - command submission parser
822*3a23aa0bSDavid (Ming Qiang) Wu *
823*3a23aa0bSDavid (Ming Qiang) Wu * @parser: Command submission parser context
824*3a23aa0bSDavid (Ming Qiang) Wu * @job: the job to parse
825*3a23aa0bSDavid (Ming Qiang) Wu * @ib: the IB to parse
826*3a23aa0bSDavid (Ming Qiang) Wu *
827*3a23aa0bSDavid (Ming Qiang) Wu * Parse the command stream, return -EINVAL for invalid packet,
828*3a23aa0bSDavid (Ming Qiang) Wu * 0 otherwise
829*3a23aa0bSDavid (Ming Qiang) Wu */
jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser * parser,struct amdgpu_job * job,struct amdgpu_ib * ib)830*3a23aa0bSDavid (Ming Qiang) Wu int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser,
831*3a23aa0bSDavid (Ming Qiang) Wu struct amdgpu_job *job,
832*3a23aa0bSDavid (Ming Qiang) Wu struct amdgpu_ib *ib)
833*3a23aa0bSDavid (Ming Qiang) Wu {
834*3a23aa0bSDavid (Ming Qiang) Wu u32 i, reg, res, cond, type;
835*3a23aa0bSDavid (Ming Qiang) Wu struct amdgpu_device *adev = parser->adev;
836*3a23aa0bSDavid (Ming Qiang) Wu
837*3a23aa0bSDavid (Ming Qiang) Wu for (i = 0; i < ib->length_dw ; i += 2) {
838*3a23aa0bSDavid (Ming Qiang) Wu reg = CP_PACKETJ_GET_REG(ib->ptr[i]);
839*3a23aa0bSDavid (Ming Qiang) Wu res = CP_PACKETJ_GET_RES(ib->ptr[i]);
840*3a23aa0bSDavid (Ming Qiang) Wu cond = CP_PACKETJ_GET_COND(ib->ptr[i]);
841*3a23aa0bSDavid (Ming Qiang) Wu type = CP_PACKETJ_GET_TYPE(ib->ptr[i]);
842*3a23aa0bSDavid (Ming Qiang) Wu
843*3a23aa0bSDavid (Ming Qiang) Wu if (res) /* only support 0 at the moment */
844*3a23aa0bSDavid (Ming Qiang) Wu return -EINVAL;
845*3a23aa0bSDavid (Ming Qiang) Wu
846*3a23aa0bSDavid (Ming Qiang) Wu switch (type) {
847*3a23aa0bSDavid (Ming Qiang) Wu case PACKETJ_TYPE0:
848*3a23aa0bSDavid (Ming Qiang) Wu if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START ||
849*3a23aa0bSDavid (Ming Qiang) Wu reg > JPEG_REG_RANGE_END) {
850*3a23aa0bSDavid (Ming Qiang) Wu dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
851*3a23aa0bSDavid (Ming Qiang) Wu return -EINVAL;
852*3a23aa0bSDavid (Ming Qiang) Wu }
853*3a23aa0bSDavid (Ming Qiang) Wu break;
854*3a23aa0bSDavid (Ming Qiang) Wu case PACKETJ_TYPE3:
855*3a23aa0bSDavid (Ming Qiang) Wu if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START ||
856*3a23aa0bSDavid (Ming Qiang) Wu reg > JPEG_REG_RANGE_END) {
857*3a23aa0bSDavid (Ming Qiang) Wu dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
858*3a23aa0bSDavid (Ming Qiang) Wu return -EINVAL;
859*3a23aa0bSDavid (Ming Qiang) Wu }
860*3a23aa0bSDavid (Ming Qiang) Wu break;
861*3a23aa0bSDavid (Ming Qiang) Wu case PACKETJ_TYPE6:
862*3a23aa0bSDavid (Ming Qiang) Wu if (ib->ptr[i] == CP_PACKETJ_NOP)
863*3a23aa0bSDavid (Ming Qiang) Wu continue;
864*3a23aa0bSDavid (Ming Qiang) Wu dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]);
865*3a23aa0bSDavid (Ming Qiang) Wu return -EINVAL;
866*3a23aa0bSDavid (Ming Qiang) Wu default:
867*3a23aa0bSDavid (Ming Qiang) Wu dev_err(adev->dev, "Unknown packet type %d !\n", type);
868*3a23aa0bSDavid (Ming Qiang) Wu return -EINVAL;
869*3a23aa0bSDavid (Ming Qiang) Wu }
870*3a23aa0bSDavid (Ming Qiang) Wu }
871*3a23aa0bSDavid (Ming Qiang) Wu
872*3a23aa0bSDavid (Ming Qiang) Wu return 0;
873*3a23aa0bSDavid (Ming Qiang) Wu }
874