1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_imu.h" 27 #include "amdgpu_dpm.h" 28 29 #include "imu_v12_0.h" 30 31 #include "gc/gc_12_0_0_offset.h" 32 #include "gc/gc_12_0_0_sh_mask.h" 33 #include "mmhub/mmhub_4_1_0_offset.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_12_0_0_imu.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_12_0_1_imu.bin"); 37 38 #define TRANSFER_RAM_MASK 0x001c0000 39 40 static int imu_v12_0_init_microcode(struct amdgpu_device *adev) 41 { 42 char ucode_prefix[15]; 43 int err; 44 const struct imu_firmware_header_v1_0 *imu_hdr; 45 struct amdgpu_firmware_info *info = NULL; 46 47 DRM_DEBUG("\n"); 48 49 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 50 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, 51 "amdgpu/%s_imu.bin", ucode_prefix); 52 if (err) 53 goto out; 54 55 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; 56 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); 57 58 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 59 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_I]; 60 info->ucode_id = AMDGPU_UCODE_ID_IMU_I; 61 info->fw = adev->gfx.imu_fw; 62 adev->firmware.fw_size += 63 ALIGN(le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes), PAGE_SIZE); 64 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_D]; 65 info->ucode_id = AMDGPU_UCODE_ID_IMU_D; 66 info->fw = adev->gfx.imu_fw; 67 adev->firmware.fw_size += 68 ALIGN(le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes), PAGE_SIZE); 69 } 70 71 out: 72 if (err) { 73 dev_err(adev->dev, 74 "gfx12: Failed to load firmware \"%s_imu.bin\"\n", 75 ucode_prefix); 76 amdgpu_ucode_release(&adev->gfx.imu_fw); 77 } 78 79 return err; 80 } 81 82 static int imu_v12_0_load_microcode(struct amdgpu_device *adev) 83 { 84 const struct imu_firmware_header_v1_0 *hdr; 85 const __le32 *fw_data; 86 unsigned i, fw_size; 87 88 if (!adev->gfx.imu_fw) 89 return -EINVAL; 90 91 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; 92 93 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + 94 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 95 fw_size = le32_to_cpu(hdr->imu_iram_ucode_size_bytes) / 4; 96 97 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0); 98 99 for (i = 0; i < fw_size; i++) 100 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++)); 101 102 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version); 103 104 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + 105 le32_to_cpu(hdr->header.ucode_array_offset_bytes) + 106 le32_to_cpu(hdr->imu_iram_ucode_size_bytes)); 107 fw_size = le32_to_cpu(hdr->imu_dram_ucode_size_bytes) / 4; 108 109 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0); 110 111 for (i = 0; i < fw_size; i++) 112 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++)); 113 114 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version); 115 116 return 0; 117 } 118 119 static int imu_v12_0_wait_for_reset_status(struct amdgpu_device *adev) 120 { 121 u32 imu_reg_val = 0; 122 int i; 123 124 for (i = 0; i < adev->usec_timeout; i++) { 125 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); 126 if ((imu_reg_val & 0x1f) == 0x1f) 127 break; 128 udelay(1); 129 } 130 131 if (i >= adev->usec_timeout) { 132 dev_err(adev->dev, "init imu: IMU start timeout\n"); 133 return -ETIMEDOUT; 134 } 135 136 return 0; 137 } 138 139 static void imu_v12_0_setup(struct amdgpu_device *adev) 140 { 141 u32 imu_reg_val; 142 143 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff); 144 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff); 145 146 if (adev->gfx.imu.mode == DEBUG_MODE) { 147 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16); 148 imu_reg_val |= 0x1; 149 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val); 150 151 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10); 152 imu_reg_val |= 0x20010007; 153 WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val); 154 155 } 156 } 157 158 static int imu_v12_0_start(struct amdgpu_device *adev) 159 { 160 u32 imu_reg_val; 161 162 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL); 163 imu_reg_val &= 0xfffffffe; 164 WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val); 165 166 if (adev->flags & AMD_IS_APU) 167 amdgpu_dpm_set_gfx_power_up_by_imu(adev); 168 169 return imu_v12_0_wait_for_reset_status(adev); 170 } 171 172 static const struct imu_rlc_ram_golden imu_rlc_ram_golden_12_0_1[] = { 173 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCH_PIPE_STEER, 0x1e4, 0x1c0000), 174 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL1X_PIPE_STEER, 0x1e4, 0x1c0000), 175 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL1_PIPE_STEER, 0x1e4, 0x1c0000), 176 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_0, 0x13571357, 0x1c0000), 177 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_1, 0x64206420, 0x1c0000), 178 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_2, 0x2460246, 0x1c0000), 179 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2_PIPE_STEER_3, 0x75317531, 0x1c0000), 180 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xc0d41183, 0x1c0000), 181 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_CHICKEN_BITS, 0x507d1c0, 0x1c0000), 182 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_CHICKEN_BITS, 0x507d1c0, 0x1c0000), 183 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_RB_WPTR_POLL_CNTL, 0x600100, 0x1c0000), 184 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_CREDITS, 0x3f7fff, 0x1c0000), 185 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_CREDITS, 0x3f7ebf, 0x1c0000), 186 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_TAG_RESERVE0, 0x2e00000, 0x1c0000), 187 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_TAG_RESERVE1, 0x1a078, 0x1c0000), 188 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_TAG_RESERVE2, 0x0, 0x1c0000), 189 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_TAG_RESERVE0, 0x0, 0x1c0000), 190 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_TAG_RESERVE1, 0x12030, 0x1c0000), 191 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_TAG_RESERVE2, 0x0, 0x1c0000), 192 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_VCC_RESERVE0, 0x19041000, 0x1c0000), 193 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_VCC_RESERVE1, 0x80000000, 0x1c0000), 194 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_VCC_RESERVE0, 0x1e080000, 0x1c0000), 195 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_VCC_RESERVE1, 0x80000000, 0x1c0000), 196 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_PRIORITY, 0x880, 0x1c0000), 197 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_PRIORITY, 0x8880, 0x1c0000), 198 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_ARB_FINAL, 0x17, 0x1c0000), 199 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_ARB_FINAL, 0x77, 0x1c0000), 200 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_SDP_ENABLE, 0x00000001, 0x1c0000), 201 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_SDP_ENABLE, 0x00000001, 0x1c0000), 202 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x20000, 0x1c0000), 203 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_APT_CNTL, 0x0c, 0x1c0000), 204 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xfffff, 0x1c0000), 205 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_CPWD_MISC, 0x0091, 0x1c0000), 206 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGC_EA_SE_MISC, 0x0091, 0x1c0000), 207 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000), 208 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCR_GENERAL_CNTL, 0x00008500, 0x1c0000), 209 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0x00880007, 0x1c0000), 210 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regTD_CNTL, 0x00000001, 0x1c0000), 211 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000000, 0x1c0000), 212 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000), 213 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000001, 0x1c0000), 214 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000), 215 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000100, 0x1c0000), 216 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000), 217 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0x00000101, 0x1c0000), 218 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regRMI_GENERAL_CNTL, 0x01e00000, 0x1c0000), 219 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBM_GFX_INDEX, 0xe0000000, 0x1c0000), 220 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x08200545, 0x1c0000), 221 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGRBMH_CP_PERFMON_CNTL, 0x00000000, 0x1c0000), 222 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCB_PERFCOUNTER0_SELECT1, 0x000fffff, 0x1c0000), 223 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_DEBUG_2, 0x00020000, 0x1c0000), 224 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCP_CPC_DEBUG, 0x00500010, 0x1c0000), 225 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000500, 0x1c0000), 226 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x00000001, 0x1c0000), 227 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x00000000, 0x1c0000), 228 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START, 0x00000000, 0x1c0000), 229 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END, 0x0000000f, 0x1c0000), 230 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_BASE, 0x00006000, 0x1c0000), 231 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_FB_LOCATION_TOP, 0x0000600f, 0x1c0000), 232 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT0_CNTL, 0x00000000, 0x1c0000), 233 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_CONTEXT1_CNTL, 0x00000000, 0x1c0000), 234 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_TOP_OF_DRAM_SLOT1, 0xff800000, 0xe0000000), 235 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_LOWER_TOP_OF_DRAM2, 0x00000001, 0x1c0000), 236 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_NB_UPPER_TOP_OF_DRAM2, 0x0000ffff, 0x1c0000), 237 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BASE, 0x00000000, 0x1c0000), 238 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0x1c0000), 239 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0x1c0000), 240 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, 0x00001ffc, 0x1c0000), 241 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, 0x00000551, 0x1c0000), 242 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL, 0x00080603, 0x1c0000), 243 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL2, 0x00000003, 0x1c0000), 244 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL3, 0x00100003, 0x1c0000), 245 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_CNTL5, 0x00003fe0, 0x1c0000), 246 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x0003d000, 0x1c0000), 247 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0x0003d7ff, 0x1c0000), 248 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0, 0x1c0000), 249 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0, 0x1c0000) 250 }; 251 252 static void program_imu_rlc_ram_old(struct amdgpu_device *adev, 253 const struct imu_rlc_ram_golden *regs, 254 const u32 array_size) 255 { 256 const struct imu_rlc_ram_golden *entry; 257 u32 reg, data; 258 int i; 259 260 for (i = 0; i < array_size; ++i) { 261 entry = ®s[i]; 262 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 263 reg |= entry->addr_mask; 264 data = entry->data; 265 if (entry->reg == regGCMC_VM_AGP_BASE) 266 data = 0x00ffffff; 267 else if (entry->reg == regGCMC_VM_AGP_TOP) 268 data = 0x0; 269 else if (entry->reg == regGCMC_VM_FB_LOCATION_BASE) 270 data = adev->gmc.vram_start >> 24; 271 else if (entry->reg == regGCMC_VM_FB_LOCATION_TOP) 272 data = adev->gmc.vram_end >> 24; 273 274 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); 275 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg); 276 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data); 277 } 278 } 279 280 static u32 imu_v12_0_grbm_gfx_index_remap(struct amdgpu_device *adev, 281 u32 data, bool high) 282 { 283 u32 val, inst_index; 284 285 inst_index = REG_GET_FIELD(data, GRBM_GFX_INDEX, INSTANCE_INDEX); 286 287 if (high) 288 val = inst_index >> 5; 289 else 290 val = REG_GET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES) << 18 | 291 REG_GET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES) << 19 | 292 REG_GET_FIELD(data, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES) << 20 | 293 REG_GET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX) << 21 | 294 REG_GET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX) << 25 | 295 (inst_index & 0x1f); 296 297 return val; 298 } 299 300 static u32 imu_v12_init_gfxhub_settings(struct amdgpu_device *adev, 301 u32 reg, u32 data) 302 { 303 if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_LOCATION_BASE)) 304 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); 305 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_LOCATION_TOP)) 306 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_TOP); 307 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_FB_OFFSET)) 308 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET); 309 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_BASE)) 310 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE); 311 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_BOT)) 312 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT); 313 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_AGP_TOP)) 314 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP); 315 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL)) 316 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 317 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR)) 318 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR); 319 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR)) 320 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR); 321 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_START)) 322 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_FB_ADDRESS_START); 323 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_FB_ADDRESS_END)) 324 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_FB_ADDRESS_END); 325 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START)) 326 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START); 327 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END)) 328 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END); 329 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB)) 330 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB); 331 else if (reg == SOC15_REG_OFFSET(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB)) 332 return RREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB); 333 else 334 return data; 335 } 336 337 static void program_imu_rlc_ram(struct amdgpu_device *adev, 338 const u32 *regs, 339 const u32 array_size) 340 { 341 u32 reg, data, val_h = 0, val_l = TRANSFER_RAM_MASK; 342 int i; 343 344 if (array_size % 3) 345 return; 346 347 for (i = 0; i < array_size; i += 3) { 348 reg = regs[i + 0]; 349 data = regs[i + 2]; 350 data = imu_v12_init_gfxhub_settings(adev, reg, data); 351 if (reg == SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX)) { 352 val_l = imu_v12_0_grbm_gfx_index_remap(adev, data, false); 353 val_h = imu_v12_0_grbm_gfx_index_remap(adev, data, true); 354 } else { 355 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, val_h); 356 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg | val_l); 357 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data); 358 } 359 } 360 } 361 362 static void imu_v12_0_program_rlc_ram(struct amdgpu_device *adev) 363 { 364 u32 reg_data, size = 0; 365 const u32 *data; 366 int r = -EINVAL; 367 368 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, 0x2); 369 370 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 371 case IP_VERSION(12, 0, 0): 372 case IP_VERSION(12, 0, 1): 373 if (!r) 374 program_imu_rlc_ram(adev, data, (const u32)size); 375 else 376 program_imu_rlc_ram_old(adev, imu_rlc_ram_golden_12_0_1, 377 (const u32)ARRAY_SIZE(imu_rlc_ram_golden_12_0_1)); 378 break; 379 default: 380 BUG(); 381 break; 382 } 383 384 //Indicate the latest entry 385 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0); 386 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0); 387 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, 0); 388 389 reg_data = RREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX); 390 reg_data |= GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK; 391 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, reg_data); 392 } 393 394 const struct amdgpu_imu_funcs gfx_v12_0_imu_funcs = { 395 .init_microcode = imu_v12_0_init_microcode, 396 .load_microcode = imu_v12_0_load_microcode, 397 .setup_imu = imu_v12_0_setup, 398 .start_imu = imu_v12_0_start, 399 .program_rlc_ram = imu_v12_0_program_rlc_ram, 400 .wait_for_reset_status = imu_v12_0_wait_for_reset_status, 401 }; 402