1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 29 #include "oss/osssys_7_0_0_offset.h" 30 #include "oss/osssys_7_0_0_sh_mask.h" 31 32 #include "soc15_common.h" 33 #include "ih_v7_0.h" 34 35 #define MAX_REARM_RETRY 10 36 37 static void ih_v7_0_set_interrupt_funcs(struct amdgpu_device *adev); 38 39 /** 40 * ih_v7_0_init_register_offset - Initialize register offset for ih rings 41 * 42 * @adev: amdgpu_device pointer 43 * 44 * Initialize register offset ih rings (IH_V7_0). 45 */ 46 static void ih_v7_0_init_register_offset(struct amdgpu_device *adev) 47 { 48 struct amdgpu_ih_regs *ih_regs; 49 50 /* ih ring 2 is removed 51 * ih ring and ih ring 1 are available */ 52 if (adev->irq.ih.ring_size) { 53 ih_regs = &adev->irq.ih.ih_regs; 54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); 55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); 56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); 57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); 58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); 59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR); 60 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO); 61 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_HI); 62 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; 63 } 64 65 if (adev->irq.ih1.ring_size) { 66 ih_regs = &adev->irq.ih1.ih_regs; 67 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_RING1); 68 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI_RING1); 69 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1); 70 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1); 71 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1); 72 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR_RING1); 73 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; 74 } 75 } 76 77 /** 78 * force_update_wptr_for_self_int - Force update the wptr for self interrupt 79 * 80 * @adev: amdgpu_device pointer 81 * @threshold: threshold to trigger the wptr reporting 82 * @timeout: timeout to trigger the wptr reporting 83 * @enabled: Enable/disable timeout flush mechanism 84 * 85 * threshold input range: 0 ~ 15, default 0, 86 * real_threshold = 2^threshold 87 * timeout input range: 0 ~ 20, default 8, 88 * real_timeout = (2^timeout) * 1024 / (socclk_freq) 89 * 90 * Force update wptr for self interrupt ( >= SIENNA_CICHLID). 91 */ 92 static void 93 force_update_wptr_for_self_int(struct amdgpu_device *adev, 94 u32 threshold, u32 timeout, bool enabled) 95 { 96 u32 ih_cntl, ih_rb_cntl; 97 98 ih_cntl = RREG32_SOC15(OSSSYS, 0, regIH_CNTL2); 99 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1); 100 101 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 102 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout); 103 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2, 104 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled); 105 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1, 106 RB_USED_INT_THRESHOLD, threshold); 107 108 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { 109 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl)) 110 return; 111 } else { 112 WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl); 113 } 114 115 WREG32_SOC15(OSSSYS, 0, regIH_CNTL2, ih_cntl); 116 } 117 118 /** 119 * ih_v7_0_toggle_ring_interrupts - toggle the interrupt ring buffer 120 * 121 * @adev: amdgpu_device pointer 122 * @ih: amdgpu_ih_ring pointet 123 * @enable: true - enable the interrupts, false - disable the interrupts 124 * 125 * Toggle the interrupt ring buffer (IH_V7_0) 126 */ 127 static int ih_v7_0_toggle_ring_interrupts(struct amdgpu_device *adev, 128 struct amdgpu_ih_ring *ih, 129 bool enable) 130 { 131 struct amdgpu_ih_regs *ih_regs; 132 uint32_t tmp; 133 134 ih_regs = &ih->ih_regs; 135 136 tmp = RREG32(ih_regs->ih_rb_cntl); 137 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); 138 /* enable_intr field is only valid in ring0 */ 139 if (ih == &adev->irq.ih) 140 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); 141 142 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { 143 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) 144 return -ETIMEDOUT; 145 } else { 146 WREG32(ih_regs->ih_rb_cntl, tmp); 147 } 148 149 if (enable) { 150 ih->enabled = true; 151 } else { 152 /* set rptr, wptr to 0 */ 153 WREG32(ih_regs->ih_rb_rptr, 0); 154 WREG32(ih_regs->ih_rb_wptr, 0); 155 ih->enabled = false; 156 ih->rptr = 0; 157 } 158 159 return 0; 160 } 161 162 /** 163 * ih_v7_0_toggle_interrupts - Toggle all the available interrupt ring buffers 164 * 165 * @adev: amdgpu_device pointer 166 * @enable: enable or disable interrupt ring buffers 167 * 168 * Toggle all the available interrupt ring buffers (IH_V7_0). 169 */ 170 static int ih_v7_0_toggle_interrupts(struct amdgpu_device *adev, bool enable) 171 { 172 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; 173 int i; 174 int r; 175 176 for (i = 0; i < ARRAY_SIZE(ih); i++) { 177 if (ih[i]->ring_size) { 178 r = ih_v7_0_toggle_ring_interrupts(adev, ih[i], enable); 179 if (r) 180 return r; 181 } 182 } 183 184 return 0; 185 } 186 187 static uint32_t ih_v7_0_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) 188 { 189 int rb_bufsz = order_base_2(ih->ring_size / 4); 190 191 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 192 MC_SPACE, ih->use_bus_addr ? 2 : 4); 193 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 194 WPTR_OVERFLOW_CLEAR, 1); 195 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 196 WPTR_OVERFLOW_ENABLE, 1); 197 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 198 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register 199 * value is written to memory 200 */ 201 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, 202 WPTR_WRITEBACK_ENABLE, 1); 203 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1); 204 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0); 205 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 206 207 return ih_rb_cntl; 208 } 209 210 static uint32_t ih_v7_0_doorbell_rptr(struct amdgpu_ih_ring *ih) 211 { 212 u32 ih_doorbell_rtpr = 0; 213 214 if (ih->use_doorbell) { 215 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 216 IH_DOORBELL_RPTR, OFFSET, 217 ih->doorbell_index); 218 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 219 IH_DOORBELL_RPTR, 220 ENABLE, 1); 221 } else { 222 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, 223 IH_DOORBELL_RPTR, 224 ENABLE, 0); 225 } 226 return ih_doorbell_rtpr; 227 } 228 229 /** 230 * ih_v7_0_enable_ring - enable an ih ring buffer 231 * 232 * @adev: amdgpu_device pointer 233 * @ih: amdgpu_ih_ring pointer 234 * 235 * Enable an ih ring buffer (IH_V7_0) 236 */ 237 static int ih_v7_0_enable_ring(struct amdgpu_device *adev, 238 struct amdgpu_ih_ring *ih) 239 { 240 struct amdgpu_ih_regs *ih_regs; 241 uint32_t tmp; 242 243 ih_regs = &ih->ih_regs; 244 245 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 246 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); 247 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); 248 249 tmp = RREG32(ih_regs->ih_rb_cntl); 250 tmp = ih_v7_0_rb_cntl(ih, tmp); 251 if (ih == &adev->irq.ih) 252 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); 253 if (ih == &adev->irq.ih1) { 254 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0); 255 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1); 256 } 257 258 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { 259 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { 260 DRM_ERROR("PSP program IH_RB_CNTL failed!\n"); 261 return -ETIMEDOUT; 262 } 263 } else { 264 WREG32(ih_regs->ih_rb_cntl, tmp); 265 } 266 267 if (ih == &adev->irq.ih) { 268 /* set the ih ring 0 writeback address whether it's enabled or not */ 269 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); 270 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); 271 } 272 273 /* set rptr, wptr to 0 */ 274 WREG32(ih_regs->ih_rb_wptr, 0); 275 WREG32(ih_regs->ih_rb_rptr, 0); 276 277 WREG32(ih_regs->ih_doorbell_rptr, ih_v7_0_doorbell_rptr(ih)); 278 279 return 0; 280 } 281 282 static uint32_t ih_v7_0_setup_retry_doorbell(u32 doorbell_index) 283 { 284 u32 val = 0; 285 286 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index); 287 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1); 288 289 return val; 290 } 291 292 #define regIH_RING1_CLIENT_CFG_INDEX_V7_1 0x122 293 #define regIH_RING1_CLIENT_CFG_INDEX_V7_1_BASE_IDX 0 294 #define regIH_RING1_CLIENT_CFG_DATA_V7_1 0x123 295 #define regIH_RING1_CLIENT_CFG_DATA_V7_1_BASE_IDX 0 296 #define regIH_CHICKEN_V7_1 0x129 297 #define regIH_CHICKEN_V7_1_BASE_IDX 0 298 299 /** 300 * ih_v7_0_irq_init - init and enable the interrupt ring 301 * 302 * @adev: amdgpu_device pointer 303 * 304 * Allocate a ring buffer for the interrupt controller, 305 * enable the RLC, disable interrupts, enable the IH 306 * ring buffer and enable it. 307 * Called at device load and reume. 308 * Returns 0 for success, errors for failure. 309 */ 310 static int ih_v7_0_irq_init(struct amdgpu_device *adev) 311 { 312 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; 313 u32 ih_chicken; 314 u32 tmp; 315 int ret; 316 int i; 317 u32 reg_addr; 318 319 /* disable irqs */ 320 ret = ih_v7_0_toggle_interrupts(adev, false); 321 if (ret) 322 return ret; 323 324 adev->nbio.funcs->ih_control(adev); 325 326 if (unlikely((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || 327 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO))) { 328 if (ih[0]->use_bus_addr) { 329 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(7, 1, 0)) 330 reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_CHICKEN_V7_1); 331 else 332 reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_CHICKEN); 333 ih_chicken = RREG32(reg_addr); 334 /* The reg fields definitions are identical in ih v7_0 and ih v7_1 */ 335 ih_chicken = REG_SET_FIELD(ih_chicken, 336 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); 337 WREG32(reg_addr, ih_chicken); 338 } 339 } 340 341 for (i = 0; i < ARRAY_SIZE(ih); i++) { 342 if (ih[i]->ring_size) { 343 ret = ih_v7_0_enable_ring(adev, ih[i]); 344 if (ret) 345 return ret; 346 } 347 } 348 349 /* update doorbell range for ih ring 0 */ 350 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, 351 ih[0]->doorbell_index); 352 353 tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL); 354 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL, 355 CLIENT18_IS_STORM_CLIENT, 1); 356 WREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL, tmp); 357 358 tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL); 359 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1); 360 WREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL, tmp); 361 362 /* GC/MMHUB UTCL2 page fault interrupts are configured as 363 * MSI storm capable interrupts by deafult. The delay is 364 * used to avoid ISR being called too frequently 365 * when page fault happens on several continuous page 366 * and thus avoid MSI storm */ 367 tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL); 368 tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL, 369 DELAY, 3); 370 WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp); 371 372 /* Redirect the interrupts to IH RB1 for dGPU */ 373 if (adev->irq.ih1.ring_size) { 374 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(7, 1, 0)) 375 reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX_V7_1); 376 else 377 reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX); 378 tmp = RREG32(reg_addr); 379 /* The reg fields definitions are identical in ih v7_0 and ih v7_1 */ 380 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0); 381 WREG32(reg_addr, tmp); 382 383 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(7, 1, 0)) 384 reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA_V7_1); 385 else 386 reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA); 387 tmp = RREG32(reg_addr); 388 /* The reg fields definitions are identical in ih v7_0 and ih v7_1 */ 389 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa); 390 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0); 391 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, 392 SOURCE_ID_MATCH_ENABLE, 0x1); 393 WREG32(reg_addr, tmp); 394 } 395 396 pci_set_master(adev->pdev); 397 398 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(7, 1, 0)) { 399 /* Allocate the doorbell for IH Retry CAM */ 400 adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 2) << 1; 401 WREG32_SOC15(OSSSYS, 0, regIH_DOORBELL_RETRY_CAM, 402 ih_v7_0_setup_retry_doorbell(adev->irq.retry_cam_doorbell_index)); 403 404 /* Enable IH Retry CAM */ 405 tmp = RREG32_SOC15(OSSSYS, 0, regIH_RETRY_INT_CAM_CNTL); 406 tmp = REG_SET_FIELD(tmp, IH_RETRY_INT_CAM_CNTL, ENABLE, 1); 407 tmp = REG_SET_FIELD(tmp, IH_RETRY_INT_CAM_CNTL, CAM_SIZE, 0xF); 408 WREG32_SOC15(OSSSYS, 0, regIH_RETRY_INT_CAM_CNTL, tmp); 409 410 adev->irq.retry_cam_enabled = true; 411 } 412 413 /* enable interrupts */ 414 ret = ih_v7_0_toggle_interrupts(adev, true); 415 if (ret) 416 return ret; 417 /* enable wptr force update for self int */ 418 force_update_wptr_for_self_int(adev, 0, 8, true); 419 420 if (adev->irq.ih_soft.ring_size) 421 adev->irq.ih_soft.enabled = true; 422 423 return 0; 424 } 425 426 /** 427 * ih_v7_0_irq_disable - disable interrupts 428 * 429 * @adev: amdgpu_device pointer 430 * 431 * Disable interrupts on the hw. 432 */ 433 static void ih_v7_0_irq_disable(struct amdgpu_device *adev) 434 { 435 force_update_wptr_for_self_int(adev, 0, 8, false); 436 ih_v7_0_toggle_interrupts(adev, false); 437 438 /* Wait and acknowledge irq */ 439 mdelay(1); 440 } 441 442 /** 443 * ih_v7_0_get_wptr() - get the IH ring buffer wptr 444 * 445 * @adev: amdgpu_device pointer 446 * @ih: IH ring buffer to fetch wptr 447 * 448 * Get the IH ring buffer wptr from either the register 449 * or the writeback memory buffer. Also check for 450 * ring buffer overflow and deal with it. 451 * Returns the value of the wptr. 452 */ 453 static u32 ih_v7_0_get_wptr(struct amdgpu_device *adev, 454 struct amdgpu_ih_ring *ih) 455 { 456 u32 wptr, tmp; 457 struct amdgpu_ih_regs *ih_regs; 458 459 wptr = le32_to_cpu(*ih->wptr_cpu); 460 ih_regs = &ih->ih_regs; 461 462 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 463 goto out; 464 465 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); 466 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 467 goto out; 468 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 469 470 /* When a ring buffer overflow happen start parsing interrupt 471 * from the last not overwritten vector (wptr + 32). Hopefully 472 * this should allow us to catch up. 473 */ 474 tmp = (wptr + 32) & ih->ptr_mask; 475 dev_warn(adev->dev, "IH ring buffer overflow " 476 "(0x%08X, 0x%08X, 0x%08X)\n", 477 wptr, ih->rptr, tmp); 478 ih->rptr = tmp; 479 480 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 481 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 482 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 483 484 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 485 * can be detected. 486 */ 487 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); 488 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 489 out: 490 return (wptr & ih->ptr_mask); 491 } 492 493 /** 494 * ih_v7_0_irq_rearm - rearm IRQ if lost 495 * 496 * @adev: amdgpu_device pointer 497 * @ih: IH ring to match 498 * 499 */ 500 static void ih_v7_0_irq_rearm(struct amdgpu_device *adev, 501 struct amdgpu_ih_ring *ih) 502 { 503 uint32_t v = 0; 504 uint32_t i = 0; 505 struct amdgpu_ih_regs *ih_regs; 506 507 ih_regs = &ih->ih_regs; 508 509 /* Rearm IRQ / re-write doorbell if doorbell write is lost */ 510 for (i = 0; i < MAX_REARM_RETRY; i++) { 511 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); 512 if ((v < ih->ring_size) && (v != ih->rptr)) 513 WDOORBELL32(ih->doorbell_index, ih->rptr); 514 else 515 break; 516 } 517 } 518 519 /** 520 * ih_v7_0_set_rptr - set the IH ring buffer rptr 521 * 522 * @adev: amdgpu_device pointer 523 * @ih: IH ring buffer to set rptr 524 */ 525 static void ih_v7_0_set_rptr(struct amdgpu_device *adev, 526 struct amdgpu_ih_ring *ih) 527 { 528 struct amdgpu_ih_regs *ih_regs; 529 530 if (ih->use_doorbell) { 531 /* XXX check if swapping is necessary on BE */ 532 *ih->rptr_cpu = ih->rptr; 533 WDOORBELL32(ih->doorbell_index, ih->rptr); 534 535 if (amdgpu_sriov_vf(adev)) 536 ih_v7_0_irq_rearm(adev, ih); 537 } else { 538 ih_regs = &ih->ih_regs; 539 WREG32(ih_regs->ih_rb_rptr, ih->rptr); 540 } 541 } 542 543 /** 544 * ih_v7_0_self_irq - dispatch work for ring 1 545 * 546 * @adev: amdgpu_device pointer 547 * @source: irq source 548 * @entry: IV with WPTR update 549 * 550 * Update the WPTR from the IV and schedule work to handle the entries. 551 */ 552 static int ih_v7_0_self_irq(struct amdgpu_device *adev, 553 struct amdgpu_irq_src *source, 554 struct amdgpu_iv_entry *entry) 555 { 556 uint32_t wptr = cpu_to_le32(entry->src_data[0]); 557 558 switch (entry->ring_id) { 559 case 1: 560 *adev->irq.ih1.wptr_cpu = wptr; 561 schedule_work(&adev->irq.ih1_work); 562 break; 563 default: break; 564 } 565 return 0; 566 } 567 568 static const struct amdgpu_irq_src_funcs ih_v7_0_self_irq_funcs = { 569 .process = ih_v7_0_self_irq, 570 }; 571 572 static void ih_v7_0_set_self_irq_funcs(struct amdgpu_device *adev) 573 { 574 adev->irq.self_irq.num_types = 0; 575 adev->irq.self_irq.funcs = &ih_v7_0_self_irq_funcs; 576 } 577 578 static int ih_v7_0_early_init(struct amdgpu_ip_block *ip_block) 579 { 580 struct amdgpu_device *adev = ip_block->adev; 581 582 ih_v7_0_set_interrupt_funcs(adev); 583 ih_v7_0_set_self_irq_funcs(adev); 584 return 0; 585 } 586 587 static int ih_v7_0_sw_init(struct amdgpu_ip_block *ip_block) 588 { 589 int r; 590 struct amdgpu_device *adev = ip_block->adev; 591 bool use_bus_addr; 592 unsigned int sw_ring_size; 593 594 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_IH, 0, 595 &adev->irq.self_irq); 596 597 if (r) 598 return r; 599 600 /* use gpu virtual address for ih ring 601 * until ih_checken is programmed to allow 602 * use bus address for ih ring by psp bl */ 603 use_bus_addr = adev->firmware.load_type != AMDGPU_FW_LOAD_PSP; 604 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr); 605 if (r) 606 return r; 607 608 adev->irq.ih.use_doorbell = true; 609 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; 610 611 if (!(adev->flags & AMD_IS_APU)) { 612 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE, 613 use_bus_addr); 614 if (r) 615 return r; 616 617 adev->irq.ih1.use_doorbell = true; 618 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; 619 } 620 621 /* initialize ih control register offset */ 622 ih_v7_0_init_register_offset(adev); 623 624 sw_ring_size = (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(7, 1, 0)) ? 625 IH_SW_RING_SIZE : PAGE_SIZE; 626 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, sw_ring_size, true); 627 if (r) 628 return r; 629 630 r = amdgpu_irq_init(adev); 631 632 return r; 633 } 634 635 static int ih_v7_0_sw_fini(struct amdgpu_ip_block *ip_block) 636 { 637 struct amdgpu_device *adev = ip_block->adev; 638 639 amdgpu_irq_fini_sw(adev); 640 641 return 0; 642 } 643 644 static int ih_v7_0_hw_init(struct amdgpu_ip_block *ip_block) 645 { 646 int r; 647 struct amdgpu_device *adev = ip_block->adev; 648 649 r = ih_v7_0_irq_init(adev); 650 if (r) 651 return r; 652 653 return 0; 654 } 655 656 static int ih_v7_0_hw_fini(struct amdgpu_ip_block *ip_block) 657 { 658 ih_v7_0_irq_disable(ip_block->adev); 659 660 return 0; 661 } 662 663 static int ih_v7_0_suspend(struct amdgpu_ip_block *ip_block) 664 { 665 return ih_v7_0_hw_fini(ip_block); 666 } 667 668 static int ih_v7_0_resume(struct amdgpu_ip_block *ip_block) 669 { 670 return ih_v7_0_hw_init(ip_block); 671 } 672 673 static bool ih_v7_0_is_idle(struct amdgpu_ip_block *ip_block) 674 { 675 /* todo */ 676 return true; 677 } 678 679 static int ih_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 680 { 681 /* todo */ 682 return -ETIMEDOUT; 683 } 684 685 static int ih_v7_0_soft_reset(struct amdgpu_ip_block *ip_block) 686 { 687 /* todo */ 688 return 0; 689 } 690 691 static void ih_v7_0_update_clockgating_state(struct amdgpu_device *adev, 692 bool enable) 693 { 694 uint32_t data, def, field_val; 695 696 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { 697 def = data = RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL); 698 field_val = enable ? 0 : 1; 699 data = REG_SET_FIELD(data, IH_CLK_CTRL, 700 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); 701 data = REG_SET_FIELD(data, IH_CLK_CTRL, 702 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); 703 data = REG_SET_FIELD(data, IH_CLK_CTRL, 704 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); 705 data = REG_SET_FIELD(data, IH_CLK_CTRL, 706 DYN_CLK_SOFT_OVERRIDE, field_val); 707 data = REG_SET_FIELD(data, IH_CLK_CTRL, 708 REG_CLK_SOFT_OVERRIDE, field_val); 709 if (def != data) 710 WREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL, data); 711 } 712 713 return; 714 } 715 716 static int ih_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 717 enum amd_clockgating_state state) 718 { 719 struct amdgpu_device *adev = ip_block->adev; 720 721 ih_v7_0_update_clockgating_state(adev, 722 state == AMD_CG_STATE_GATE); 723 return 0; 724 } 725 726 static void ih_v7_0_update_ih_mem_power_gating(struct amdgpu_device *adev, 727 bool enable) 728 { 729 uint32_t ih_mem_pwr_cntl; 730 731 /* Disable ih sram power cntl before switch powergating mode */ 732 ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL); 733 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 734 IH_BUFFER_MEM_POWER_CTRL_EN, 0); 735 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl); 736 737 /* It is recommended to set mem powergating mode to DS mode */ 738 if (enable) { 739 /* mem power mode */ 740 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 741 IH_BUFFER_MEM_POWER_LS_EN, 0); 742 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 743 IH_BUFFER_MEM_POWER_DS_EN, 1); 744 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 745 IH_BUFFER_MEM_POWER_SD_EN, 0); 746 /* cam mem power mode */ 747 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 748 IH_RETRY_INT_CAM_MEM_POWER_LS_EN, 0); 749 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 750 IH_RETRY_INT_CAM_MEM_POWER_DS_EN, 1); 751 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 752 IH_RETRY_INT_CAM_MEM_POWER_SD_EN, 0); 753 /* re-enable power cntl */ 754 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 755 IH_BUFFER_MEM_POWER_CTRL_EN, 1); 756 } else { 757 /* mem power mode */ 758 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 759 IH_BUFFER_MEM_POWER_LS_EN, 0); 760 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 761 IH_BUFFER_MEM_POWER_DS_EN, 0); 762 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 763 IH_BUFFER_MEM_POWER_SD_EN, 0); 764 /* cam mem power mode */ 765 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 766 IH_RETRY_INT_CAM_MEM_POWER_LS_EN, 0); 767 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 768 IH_RETRY_INT_CAM_MEM_POWER_DS_EN, 0); 769 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 770 IH_RETRY_INT_CAM_MEM_POWER_SD_EN, 0); 771 /* re-enable power cntl*/ 772 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL, 773 IH_BUFFER_MEM_POWER_CTRL_EN, 1); 774 } 775 776 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl); 777 } 778 779 static int ih_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 780 enum amd_powergating_state state) 781 { 782 struct amdgpu_device *adev = ip_block->adev; 783 bool enable = (state == AMD_PG_STATE_GATE); 784 785 if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG) 786 ih_v7_0_update_ih_mem_power_gating(adev, enable); 787 788 return 0; 789 } 790 791 static void ih_v7_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 792 { 793 struct amdgpu_device *adev = ip_block->adev; 794 795 if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL)) 796 *flags |= AMD_CG_SUPPORT_IH_CG; 797 798 return; 799 } 800 801 static const struct amd_ip_funcs ih_v7_0_ip_funcs = { 802 .name = "ih_v7_0", 803 .early_init = ih_v7_0_early_init, 804 .sw_init = ih_v7_0_sw_init, 805 .sw_fini = ih_v7_0_sw_fini, 806 .hw_init = ih_v7_0_hw_init, 807 .hw_fini = ih_v7_0_hw_fini, 808 .suspend = ih_v7_0_suspend, 809 .resume = ih_v7_0_resume, 810 .is_idle = ih_v7_0_is_idle, 811 .wait_for_idle = ih_v7_0_wait_for_idle, 812 .soft_reset = ih_v7_0_soft_reset, 813 .set_clockgating_state = ih_v7_0_set_clockgating_state, 814 .set_powergating_state = ih_v7_0_set_powergating_state, 815 .get_clockgating_state = ih_v7_0_get_clockgating_state, 816 }; 817 818 static const struct amdgpu_ih_funcs ih_v7_0_funcs = { 819 .get_wptr = ih_v7_0_get_wptr, 820 .decode_iv = amdgpu_ih_decode_iv_helper, 821 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper, 822 .set_rptr = ih_v7_0_set_rptr 823 }; 824 825 static void ih_v7_0_set_interrupt_funcs(struct amdgpu_device *adev) 826 { 827 adev->irq.ih_funcs = &ih_v7_0_funcs; 828 } 829 830 const struct amdgpu_ip_block_version ih_v7_0_ip_block = 831 { 832 .type = AMD_IP_BLOCK_TYPE_IH, 833 .major = 7, 834 .minor = 0, 835 .rev = 0, 836 .funcs = &ih_v7_0_ip_funcs, 837 }; 838