1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "vid.h" 29 30 #include "oss/oss_2_4_d.h" 31 #include "oss/oss_2_4_sh_mask.h" 32 33 #include "bif/bif_5_1_d.h" 34 #include "bif/bif_5_1_sh_mask.h" 35 36 /* 37 * Interrupts 38 * Starting with r6xx, interrupts are handled via a ring buffer. 39 * Ring buffers are areas of GPU accessible memory that the GPU 40 * writes interrupt vectors into and the host reads vectors out of. 41 * There is a rptr (read pointer) that determines where the 42 * host is currently reading, and a wptr (write pointer) 43 * which determines where the GPU has written. When the 44 * pointers are equal, the ring is idle. When the GPU 45 * writes vectors to the ring buffer, it increments the 46 * wptr. When there is an interrupt, the host then starts 47 * fetching commands and processing them until the pointers are 48 * equal again at which point it updates the rptr. 49 */ 50 51 static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev); 52 53 /** 54 * iceland_ih_enable_interrupts - Enable the interrupt ring buffer 55 * 56 * @adev: amdgpu_device pointer 57 * 58 * Enable the interrupt ring buffer (VI). 59 */ 60 static void iceland_ih_enable_interrupts(struct amdgpu_device *adev) 61 { 62 u32 ih_cntl = RREG32(mmIH_CNTL); 63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 64 65 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); 66 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 67 WREG32(mmIH_CNTL, ih_cntl); 68 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 69 adev->irq.ih.enabled = true; 70 } 71 72 /** 73 * iceland_ih_disable_interrupts - Disable the interrupt ring buffer 74 * 75 * @adev: amdgpu_device pointer 76 * 77 * Disable the interrupt ring buffer (VI). 78 */ 79 static void iceland_ih_disable_interrupts(struct amdgpu_device *adev) 80 { 81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 82 u32 ih_cntl = RREG32(mmIH_CNTL); 83 84 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 85 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); 86 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 87 WREG32(mmIH_CNTL, ih_cntl); 88 /* set rptr, wptr to 0 */ 89 WREG32(mmIH_RB_RPTR, 0); 90 WREG32(mmIH_RB_WPTR, 0); 91 adev->irq.ih.enabled = false; 92 adev->irq.ih.rptr = 0; 93 } 94 95 /** 96 * iceland_ih_irq_init - init and enable the interrupt ring 97 * 98 * @adev: amdgpu_device pointer 99 * 100 * Allocate a ring buffer for the interrupt controller, 101 * enable the RLC, disable interrupts, enable the IH 102 * ring buffer and enable it (VI). 103 * Called at device load and reume. 104 * Returns 0 for success, errors for failure. 105 */ 106 static int iceland_ih_irq_init(struct amdgpu_device *adev) 107 { 108 struct amdgpu_ih_ring *ih = &adev->irq.ih; 109 int rb_bufsz; 110 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 111 112 /* disable irqs */ 113 iceland_ih_disable_interrupts(adev); 114 115 /* setup interrupt control */ 116 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); 118 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 119 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 120 */ 121 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 122 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 123 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 124 WREG32(mmINTERRUPT_CNTL, interrupt_cntl); 125 126 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 127 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 128 129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 130 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); 131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 133 134 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ 135 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); 136 137 /* set the writeback address whether it's enabled or not */ 138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); 139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); 140 141 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 142 143 /* set rptr, wptr to 0 */ 144 WREG32(mmIH_RB_RPTR, 0); 145 WREG32(mmIH_RB_WPTR, 0); 146 147 /* Default settings for IH_CNTL (disabled at first) */ 148 ih_cntl = RREG32(mmIH_CNTL); 149 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); 150 151 if (adev->irq.msi_enabled) 152 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); 153 WREG32(mmIH_CNTL, ih_cntl); 154 155 pci_set_master(adev->pdev); 156 157 /* enable interrupts */ 158 iceland_ih_enable_interrupts(adev); 159 160 if (adev->irq.ih_soft.ring_size) 161 adev->irq.ih_soft.enabled = true; 162 163 return 0; 164 } 165 166 /** 167 * iceland_ih_irq_disable - disable interrupts 168 * 169 * @adev: amdgpu_device pointer 170 * 171 * Disable interrupts on the hw (VI). 172 */ 173 static void iceland_ih_irq_disable(struct amdgpu_device *adev) 174 { 175 iceland_ih_disable_interrupts(adev); 176 177 /* Wait and acknowledge irq */ 178 mdelay(1); 179 } 180 181 /** 182 * iceland_ih_get_wptr - get the IH ring buffer wptr 183 * 184 * @adev: amdgpu_device pointer 185 * @ih: IH ring buffer to fetch wptr 186 * 187 * Get the IH ring buffer wptr from either the register 188 * or the writeback memory buffer (VI). Also check for 189 * ring buffer overflow and deal with it. 190 * Used by cz_irq_process(VI). 191 * Returns the value of the wptr. 192 */ 193 static u32 iceland_ih_get_wptr(struct amdgpu_device *adev, 194 struct amdgpu_ih_ring *ih) 195 { 196 u32 wptr, tmp; 197 198 wptr = le32_to_cpu(*ih->wptr_cpu); 199 200 if (ih == &adev->irq.ih_soft) 201 goto out; 202 203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 204 goto out; 205 206 /* Double check that the overflow wasn't already cleared. */ 207 wptr = RREG32(mmIH_RB_WPTR); 208 209 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 210 goto out; 211 212 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 213 /* When a ring buffer overflow happen start parsing interrupt 214 * from the last not overwritten vector (wptr + 16). Hopefully 215 * this should allow us to catchup. 216 */ 217 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 218 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); 219 ih->rptr = (wptr + 16) & ih->ptr_mask; 220 tmp = RREG32(mmIH_RB_CNTL); 221 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 222 WREG32(mmIH_RB_CNTL, tmp); 223 224 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 225 * can be detected. 226 */ 227 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); 228 WREG32(mmIH_RB_CNTL, tmp); 229 230 out: 231 return (wptr & ih->ptr_mask); 232 } 233 234 /** 235 * iceland_ih_decode_iv - decode an interrupt vector 236 * 237 * @adev: amdgpu_device pointer 238 * @ih: IH ring buffer to decode 239 * @entry: IV entry to place decoded information into 240 * 241 * Decodes the interrupt vector at the current rptr 242 * position and also advance the position. 243 */ 244 static void iceland_ih_decode_iv(struct amdgpu_device *adev, 245 struct amdgpu_ih_ring *ih, 246 struct amdgpu_iv_entry *entry) 247 { 248 /* wptr/rptr are in bytes! */ 249 u32 ring_index = ih->rptr >> 2; 250 uint32_t dw[4]; 251 252 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 253 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 254 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 255 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 256 257 entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 258 entry->src_id = dw[0] & 0xff; 259 entry->src_data[0] = dw[1] & 0xfffffff; 260 entry->ring_id = dw[2] & 0xff; 261 entry->vmid = (dw[2] >> 8) & 0xff; 262 entry->pasid = (dw[2] >> 16) & 0xffff; 263 264 /* wptr/rptr are in bytes! */ 265 ih->rptr += 16; 266 } 267 268 /** 269 * iceland_ih_set_rptr - set the IH ring buffer rptr 270 * 271 * @adev: amdgpu_device pointer 272 * @ih: IH ring buffer to set rptr 273 * 274 * Set the IH ring buffer rptr. 275 */ 276 static void iceland_ih_set_rptr(struct amdgpu_device *adev, 277 struct amdgpu_ih_ring *ih) 278 { 279 WREG32(mmIH_RB_RPTR, ih->rptr); 280 } 281 282 static int iceland_ih_early_init(struct amdgpu_ip_block *ip_block) 283 { 284 struct amdgpu_device *adev = ip_block->adev; 285 int ret; 286 287 ret = amdgpu_irq_add_domain(adev); 288 if (ret) 289 return ret; 290 291 iceland_ih_set_interrupt_funcs(adev); 292 293 return 0; 294 } 295 296 static int iceland_ih_sw_init(struct amdgpu_ip_block *ip_block) 297 { 298 int r; 299 struct amdgpu_device *adev = ip_block->adev; 300 301 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); 302 if (r) 303 return r; 304 305 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true); 306 if (r) 307 return r; 308 309 r = amdgpu_irq_init(adev); 310 311 return r; 312 } 313 314 static int iceland_ih_sw_fini(struct amdgpu_ip_block *ip_block) 315 { 316 struct amdgpu_device *adev = ip_block->adev; 317 318 amdgpu_irq_fini_sw(adev); 319 amdgpu_irq_remove_domain(adev); 320 321 return 0; 322 } 323 324 static int iceland_ih_hw_init(struct amdgpu_ip_block *ip_block) 325 { 326 struct amdgpu_device *adev = ip_block->adev; 327 328 return iceland_ih_irq_init(adev); 329 } 330 331 static int iceland_ih_hw_fini(struct amdgpu_ip_block *ip_block) 332 { 333 iceland_ih_irq_disable(ip_block->adev); 334 335 return 0; 336 } 337 338 static int iceland_ih_suspend(struct amdgpu_ip_block *ip_block) 339 { 340 return iceland_ih_hw_fini(ip_block); 341 } 342 343 static int iceland_ih_resume(struct amdgpu_ip_block *ip_block) 344 { 345 return iceland_ih_hw_init(ip_block); 346 } 347 348 static bool iceland_ih_is_idle(struct amdgpu_ip_block *ip_block) 349 { 350 struct amdgpu_device *adev = ip_block->adev; 351 u32 tmp = RREG32(mmSRBM_STATUS); 352 353 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 354 return false; 355 356 return true; 357 } 358 359 static int iceland_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) 360 { 361 unsigned i; 362 u32 tmp; 363 struct amdgpu_device *adev = ip_block->adev; 364 365 for (i = 0; i < adev->usec_timeout; i++) { 366 /* read MC_STATUS */ 367 tmp = RREG32(mmSRBM_STATUS); 368 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 369 return 0; 370 udelay(1); 371 } 372 return -ETIMEDOUT; 373 } 374 375 static int iceland_ih_soft_reset(struct amdgpu_ip_block *ip_block) 376 { 377 u32 srbm_soft_reset = 0; 378 struct amdgpu_device *adev = ip_block->adev; 379 u32 tmp = RREG32(mmSRBM_STATUS); 380 381 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 382 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, 383 SOFT_RESET_IH, 1); 384 385 if (srbm_soft_reset) { 386 tmp = RREG32(mmSRBM_SOFT_RESET); 387 tmp |= srbm_soft_reset; 388 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 389 WREG32(mmSRBM_SOFT_RESET, tmp); 390 tmp = RREG32(mmSRBM_SOFT_RESET); 391 392 udelay(50); 393 394 tmp &= ~srbm_soft_reset; 395 WREG32(mmSRBM_SOFT_RESET, tmp); 396 tmp = RREG32(mmSRBM_SOFT_RESET); 397 398 /* Wait a little for things to settle down */ 399 udelay(50); 400 } 401 402 return 0; 403 } 404 405 static int iceland_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block, 406 enum amd_clockgating_state state) 407 { 408 return 0; 409 } 410 411 static int iceland_ih_set_powergating_state(struct amdgpu_ip_block *ip_block, 412 enum amd_powergating_state state) 413 { 414 return 0; 415 } 416 417 static const struct amd_ip_funcs iceland_ih_ip_funcs = { 418 .name = "iceland_ih", 419 .early_init = iceland_ih_early_init, 420 .sw_init = iceland_ih_sw_init, 421 .sw_fini = iceland_ih_sw_fini, 422 .hw_init = iceland_ih_hw_init, 423 .hw_fini = iceland_ih_hw_fini, 424 .suspend = iceland_ih_suspend, 425 .resume = iceland_ih_resume, 426 .is_idle = iceland_ih_is_idle, 427 .wait_for_idle = iceland_ih_wait_for_idle, 428 .soft_reset = iceland_ih_soft_reset, 429 .set_clockgating_state = iceland_ih_set_clockgating_state, 430 .set_powergating_state = iceland_ih_set_powergating_state, 431 }; 432 433 static const struct amdgpu_ih_funcs iceland_ih_funcs = { 434 .get_wptr = iceland_ih_get_wptr, 435 .decode_iv = iceland_ih_decode_iv, 436 .set_rptr = iceland_ih_set_rptr 437 }; 438 439 static void iceland_ih_set_interrupt_funcs(struct amdgpu_device *adev) 440 { 441 adev->irq.ih_funcs = &iceland_ih_funcs; 442 } 443 444 const struct amdgpu_ip_block_version iceland_ih_ip_block = 445 { 446 .type = AMD_IP_BLOCK_TYPE_IH, 447 .major = 2, 448 .minor = 4, 449 .rev = 0, 450 .funcs = &iceland_ih_ip_funcs, 451 }; 452