1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "hdp_v7_0.h" 25 26 #include "hdp/hdp_7_0_0_offset.h" 27 #include "hdp/hdp_7_0_0_sh_mask.h" 28 #include <uapi/linux/kfd_ioctl.h> 29 30 static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev, 31 struct amdgpu_ring *ring) 32 { 33 if (!ring || !ring->funcs->emit_wreg) { 34 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 35 /* We just need to read back a register to post the write. 36 * Reading back the remapped register causes problems on 37 * some platforms so just read back the memory size register. 38 */ 39 if (adev->nbio.funcs->get_memsize) 40 adev->nbio.funcs->get_memsize(adev); 41 } else { 42 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 43 } 44 } 45 46 static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev, 47 bool enable) 48 { 49 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 50 uint32_t hdp_mem_pwr_cntl; 51 52 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 53 AMD_CG_SUPPORT_HDP_DS | 54 AMD_CG_SUPPORT_HDP_SD))) 55 return; 56 57 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL); 58 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); 59 60 /* Before doing clock/power mode switch, 61 * forced on IPH & RC clock */ 62 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 63 RC_MEM_CLK_SOFT_OVERRIDE, 1); 64 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); 65 66 /* disable clock and power gating before any changing */ 67 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 68 ATOMIC_MEM_POWER_CTRL_EN, 0); 69 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 70 ATOMIC_MEM_POWER_LS_EN, 0); 71 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 72 ATOMIC_MEM_POWER_DS_EN, 0); 73 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 74 ATOMIC_MEM_POWER_SD_EN, 0); 75 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 76 RC_MEM_POWER_CTRL_EN, 0); 77 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 78 RC_MEM_POWER_LS_EN, 0); 79 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 80 RC_MEM_POWER_DS_EN, 0); 81 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 82 RC_MEM_POWER_SD_EN, 0); 83 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 84 85 /* Already disabled above. The actions below are for "enabled" only */ 86 if (enable) { 87 /* only one clock gating mode (LS/DS/SD) can be enabled */ 88 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 89 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 90 HDP_MEM_POWER_CTRL, 91 ATOMIC_MEM_POWER_SD_EN, 1); 92 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 93 HDP_MEM_POWER_CTRL, 94 RC_MEM_POWER_SD_EN, 1); 95 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 96 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 97 HDP_MEM_POWER_CTRL, 98 ATOMIC_MEM_POWER_LS_EN, 1); 99 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 100 HDP_MEM_POWER_CTRL, 101 RC_MEM_POWER_LS_EN, 1); 102 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 103 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 104 HDP_MEM_POWER_CTRL, 105 ATOMIC_MEM_POWER_DS_EN, 1); 106 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 107 HDP_MEM_POWER_CTRL, 108 RC_MEM_POWER_DS_EN, 1); 109 } 110 111 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 112 * be set for SRAM LS/DS/SD */ 113 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 114 AMD_CG_SUPPORT_HDP_SD)) { 115 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 116 ATOMIC_MEM_POWER_CTRL_EN, 1); 117 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 118 RC_MEM_POWER_CTRL_EN, 1); 119 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 120 } 121 } 122 123 /* disable IPH & RC clock override after clock/power mode changing */ 124 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 125 RC_MEM_CLK_SOFT_OVERRIDE, 0); 126 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); 127 } 128 129 static void hdp_v7_0_get_clockgating_state(struct amdgpu_device *adev, 130 u64 *flags) 131 { 132 uint32_t tmp; 133 134 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 135 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); 136 if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK) 137 *flags |= AMD_CG_SUPPORT_HDP_LS; 138 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK) 139 *flags |= AMD_CG_SUPPORT_HDP_DS; 140 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK) 141 *flags |= AMD_CG_SUPPORT_HDP_SD; 142 } 143 144 const struct amdgpu_hdp_funcs hdp_v7_0_funcs = { 145 .flush_hdp = hdp_v7_0_flush_hdp, 146 .update_clock_gating = hdp_v7_0_update_clock_gating, 147 .get_clock_gating_state = hdp_v7_0_get_clockgating_state, 148 }; 149