1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "hdp_v7_0.h" 26 27 #include "hdp/hdp_7_0_0_offset.h" 28 #include "hdp/hdp_7_0_0_sh_mask.h" 29 #include <uapi/linux/kfd_ioctl.h> 30 31 static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev, 32 struct amdgpu_ring *ring) 33 { 34 if (!ring || !ring->funcs->emit_wreg) { 35 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 36 RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); 37 } else { 38 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 39 } 40 } 41 42 static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev, 43 bool enable) 44 { 45 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 46 uint32_t hdp_mem_pwr_cntl; 47 48 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 49 AMD_CG_SUPPORT_HDP_DS | 50 AMD_CG_SUPPORT_HDP_SD))) 51 return; 52 53 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL); 54 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); 55 56 /* Before doing clock/power mode switch, 57 * forced on IPH & RC clock */ 58 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 59 RC_MEM_CLK_SOFT_OVERRIDE, 1); 60 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); 61 62 /* disable clock and power gating before any changing */ 63 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 64 ATOMIC_MEM_POWER_CTRL_EN, 0); 65 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 66 ATOMIC_MEM_POWER_LS_EN, 0); 67 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 68 ATOMIC_MEM_POWER_DS_EN, 0); 69 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 70 ATOMIC_MEM_POWER_SD_EN, 0); 71 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 72 RC_MEM_POWER_CTRL_EN, 0); 73 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 74 RC_MEM_POWER_LS_EN, 0); 75 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 76 RC_MEM_POWER_DS_EN, 0); 77 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 78 RC_MEM_POWER_SD_EN, 0); 79 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 80 81 /* Already disabled above. The actions below are for "enabled" only */ 82 if (enable) { 83 /* only one clock gating mode (LS/DS/SD) can be enabled */ 84 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 85 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 86 HDP_MEM_POWER_CTRL, 87 ATOMIC_MEM_POWER_SD_EN, 1); 88 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 89 HDP_MEM_POWER_CTRL, 90 RC_MEM_POWER_SD_EN, 1); 91 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 92 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 93 HDP_MEM_POWER_CTRL, 94 ATOMIC_MEM_POWER_LS_EN, 1); 95 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 96 HDP_MEM_POWER_CTRL, 97 RC_MEM_POWER_LS_EN, 1); 98 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 99 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 100 HDP_MEM_POWER_CTRL, 101 ATOMIC_MEM_POWER_DS_EN, 1); 102 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 103 HDP_MEM_POWER_CTRL, 104 RC_MEM_POWER_DS_EN, 1); 105 } 106 107 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 108 * be set for SRAM LS/DS/SD */ 109 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 110 AMD_CG_SUPPORT_HDP_SD)) { 111 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 112 ATOMIC_MEM_POWER_CTRL_EN, 1); 113 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 114 RC_MEM_POWER_CTRL_EN, 1); 115 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 116 } 117 } 118 119 /* disable IPH & RC clock override after clock/power mode changing */ 120 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 121 RC_MEM_CLK_SOFT_OVERRIDE, 0); 122 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); 123 } 124 125 static void hdp_v7_0_get_clockgating_state(struct amdgpu_device *adev, 126 u64 *flags) 127 { 128 uint32_t tmp; 129 130 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 131 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); 132 if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK) 133 *flags |= AMD_CG_SUPPORT_HDP_LS; 134 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK) 135 *flags |= AMD_CG_SUPPORT_HDP_DS; 136 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK) 137 *flags |= AMD_CG_SUPPORT_HDP_SD; 138 } 139 140 const struct amdgpu_hdp_funcs hdp_v7_0_funcs = { 141 .flush_hdp = hdp_v7_0_flush_hdp, 142 .update_clock_gating = hdp_v7_0_update_clock_gating, 143 .get_clock_gating_state = hdp_v7_0_get_clockgating_state, 144 }; 145