1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "hdp_v7_0.h" 25 26 #include "hdp/hdp_7_0_0_offset.h" 27 #include "hdp/hdp_7_0_0_sh_mask.h" 28 #include <uapi/linux/kfd_ioctl.h> 29 30 static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev, 31 struct amdgpu_ring *ring) 32 { 33 if (!ring || !ring->funcs->emit_wreg) { 34 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 35 RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); 36 } else { 37 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 38 } 39 } 40 41 static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev, 42 bool enable) 43 { 44 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 45 uint32_t hdp_mem_pwr_cntl; 46 47 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 48 AMD_CG_SUPPORT_HDP_DS | 49 AMD_CG_SUPPORT_HDP_SD))) 50 return; 51 52 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL); 53 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); 54 55 /* Before doing clock/power mode switch, 56 * forced on IPH & RC clock */ 57 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 58 RC_MEM_CLK_SOFT_OVERRIDE, 1); 59 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); 60 61 /* disable clock and power gating before any changing */ 62 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 63 ATOMIC_MEM_POWER_CTRL_EN, 0); 64 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 65 ATOMIC_MEM_POWER_LS_EN, 0); 66 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 67 ATOMIC_MEM_POWER_DS_EN, 0); 68 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 69 ATOMIC_MEM_POWER_SD_EN, 0); 70 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 71 RC_MEM_POWER_CTRL_EN, 0); 72 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 73 RC_MEM_POWER_LS_EN, 0); 74 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 75 RC_MEM_POWER_DS_EN, 0); 76 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 77 RC_MEM_POWER_SD_EN, 0); 78 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 79 80 /* Already disabled above. The actions below are for "enabled" only */ 81 if (enable) { 82 /* only one clock gating mode (LS/DS/SD) can be enabled */ 83 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 84 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 85 HDP_MEM_POWER_CTRL, 86 ATOMIC_MEM_POWER_SD_EN, 1); 87 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 88 HDP_MEM_POWER_CTRL, 89 RC_MEM_POWER_SD_EN, 1); 90 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 91 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 92 HDP_MEM_POWER_CTRL, 93 ATOMIC_MEM_POWER_LS_EN, 1); 94 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 95 HDP_MEM_POWER_CTRL, 96 RC_MEM_POWER_LS_EN, 1); 97 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 98 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 99 HDP_MEM_POWER_CTRL, 100 ATOMIC_MEM_POWER_DS_EN, 1); 101 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 102 HDP_MEM_POWER_CTRL, 103 RC_MEM_POWER_DS_EN, 1); 104 } 105 106 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 107 * be set for SRAM LS/DS/SD */ 108 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 109 AMD_CG_SUPPORT_HDP_SD)) { 110 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 111 ATOMIC_MEM_POWER_CTRL_EN, 1); 112 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 113 RC_MEM_POWER_CTRL_EN, 1); 114 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 115 } 116 } 117 118 /* disable IPH & RC clock override after clock/power mode changing */ 119 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 120 RC_MEM_CLK_SOFT_OVERRIDE, 0); 121 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); 122 } 123 124 static void hdp_v7_0_get_clockgating_state(struct amdgpu_device *adev, 125 u64 *flags) 126 { 127 uint32_t tmp; 128 129 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 130 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); 131 if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK) 132 *flags |= AMD_CG_SUPPORT_HDP_LS; 133 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK) 134 *flags |= AMD_CG_SUPPORT_HDP_DS; 135 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK) 136 *flags |= AMD_CG_SUPPORT_HDP_SD; 137 } 138 139 const struct amdgpu_hdp_funcs hdp_v7_0_funcs = { 140 .flush_hdp = hdp_v7_0_flush_hdp, 141 .update_clock_gating = hdp_v7_0_update_clock_gating, 142 .get_clock_gating_state = hdp_v7_0_get_clockgating_state, 143 }; 144