1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "hdp_v6_0.h" 25 26 #include "hdp/hdp_6_0_0_offset.h" 27 #include "hdp/hdp_6_0_0_sh_mask.h" 28 #include <uapi/linux/kfd_ioctl.h> 29 30 #define regHDP_CLK_CNTL_V6_1 0xd5 31 #define regHDP_CLK_CNTL_V6_1_BASE_IDX 0 32 33 static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev, 34 bool enable) 35 { 36 uint32_t hdp_clk_cntl; 37 uint32_t hdp_mem_pwr_cntl; 38 39 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 40 AMD_CG_SUPPORT_HDP_DS | 41 AMD_CG_SUPPORT_HDP_SD))) 42 return; 43 44 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0)) 45 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1); 46 else 47 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); 48 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); 49 50 /* Before doing clock/power mode switch, 51 * forced on IPH & RC clock */ 52 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 53 RC_MEM_CLK_SOFT_OVERRIDE, 1); 54 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0)) 55 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); 56 else 57 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); 58 59 /* disable clock and power gating before any changing */ 60 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 61 ATOMIC_MEM_POWER_CTRL_EN, 0); 62 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 63 ATOMIC_MEM_POWER_LS_EN, 0); 64 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 65 ATOMIC_MEM_POWER_DS_EN, 0); 66 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 67 ATOMIC_MEM_POWER_SD_EN, 0); 68 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 69 RC_MEM_POWER_CTRL_EN, 0); 70 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 71 RC_MEM_POWER_LS_EN, 0); 72 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 73 RC_MEM_POWER_DS_EN, 0); 74 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 75 RC_MEM_POWER_SD_EN, 0); 76 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 77 78 /* Already disabled above. The actions below are for "enabled" only */ 79 if (enable) { 80 /* only one clock gating mode (LS/DS/SD) can be enabled */ 81 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 82 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 83 HDP_MEM_POWER_CTRL, 84 ATOMIC_MEM_POWER_SD_EN, 1); 85 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 86 HDP_MEM_POWER_CTRL, 87 RC_MEM_POWER_SD_EN, 1); 88 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 89 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 90 HDP_MEM_POWER_CTRL, 91 ATOMIC_MEM_POWER_LS_EN, 1); 92 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 93 HDP_MEM_POWER_CTRL, 94 RC_MEM_POWER_LS_EN, 1); 95 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 96 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 97 HDP_MEM_POWER_CTRL, 98 ATOMIC_MEM_POWER_DS_EN, 1); 99 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 100 HDP_MEM_POWER_CTRL, 101 RC_MEM_POWER_DS_EN, 1); 102 } 103 104 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 105 * be set for SRAM LS/DS/SD */ 106 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 107 AMD_CG_SUPPORT_HDP_SD)) { 108 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 109 ATOMIC_MEM_POWER_CTRL_EN, 1); 110 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 111 RC_MEM_POWER_CTRL_EN, 1); 112 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 113 } 114 } 115 116 /* disable IPH & RC clock override after clock/power mode changing */ 117 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 118 RC_MEM_CLK_SOFT_OVERRIDE, 0); 119 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0)) 120 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); 121 else 122 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); 123 } 124 125 static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev, 126 u64 *flags) 127 { 128 uint32_t tmp; 129 130 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 131 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); 132 if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK) 133 *flags |= AMD_CG_SUPPORT_HDP_LS; 134 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK) 135 *flags |= AMD_CG_SUPPORT_HDP_DS; 136 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK) 137 *flags |= AMD_CG_SUPPORT_HDP_SD; 138 } 139 140 const struct amdgpu_hdp_funcs hdp_v6_0_funcs = { 141 .flush_hdp = amdgpu_hdp_generic_flush, 142 .update_clock_gating = hdp_v6_0_update_clock_gating, 143 .get_clock_gating_state = hdp_v6_0_get_clockgating_state, 144 }; 145