1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "hdp_v6_0.h" 25 26 #include "hdp/hdp_6_0_0_offset.h" 27 #include "hdp/hdp_6_0_0_sh_mask.h" 28 #include <uapi/linux/kfd_ioctl.h> 29 30 #define regHDP_CLK_CNTL_V6_1 0xd5 31 #define regHDP_CLK_CNTL_V6_1_BASE_IDX 0 32 33 static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev, 34 struct amdgpu_ring *ring) 35 { 36 if (!ring || !ring->funcs->emit_wreg) { 37 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 38 RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); 39 } else { 40 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 41 } 42 } 43 44 static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev, 45 bool enable) 46 { 47 uint32_t hdp_clk_cntl; 48 uint32_t hdp_mem_pwr_cntl; 49 50 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 51 AMD_CG_SUPPORT_HDP_DS | 52 AMD_CG_SUPPORT_HDP_SD))) 53 return; 54 55 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0)) 56 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1); 57 else 58 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); 59 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); 60 61 /* Before doing clock/power mode switch, 62 * forced on IPH & RC clock */ 63 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 64 RC_MEM_CLK_SOFT_OVERRIDE, 1); 65 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0)) 66 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); 67 else 68 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); 69 70 /* disable clock and power gating before any changing */ 71 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 72 ATOMIC_MEM_POWER_CTRL_EN, 0); 73 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 74 ATOMIC_MEM_POWER_LS_EN, 0); 75 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 76 ATOMIC_MEM_POWER_DS_EN, 0); 77 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 78 ATOMIC_MEM_POWER_SD_EN, 0); 79 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 80 RC_MEM_POWER_CTRL_EN, 0); 81 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 82 RC_MEM_POWER_LS_EN, 0); 83 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 84 RC_MEM_POWER_DS_EN, 0); 85 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 86 RC_MEM_POWER_SD_EN, 0); 87 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 88 89 /* Already disabled above. The actions below are for "enabled" only */ 90 if (enable) { 91 /* only one clock gating mode (LS/DS/SD) can be enabled */ 92 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 93 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 94 HDP_MEM_POWER_CTRL, 95 ATOMIC_MEM_POWER_SD_EN, 1); 96 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 97 HDP_MEM_POWER_CTRL, 98 RC_MEM_POWER_SD_EN, 1); 99 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 100 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 101 HDP_MEM_POWER_CTRL, 102 ATOMIC_MEM_POWER_LS_EN, 1); 103 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 104 HDP_MEM_POWER_CTRL, 105 RC_MEM_POWER_LS_EN, 1); 106 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 107 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 108 HDP_MEM_POWER_CTRL, 109 ATOMIC_MEM_POWER_DS_EN, 1); 110 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 111 HDP_MEM_POWER_CTRL, 112 RC_MEM_POWER_DS_EN, 1); 113 } 114 115 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 116 * be set for SRAM LS/DS/SD */ 117 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 118 AMD_CG_SUPPORT_HDP_SD)) { 119 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 120 ATOMIC_MEM_POWER_CTRL_EN, 1); 121 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 122 RC_MEM_POWER_CTRL_EN, 1); 123 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 124 } 125 } 126 127 /* disable IPH & RC clock override after clock/power mode changing */ 128 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 129 RC_MEM_CLK_SOFT_OVERRIDE, 0); 130 if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(6, 1, 0)) 131 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); 132 else 133 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); 134 } 135 136 static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev, 137 u64 *flags) 138 { 139 uint32_t tmp; 140 141 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 142 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); 143 if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK) 144 *flags |= AMD_CG_SUPPORT_HDP_LS; 145 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK) 146 *flags |= AMD_CG_SUPPORT_HDP_DS; 147 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK) 148 *flags |= AMD_CG_SUPPORT_HDP_SD; 149 } 150 151 const struct amdgpu_hdp_funcs hdp_v6_0_funcs = { 152 .flush_hdp = hdp_v6_0_flush_hdp, 153 .update_clock_gating = hdp_v6_0_update_clock_gating, 154 .get_clock_gating_state = hdp_v6_0_get_clockgating_state, 155 }; 156