1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "hdp_v5_0.h" 25 26 #include "hdp/hdp_5_0_0_offset.h" 27 #include "hdp/hdp_5_0_0_sh_mask.h" 28 #include <uapi/linux/kfd_ioctl.h> 29 30 static void hdp_v5_0_flush_hdp(struct amdgpu_device *adev, 31 struct amdgpu_ring *ring) 32 { 33 if (!ring || !ring->funcs->emit_wreg) { 34 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 35 RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); 36 } else { 37 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); 38 } 39 } 40 41 static void hdp_v5_0_invalidate_hdp(struct amdgpu_device *adev, 42 struct amdgpu_ring *ring) 43 { 44 if (!ring || !ring->funcs->emit_wreg) { 45 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 46 RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE); 47 } else { 48 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 49 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 50 } 51 } 52 53 static void hdp_v5_0_update_mem_power_gating(struct amdgpu_device *adev, 54 bool enable) 55 { 56 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 57 uint32_t hdp_mem_pwr_cntl; 58 59 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 60 AMD_CG_SUPPORT_HDP_DS | 61 AMD_CG_SUPPORT_HDP_SD))) 62 return; 63 64 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 65 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 66 67 /* Before doing clock/power mode switch, 68 * forced on IPH & RC clock */ 69 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 70 IPH_MEM_CLK_SOFT_OVERRIDE, 1); 71 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 72 RC_MEM_CLK_SOFT_OVERRIDE, 1); 73 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 74 75 /* HDP 5.0 doesn't support dynamic power mode switch, 76 * disable clock and power gating before any changing */ 77 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 78 IPH_MEM_POWER_CTRL_EN, 0); 79 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 80 IPH_MEM_POWER_LS_EN, 0); 81 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 82 IPH_MEM_POWER_DS_EN, 0); 83 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 84 IPH_MEM_POWER_SD_EN, 0); 85 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 86 RC_MEM_POWER_CTRL_EN, 0); 87 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 88 RC_MEM_POWER_LS_EN, 0); 89 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 90 RC_MEM_POWER_DS_EN, 0); 91 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 92 RC_MEM_POWER_SD_EN, 0); 93 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 94 95 /* Already disabled above. The actions below are for "enabled" only */ 96 if (enable) { 97 /* only one clock gating mode (LS/DS/SD) can be enabled */ 98 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 99 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 100 HDP_MEM_POWER_CTRL, 101 IPH_MEM_POWER_LS_EN, 1); 102 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 103 HDP_MEM_POWER_CTRL, 104 RC_MEM_POWER_LS_EN, 1); 105 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 106 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 107 HDP_MEM_POWER_CTRL, 108 IPH_MEM_POWER_DS_EN, 1); 109 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 110 HDP_MEM_POWER_CTRL, 111 RC_MEM_POWER_DS_EN, 1); 112 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 113 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 114 HDP_MEM_POWER_CTRL, 115 IPH_MEM_POWER_SD_EN, 1); 116 /* RC should not use shut down mode, fallback to ds or ls if allowed */ 117 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) 118 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 119 HDP_MEM_POWER_CTRL, 120 RC_MEM_POWER_DS_EN, 1); 121 else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) 122 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 123 HDP_MEM_POWER_CTRL, 124 RC_MEM_POWER_LS_EN, 1); 125 } 126 127 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 128 * be set for SRAM LS/DS/SD */ 129 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 130 AMD_CG_SUPPORT_HDP_SD)) { 131 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 132 IPH_MEM_POWER_CTRL_EN, 1); 133 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 134 RC_MEM_POWER_CTRL_EN, 1); 135 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 136 } 137 } 138 139 /* disable IPH & RC clock override after clock/power mode changing */ 140 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 141 IPH_MEM_CLK_SOFT_OVERRIDE, 0); 142 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 143 RC_MEM_CLK_SOFT_OVERRIDE, 0); 144 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 145 } 146 147 static void hdp_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 148 bool enable) 149 { 150 uint32_t hdp_clk_cntl; 151 152 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 153 return; 154 155 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 156 157 if (enable) { 158 hdp_clk_cntl &= 159 ~(uint32_t) 160 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 161 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 162 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 163 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 164 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 165 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 166 } else { 167 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 168 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 169 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 170 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 171 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 172 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 173 } 174 175 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 176 } 177 178 static void hdp_v5_0_update_clock_gating(struct amdgpu_device *adev, 179 bool enable) 180 { 181 hdp_v5_0_update_mem_power_gating(adev, enable); 182 hdp_v5_0_update_medium_grain_clock_gating(adev, enable); 183 } 184 185 static void hdp_v5_0_get_clockgating_state(struct amdgpu_device *adev, 186 u64 *flags) 187 { 188 uint32_t tmp; 189 190 /* AMD_CG_SUPPORT_HDP_MGCG */ 191 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 192 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 193 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 194 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 195 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 196 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 197 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 198 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 199 200 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 201 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 202 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 203 *flags |= AMD_CG_SUPPORT_HDP_LS; 204 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 205 *flags |= AMD_CG_SUPPORT_HDP_DS; 206 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 207 *flags |= AMD_CG_SUPPORT_HDP_SD; 208 } 209 210 static void hdp_v5_0_init_registers(struct amdgpu_device *adev) 211 { 212 u32 tmp; 213 214 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); 215 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; 216 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp); 217 } 218 219 const struct amdgpu_hdp_funcs hdp_v5_0_funcs = { 220 .flush_hdp = hdp_v5_0_flush_hdp, 221 .invalidate_hdp = hdp_v5_0_invalidate_hdp, 222 .update_clock_gating = hdp_v5_0_update_clock_gating, 223 .get_clock_gating_state = hdp_v5_0_get_clockgating_state, 224 .init_registers = hdp_v5_0_init_registers, 225 }; 226