1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "umc_v12_0.h" 60 #include "hdp_v4_0.h" 61 #include "mca_v3_0.h" 62 63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 64 65 #include "amdgpu_ras.h" 66 #include "amdgpu_xgmi.h" 67 68 /* add these here since we already include dce12 headers and these are for DCN */ 69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 77 78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 80 81 #define MAX_MEM_RANGES 8 82 83 static const char * const gfxhub_client_ids[] = { 84 "CB", 85 "DB", 86 "IA", 87 "WD", 88 "CPF", 89 "CPC", 90 "CPG", 91 "RLC", 92 "TCP", 93 "SQC (inst)", 94 "SQC (data)", 95 "SQG", 96 "PA", 97 }; 98 99 static const char *mmhub_client_ids_raven[][2] = { 100 [0][0] = "MP1", 101 [1][0] = "MP0", 102 [2][0] = "VCN", 103 [3][0] = "VCNU", 104 [4][0] = "HDP", 105 [5][0] = "DCE", 106 [13][0] = "UTCL2", 107 [19][0] = "TLS", 108 [26][0] = "OSS", 109 [27][0] = "SDMA0", 110 [0][1] = "MP1", 111 [1][1] = "MP0", 112 [2][1] = "VCN", 113 [3][1] = "VCNU", 114 [4][1] = "HDP", 115 [5][1] = "XDP", 116 [6][1] = "DBGU0", 117 [7][1] = "DCE", 118 [8][1] = "DCEDWB0", 119 [9][1] = "DCEDWB1", 120 [26][1] = "OSS", 121 [27][1] = "SDMA0", 122 }; 123 124 static const char *mmhub_client_ids_renoir[][2] = { 125 [0][0] = "MP1", 126 [1][0] = "MP0", 127 [2][0] = "HDP", 128 [4][0] = "DCEDMC", 129 [5][0] = "DCEVGA", 130 [13][0] = "UTCL2", 131 [19][0] = "TLS", 132 [26][0] = "OSS", 133 [27][0] = "SDMA0", 134 [28][0] = "VCN", 135 [29][0] = "VCNU", 136 [30][0] = "JPEG", 137 [0][1] = "MP1", 138 [1][1] = "MP0", 139 [2][1] = "HDP", 140 [3][1] = "XDP", 141 [6][1] = "DBGU0", 142 [7][1] = "DCEDMC", 143 [8][1] = "DCEVGA", 144 [9][1] = "DCEDWB", 145 [26][1] = "OSS", 146 [27][1] = "SDMA0", 147 [28][1] = "VCN", 148 [29][1] = "VCNU", 149 [30][1] = "JPEG", 150 }; 151 152 static const char *mmhub_client_ids_vega10[][2] = { 153 [0][0] = "MP0", 154 [1][0] = "UVD", 155 [2][0] = "UVDU", 156 [3][0] = "HDP", 157 [13][0] = "UTCL2", 158 [14][0] = "OSS", 159 [15][0] = "SDMA1", 160 [32+0][0] = "VCE0", 161 [32+1][0] = "VCE0U", 162 [32+2][0] = "XDMA", 163 [32+3][0] = "DCE", 164 [32+4][0] = "MP1", 165 [32+14][0] = "SDMA0", 166 [0][1] = "MP0", 167 [1][1] = "UVD", 168 [2][1] = "UVDU", 169 [3][1] = "DBGU0", 170 [4][1] = "HDP", 171 [5][1] = "XDP", 172 [14][1] = "OSS", 173 [15][1] = "SDMA0", 174 [32+0][1] = "VCE0", 175 [32+1][1] = "VCE0U", 176 [32+2][1] = "XDMA", 177 [32+3][1] = "DCE", 178 [32+4][1] = "DCEDWB", 179 [32+5][1] = "MP1", 180 [32+6][1] = "DBGU1", 181 [32+14][1] = "SDMA1", 182 }; 183 184 static const char *mmhub_client_ids_vega12[][2] = { 185 [0][0] = "MP0", 186 [1][0] = "VCE0", 187 [2][0] = "VCE0U", 188 [3][0] = "HDP", 189 [13][0] = "UTCL2", 190 [14][0] = "OSS", 191 [15][0] = "SDMA1", 192 [32+0][0] = "DCE", 193 [32+1][0] = "XDMA", 194 [32+2][0] = "UVD", 195 [32+3][0] = "UVDU", 196 [32+4][0] = "MP1", 197 [32+15][0] = "SDMA0", 198 [0][1] = "MP0", 199 [1][1] = "VCE0", 200 [2][1] = "VCE0U", 201 [3][1] = "DBGU0", 202 [4][1] = "HDP", 203 [5][1] = "XDP", 204 [14][1] = "OSS", 205 [15][1] = "SDMA0", 206 [32+0][1] = "DCE", 207 [32+1][1] = "DCEDWB", 208 [32+2][1] = "XDMA", 209 [32+3][1] = "UVD", 210 [32+4][1] = "UVDU", 211 [32+5][1] = "MP1", 212 [32+6][1] = "DBGU1", 213 [32+15][1] = "SDMA1", 214 }; 215 216 static const char *mmhub_client_ids_vega20[][2] = { 217 [0][0] = "XDMA", 218 [1][0] = "DCE", 219 [2][0] = "VCE0", 220 [3][0] = "VCE0U", 221 [4][0] = "UVD", 222 [5][0] = "UVD1U", 223 [13][0] = "OSS", 224 [14][0] = "HDP", 225 [15][0] = "SDMA0", 226 [32+0][0] = "UVD", 227 [32+1][0] = "UVDU", 228 [32+2][0] = "MP1", 229 [32+3][0] = "MP0", 230 [32+12][0] = "UTCL2", 231 [32+14][0] = "SDMA1", 232 [0][1] = "XDMA", 233 [1][1] = "DCE", 234 [2][1] = "DCEDWB", 235 [3][1] = "VCE0", 236 [4][1] = "VCE0U", 237 [5][1] = "UVD1", 238 [6][1] = "UVD1U", 239 [7][1] = "DBGU0", 240 [8][1] = "XDP", 241 [13][1] = "OSS", 242 [14][1] = "HDP", 243 [15][1] = "SDMA0", 244 [32+0][1] = "UVD", 245 [32+1][1] = "UVDU", 246 [32+2][1] = "DBGU1", 247 [32+3][1] = "MP1", 248 [32+4][1] = "MP0", 249 [32+14][1] = "SDMA1", 250 }; 251 252 static const char *mmhub_client_ids_arcturus[][2] = { 253 [0][0] = "DBGU1", 254 [1][0] = "XDP", 255 [2][0] = "MP1", 256 [14][0] = "HDP", 257 [171][0] = "JPEG", 258 [172][0] = "VCN", 259 [173][0] = "VCNU", 260 [203][0] = "JPEG1", 261 [204][0] = "VCN1", 262 [205][0] = "VCN1U", 263 [256][0] = "SDMA0", 264 [257][0] = "SDMA1", 265 [258][0] = "SDMA2", 266 [259][0] = "SDMA3", 267 [260][0] = "SDMA4", 268 [261][0] = "SDMA5", 269 [262][0] = "SDMA6", 270 [263][0] = "SDMA7", 271 [384][0] = "OSS", 272 [0][1] = "DBGU1", 273 [1][1] = "XDP", 274 [2][1] = "MP1", 275 [14][1] = "HDP", 276 [171][1] = "JPEG", 277 [172][1] = "VCN", 278 [173][1] = "VCNU", 279 [203][1] = "JPEG1", 280 [204][1] = "VCN1", 281 [205][1] = "VCN1U", 282 [256][1] = "SDMA0", 283 [257][1] = "SDMA1", 284 [258][1] = "SDMA2", 285 [259][1] = "SDMA3", 286 [260][1] = "SDMA4", 287 [261][1] = "SDMA5", 288 [262][1] = "SDMA6", 289 [263][1] = "SDMA7", 290 [384][1] = "OSS", 291 }; 292 293 static const char *mmhub_client_ids_aldebaran[][2] = { 294 [2][0] = "MP1", 295 [3][0] = "MP0", 296 [32+1][0] = "DBGU_IO0", 297 [32+2][0] = "DBGU_IO2", 298 [32+4][0] = "MPIO", 299 [96+11][0] = "JPEG0", 300 [96+12][0] = "VCN0", 301 [96+13][0] = "VCNU0", 302 [128+11][0] = "JPEG1", 303 [128+12][0] = "VCN1", 304 [128+13][0] = "VCNU1", 305 [160+1][0] = "XDP", 306 [160+14][0] = "HDP", 307 [256+0][0] = "SDMA0", 308 [256+1][0] = "SDMA1", 309 [256+2][0] = "SDMA2", 310 [256+3][0] = "SDMA3", 311 [256+4][0] = "SDMA4", 312 [384+0][0] = "OSS", 313 [2][1] = "MP1", 314 [3][1] = "MP0", 315 [32+1][1] = "DBGU_IO0", 316 [32+2][1] = "DBGU_IO2", 317 [32+4][1] = "MPIO", 318 [96+11][1] = "JPEG0", 319 [96+12][1] = "VCN0", 320 [96+13][1] = "VCNU0", 321 [128+11][1] = "JPEG1", 322 [128+12][1] = "VCN1", 323 [128+13][1] = "VCNU1", 324 [160+1][1] = "XDP", 325 [160+14][1] = "HDP", 326 [256+0][1] = "SDMA0", 327 [256+1][1] = "SDMA1", 328 [256+2][1] = "SDMA2", 329 [256+3][1] = "SDMA3", 330 [256+4][1] = "SDMA4", 331 [384+0][1] = "OSS", 332 }; 333 334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { 335 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 336 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 337 }; 338 339 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { 340 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 341 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 342 }; 343 344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 345 (0x000143c0 + 0x00000000), 346 (0x000143c0 + 0x00000800), 347 (0x000143c0 + 0x00001000), 348 (0x000143c0 + 0x00001800), 349 (0x000543c0 + 0x00000000), 350 (0x000543c0 + 0x00000800), 351 (0x000543c0 + 0x00001000), 352 (0x000543c0 + 0x00001800), 353 (0x000943c0 + 0x00000000), 354 (0x000943c0 + 0x00000800), 355 (0x000943c0 + 0x00001000), 356 (0x000943c0 + 0x00001800), 357 (0x000d43c0 + 0x00000000), 358 (0x000d43c0 + 0x00000800), 359 (0x000d43c0 + 0x00001000), 360 (0x000d43c0 + 0x00001800), 361 (0x001143c0 + 0x00000000), 362 (0x001143c0 + 0x00000800), 363 (0x001143c0 + 0x00001000), 364 (0x001143c0 + 0x00001800), 365 (0x001543c0 + 0x00000000), 366 (0x001543c0 + 0x00000800), 367 (0x001543c0 + 0x00001000), 368 (0x001543c0 + 0x00001800), 369 (0x001943c0 + 0x00000000), 370 (0x001943c0 + 0x00000800), 371 (0x001943c0 + 0x00001000), 372 (0x001943c0 + 0x00001800), 373 (0x001d43c0 + 0x00000000), 374 (0x001d43c0 + 0x00000800), 375 (0x001d43c0 + 0x00001000), 376 (0x001d43c0 + 0x00001800), 377 }; 378 379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 380 (0x000143e0 + 0x00000000), 381 (0x000143e0 + 0x00000800), 382 (0x000143e0 + 0x00001000), 383 (0x000143e0 + 0x00001800), 384 (0x000543e0 + 0x00000000), 385 (0x000543e0 + 0x00000800), 386 (0x000543e0 + 0x00001000), 387 (0x000543e0 + 0x00001800), 388 (0x000943e0 + 0x00000000), 389 (0x000943e0 + 0x00000800), 390 (0x000943e0 + 0x00001000), 391 (0x000943e0 + 0x00001800), 392 (0x000d43e0 + 0x00000000), 393 (0x000d43e0 + 0x00000800), 394 (0x000d43e0 + 0x00001000), 395 (0x000d43e0 + 0x00001800), 396 (0x001143e0 + 0x00000000), 397 (0x001143e0 + 0x00000800), 398 (0x001143e0 + 0x00001000), 399 (0x001143e0 + 0x00001800), 400 (0x001543e0 + 0x00000000), 401 (0x001543e0 + 0x00000800), 402 (0x001543e0 + 0x00001000), 403 (0x001543e0 + 0x00001800), 404 (0x001943e0 + 0x00000000), 405 (0x001943e0 + 0x00000800), 406 (0x001943e0 + 0x00001000), 407 (0x001943e0 + 0x00001800), 408 (0x001d43e0 + 0x00000000), 409 (0x001d43e0 + 0x00000800), 410 (0x001d43e0 + 0x00001000), 411 (0x001d43e0 + 0x00001800), 412 }; 413 414 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 415 struct amdgpu_irq_src *src, 416 unsigned int type, 417 enum amdgpu_interrupt_state state) 418 { 419 u32 bits, i, tmp, reg; 420 421 /* Devices newer then VEGA10/12 shall have these programming 422 * sequences performed by PSP BL 423 */ 424 if (adev->asic_type >= CHIP_VEGA20) 425 return 0; 426 427 bits = 0x7f; 428 429 switch (state) { 430 case AMDGPU_IRQ_STATE_DISABLE: 431 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 432 reg = ecc_umc_mcumc_ctrl_addrs[i]; 433 tmp = RREG32(reg); 434 tmp &= ~bits; 435 WREG32(reg, tmp); 436 } 437 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 438 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 439 tmp = RREG32(reg); 440 tmp &= ~bits; 441 WREG32(reg, tmp); 442 } 443 break; 444 case AMDGPU_IRQ_STATE_ENABLE: 445 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 446 reg = ecc_umc_mcumc_ctrl_addrs[i]; 447 tmp = RREG32(reg); 448 tmp |= bits; 449 WREG32(reg, tmp); 450 } 451 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 452 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 453 tmp = RREG32(reg); 454 tmp |= bits; 455 WREG32(reg, tmp); 456 } 457 break; 458 default: 459 break; 460 } 461 462 return 0; 463 } 464 465 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 466 struct amdgpu_irq_src *src, 467 unsigned int type, 468 enum amdgpu_interrupt_state state) 469 { 470 struct amdgpu_vmhub *hub; 471 u32 tmp, reg, bits, i, j; 472 473 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 479 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 480 481 switch (state) { 482 case AMDGPU_IRQ_STATE_DISABLE: 483 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 484 hub = &adev->vmhub[j]; 485 for (i = 0; i < 16; i++) { 486 reg = hub->vm_context0_cntl + i; 487 488 /* This works because this interrupt is only 489 * enabled at init/resume and disabled in 490 * fini/suspend, so the overall state doesn't 491 * change over the course of suspend/resume. 492 */ 493 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 494 continue; 495 496 if (j >= AMDGPU_MMHUB0(0)) 497 tmp = RREG32_SOC15_IP(MMHUB, reg); 498 else 499 tmp = RREG32_SOC15_IP(GC, reg); 500 501 tmp &= ~bits; 502 503 if (j >= AMDGPU_MMHUB0(0)) 504 WREG32_SOC15_IP(MMHUB, reg, tmp); 505 else 506 WREG32_SOC15_IP(GC, reg, tmp); 507 } 508 } 509 break; 510 case AMDGPU_IRQ_STATE_ENABLE: 511 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 512 hub = &adev->vmhub[j]; 513 for (i = 0; i < 16; i++) { 514 reg = hub->vm_context0_cntl + i; 515 516 /* This works because this interrupt is only 517 * enabled at init/resume and disabled in 518 * fini/suspend, so the overall state doesn't 519 * change over the course of suspend/resume. 520 */ 521 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 522 continue; 523 524 if (j >= AMDGPU_MMHUB0(0)) 525 tmp = RREG32_SOC15_IP(MMHUB, reg); 526 else 527 tmp = RREG32_SOC15_IP(GC, reg); 528 529 tmp |= bits; 530 531 if (j >= AMDGPU_MMHUB0(0)) 532 WREG32_SOC15_IP(MMHUB, reg, tmp); 533 else 534 WREG32_SOC15_IP(GC, reg, tmp); 535 } 536 } 537 break; 538 default: 539 break; 540 } 541 542 return 0; 543 } 544 545 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 546 struct amdgpu_irq_src *source, 547 struct amdgpu_iv_entry *entry) 548 { 549 bool retry_fault = !!(entry->src_data[1] & 0x80); 550 bool write_fault = !!(entry->src_data[1] & 0x20); 551 uint32_t status = 0, cid = 0, rw = 0; 552 struct amdgpu_task_info task_info; 553 struct amdgpu_vmhub *hub; 554 const char *mmhub_cid; 555 const char *hub_name; 556 unsigned int vmhub; 557 u64 addr; 558 uint32_t cam_index = 0; 559 int ret, xcc_id = 0; 560 uint32_t node_id; 561 562 node_id = entry->node_id; 563 564 addr = (u64)entry->src_data[0] << 12; 565 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 566 567 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 568 hub_name = "mmhub0"; 569 vmhub = AMDGPU_MMHUB0(node_id / 4); 570 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 571 hub_name = "mmhub1"; 572 vmhub = AMDGPU_MMHUB1(0); 573 } else { 574 hub_name = "gfxhub0"; 575 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 577 node_id); 578 if (xcc_id < 0) 579 xcc_id = 0; 580 } 581 vmhub = xcc_id; 582 } 583 hub = &adev->vmhub[vmhub]; 584 585 if (retry_fault) { 586 if (adev->irq.retry_cam_enabled) { 587 /* Delegate it to a different ring if the hardware hasn't 588 * already done it. 589 */ 590 if (entry->ih == &adev->irq.ih) { 591 amdgpu_irq_delegate(adev, entry, 8); 592 return 1; 593 } 594 595 cam_index = entry->src_data[2] & 0x3ff; 596 597 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 598 addr, write_fault); 599 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 600 if (ret) 601 return 1; 602 } else { 603 /* Process it onyl if it's the first fault for this address */ 604 if (entry->ih != &adev->irq.ih_soft && 605 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 606 entry->timestamp)) 607 return 1; 608 609 /* Delegate it to a different ring if the hardware hasn't 610 * already done it. 611 */ 612 if (entry->ih == &adev->irq.ih) { 613 amdgpu_irq_delegate(adev, entry, 8); 614 return 1; 615 } 616 617 /* Try to handle the recoverable page faults by filling page 618 * tables 619 */ 620 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 621 addr, write_fault)) 622 return 1; 623 } 624 } 625 626 if (!printk_ratelimit()) 627 return 0; 628 629 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 630 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 631 632 dev_err(adev->dev, 633 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n", 634 hub_name, retry_fault ? "retry" : "no-retry", 635 entry->src_id, entry->ring_id, entry->vmid, 636 entry->pasid, task_info.process_name, task_info.tgid, 637 task_info.task_name, task_info.pid); 638 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 639 addr, entry->client_id, 640 soc15_ih_clientid_name[entry->client_id]); 641 642 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 643 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 644 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 645 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 646 647 if (amdgpu_sriov_vf(adev)) 648 return 0; 649 650 /* 651 * Issue a dummy read to wait for the status register to 652 * be updated to avoid reading an incorrect value due to 653 * the new fast GRBM interface. 654 */ 655 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 656 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 657 RREG32(hub->vm_l2_pro_fault_status); 658 659 status = RREG32(hub->vm_l2_pro_fault_status); 660 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 661 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 662 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 663 664 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub); 665 666 dev_err(adev->dev, 667 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 668 status); 669 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 670 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 671 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 672 gfxhub_client_ids[cid], 673 cid); 674 } else { 675 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 676 case IP_VERSION(9, 0, 0): 677 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 678 break; 679 case IP_VERSION(9, 3, 0): 680 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 681 break; 682 case IP_VERSION(9, 4, 0): 683 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 684 break; 685 case IP_VERSION(9, 4, 1): 686 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 687 break; 688 case IP_VERSION(9, 1, 0): 689 case IP_VERSION(9, 2, 0): 690 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 691 break; 692 case IP_VERSION(1, 5, 0): 693 case IP_VERSION(2, 4, 0): 694 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 695 break; 696 case IP_VERSION(1, 8, 0): 697 case IP_VERSION(9, 4, 2): 698 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 699 break; 700 default: 701 mmhub_cid = NULL; 702 break; 703 } 704 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 705 mmhub_cid ? mmhub_cid : "unknown", cid); 706 } 707 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 708 REG_GET_FIELD(status, 709 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 710 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 711 REG_GET_FIELD(status, 712 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 713 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 714 REG_GET_FIELD(status, 715 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 716 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 717 REG_GET_FIELD(status, 718 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 719 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 720 return 0; 721 } 722 723 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 724 .set = gmc_v9_0_vm_fault_interrupt_state, 725 .process = gmc_v9_0_process_interrupt, 726 }; 727 728 729 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 730 .set = gmc_v9_0_ecc_interrupt_state, 731 .process = amdgpu_umc_process_ecc_irq, 732 }; 733 734 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 735 { 736 adev->gmc.vm_fault.num_types = 1; 737 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 738 739 if (!amdgpu_sriov_vf(adev) && 740 !adev->gmc.xgmi.connected_to_cpu && 741 !adev->gmc.is_app_apu) { 742 adev->gmc.ecc_irq.num_types = 1; 743 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 744 } 745 } 746 747 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 748 uint32_t flush_type) 749 { 750 u32 req = 0; 751 752 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 753 PER_VMID_INVALIDATE_REQ, 1 << vmid); 754 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 755 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 756 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 757 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 758 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 759 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 760 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 761 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 762 763 return req; 764 } 765 766 /** 767 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 768 * 769 * @adev: amdgpu_device pointer 770 * @vmhub: vmhub type 771 * 772 */ 773 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 774 uint32_t vmhub) 775 { 776 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 777 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 778 return false; 779 780 return ((vmhub == AMDGPU_MMHUB0(0) || 781 vmhub == AMDGPU_MMHUB1(0)) && 782 (!amdgpu_sriov_vf(adev)) && 783 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 784 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 785 } 786 787 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 788 uint8_t vmid, uint16_t *p_pasid) 789 { 790 uint32_t value; 791 792 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 793 + vmid); 794 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 795 796 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 797 } 798 799 /* 800 * GART 801 * VMID 0 is the physical GPU addresses as used by the kernel. 802 * VMIDs 1-15 are used for userspace clients and are handled 803 * by the amdgpu vm/hsa code. 804 */ 805 806 /** 807 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 808 * 809 * @adev: amdgpu_device pointer 810 * @vmid: vm instance to flush 811 * @vmhub: which hub to flush 812 * @flush_type: the flush type 813 * 814 * Flush the TLB for the requested page table using certain type. 815 */ 816 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 817 uint32_t vmhub, uint32_t flush_type) 818 { 819 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 820 u32 j, inv_req, tmp, sem, req, ack; 821 const unsigned int eng = 17; 822 struct amdgpu_vmhub *hub; 823 824 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 825 826 hub = &adev->vmhub[vmhub]; 827 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 828 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 829 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 830 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 831 832 /* This is necessary for a HW workaround under SRIOV as well 833 * as GFXOFF under bare metal 834 */ 835 if (adev->gfx.kiq[0].ring.sched.ready && 836 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 837 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 838 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 839 840 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 841 1 << vmid); 842 return; 843 } 844 845 spin_lock(&adev->gmc.invalidate_lock); 846 847 /* 848 * It may lose gpuvm invalidate acknowldege state across power-gating 849 * off cycle, add semaphore acquire before invalidation and semaphore 850 * release after invalidation to avoid entering power gated state 851 * to WA the Issue 852 */ 853 854 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 855 if (use_semaphore) { 856 for (j = 0; j < adev->usec_timeout; j++) { 857 /* a read return value of 1 means semaphore acquire */ 858 if (vmhub >= AMDGPU_MMHUB0(0)) 859 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem); 860 else 861 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem); 862 if (tmp & 0x1) 863 break; 864 udelay(1); 865 } 866 867 if (j >= adev->usec_timeout) 868 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 869 } 870 871 if (vmhub >= AMDGPU_MMHUB0(0)) 872 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req); 873 else 874 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req); 875 876 /* 877 * Issue a dummy read to wait for the ACK register to 878 * be cleared to avoid a false ACK due to the new fast 879 * GRBM interface. 880 */ 881 if ((vmhub == AMDGPU_GFXHUB(0)) && 882 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 883 RREG32_NO_KIQ(req); 884 885 for (j = 0; j < adev->usec_timeout; j++) { 886 if (vmhub >= AMDGPU_MMHUB0(0)) 887 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack); 888 else 889 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack); 890 if (tmp & (1 << vmid)) 891 break; 892 udelay(1); 893 } 894 895 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 896 if (use_semaphore) { 897 /* 898 * add semaphore release after invalidation, 899 * write with 0 means semaphore release 900 */ 901 if (vmhub >= AMDGPU_MMHUB0(0)) 902 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0); 903 else 904 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0); 905 } 906 907 spin_unlock(&adev->gmc.invalidate_lock); 908 909 if (j < adev->usec_timeout) 910 return; 911 912 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 913 } 914 915 /** 916 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 917 * 918 * @adev: amdgpu_device pointer 919 * @pasid: pasid to be flush 920 * @flush_type: the flush type 921 * @all_hub: flush all hubs 922 * @inst: is used to select which instance of KIQ to use for the invalidation 923 * 924 * Flush the TLB for the requested pasid. 925 */ 926 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 927 uint16_t pasid, uint32_t flush_type, 928 bool all_hub, uint32_t inst) 929 { 930 uint16_t queried; 931 int i, vmid; 932 933 for (vmid = 1; vmid < 16; vmid++) { 934 bool valid; 935 936 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 937 &queried); 938 if (!valid || queried != pasid) 939 continue; 940 941 if (all_hub) { 942 for_each_set_bit(i, adev->vmhubs_mask, 943 AMDGPU_MAX_VMHUBS) 944 gmc_v9_0_flush_gpu_tlb(adev, vmid, i, 945 flush_type); 946 } else { 947 gmc_v9_0_flush_gpu_tlb(adev, vmid, 948 AMDGPU_GFXHUB(0), 949 flush_type); 950 } 951 } 952 } 953 954 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 955 unsigned int vmid, uint64_t pd_addr) 956 { 957 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 958 struct amdgpu_device *adev = ring->adev; 959 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 960 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 961 unsigned int eng = ring->vm_inv_eng; 962 963 /* 964 * It may lose gpuvm invalidate acknowldege state across power-gating 965 * off cycle, add semaphore acquire before invalidation and semaphore 966 * release after invalidation to avoid entering power gated state 967 * to WA the Issue 968 */ 969 970 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 971 if (use_semaphore) 972 /* a read return value of 1 means semaphore acuqire */ 973 amdgpu_ring_emit_reg_wait(ring, 974 hub->vm_inv_eng0_sem + 975 hub->eng_distance * eng, 0x1, 0x1); 976 977 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 978 (hub->ctx_addr_distance * vmid), 979 lower_32_bits(pd_addr)); 980 981 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 982 (hub->ctx_addr_distance * vmid), 983 upper_32_bits(pd_addr)); 984 985 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 986 hub->eng_distance * eng, 987 hub->vm_inv_eng0_ack + 988 hub->eng_distance * eng, 989 req, 1 << vmid); 990 991 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 992 if (use_semaphore) 993 /* 994 * add semaphore release after invalidation, 995 * write with 0 means semaphore release 996 */ 997 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 998 hub->eng_distance * eng, 0); 999 1000 return pd_addr; 1001 } 1002 1003 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 1004 unsigned int pasid) 1005 { 1006 struct amdgpu_device *adev = ring->adev; 1007 uint32_t reg; 1008 1009 /* Do nothing because there's no lut register for mmhub1. */ 1010 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 1011 return; 1012 1013 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 1014 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1015 else 1016 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1017 1018 amdgpu_ring_emit_wreg(ring, reg, pasid); 1019 } 1020 1021 /* 1022 * PTE format on VEGA 10: 1023 * 63:59 reserved 1024 * 58:57 mtype 1025 * 56 F 1026 * 55 L 1027 * 54 P 1028 * 53 SW 1029 * 52 T 1030 * 50:48 reserved 1031 * 47:12 4k physical page base address 1032 * 11:7 fragment 1033 * 6 write 1034 * 5 read 1035 * 4 exe 1036 * 3 Z 1037 * 2 snooped 1038 * 1 system 1039 * 0 valid 1040 * 1041 * PDE format on VEGA 10: 1042 * 63:59 block fragment size 1043 * 58:55 reserved 1044 * 54 P 1045 * 53:48 reserved 1046 * 47:6 physical base address of PD or PTE 1047 * 5:3 reserved 1048 * 2 C 1049 * 1 system 1050 * 0 valid 1051 */ 1052 1053 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1054 1055 { 1056 switch (flags) { 1057 case AMDGPU_VM_MTYPE_DEFAULT: 1058 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1059 case AMDGPU_VM_MTYPE_NC: 1060 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1061 case AMDGPU_VM_MTYPE_WC: 1062 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 1063 case AMDGPU_VM_MTYPE_RW: 1064 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 1065 case AMDGPU_VM_MTYPE_CC: 1066 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1067 case AMDGPU_VM_MTYPE_UC: 1068 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 1069 default: 1070 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1071 } 1072 } 1073 1074 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1075 uint64_t *addr, uint64_t *flags) 1076 { 1077 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1078 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1079 BUG_ON(*addr & 0xFFFF00000000003FULL); 1080 1081 if (!adev->gmc.translate_further) 1082 return; 1083 1084 if (level == AMDGPU_VM_PDB1) { 1085 /* Set the block fragment size */ 1086 if (!(*flags & AMDGPU_PDE_PTE)) 1087 *flags |= AMDGPU_PDE_BFS(0x9); 1088 1089 } else if (level == AMDGPU_VM_PDB0) { 1090 if (*flags & AMDGPU_PDE_PTE) { 1091 *flags &= ~AMDGPU_PDE_PTE; 1092 if (!(*flags & AMDGPU_PTE_VALID)) 1093 *addr |= 1 << PAGE_SHIFT; 1094 } else { 1095 *flags |= AMDGPU_PTE_TF; 1096 } 1097 } 1098 } 1099 1100 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1101 struct amdgpu_bo *bo, 1102 struct amdgpu_bo_va_mapping *mapping, 1103 uint64_t *flags) 1104 { 1105 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1106 bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM; 1107 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | AMDGPU_GEM_CREATE_EXT_COHERENT); 1108 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; 1109 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1110 struct amdgpu_vm *vm = mapping->bo_va->base.vm; 1111 unsigned int mtype_local, mtype; 1112 bool snoop = false; 1113 bool is_local; 1114 1115 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1116 case IP_VERSION(9, 4, 1): 1117 case IP_VERSION(9, 4, 2): 1118 if (is_vram) { 1119 if (bo_adev == adev) { 1120 if (uncached) 1121 mtype = MTYPE_UC; 1122 else if (coherent) 1123 mtype = MTYPE_CC; 1124 else 1125 mtype = MTYPE_RW; 1126 /* FIXME: is this still needed? Or does 1127 * amdgpu_ttm_tt_pde_flags already handle this? 1128 */ 1129 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 1130 IP_VERSION(9, 4, 2) || 1131 amdgpu_ip_version(adev, GC_HWIP, 0) == 1132 IP_VERSION(9, 4, 3)) && 1133 adev->gmc.xgmi.connected_to_cpu) 1134 snoop = true; 1135 } else { 1136 if (uncached || coherent) 1137 mtype = MTYPE_UC; 1138 else 1139 mtype = MTYPE_NC; 1140 if (mapping->bo_va->is_xgmi) 1141 snoop = true; 1142 } 1143 } else { 1144 if (uncached || coherent) 1145 mtype = MTYPE_UC; 1146 else 1147 mtype = MTYPE_NC; 1148 /* FIXME: is this still needed? Or does 1149 * amdgpu_ttm_tt_pde_flags already handle this? 1150 */ 1151 snoop = true; 1152 } 1153 break; 1154 case IP_VERSION(9, 4, 3): 1155 /* Only local VRAM BOs or system memory on non-NUMA APUs 1156 * can be assumed to be local in their entirety. Choose 1157 * MTYPE_NC as safe fallback for all system memory BOs on 1158 * NUMA systems. Their MTYPE can be overridden per-page in 1159 * gmc_v9_0_override_vm_pte_flags. 1160 */ 1161 mtype_local = MTYPE_RW; 1162 if (amdgpu_mtype_local == 1) { 1163 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); 1164 mtype_local = MTYPE_NC; 1165 } else if (amdgpu_mtype_local == 2) { 1166 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n"); 1167 mtype_local = MTYPE_CC; 1168 } else { 1169 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); 1170 } 1171 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1172 num_possible_nodes() <= 1) || 1173 (is_vram && adev == bo_adev && 1174 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id); 1175 snoop = true; 1176 if (uncached) { 1177 mtype = MTYPE_UC; 1178 } else if (ext_coherent) { 1179 mtype = is_local ? MTYPE_CC : MTYPE_UC; 1180 } else if (adev->flags & AMD_IS_APU) { 1181 mtype = is_local ? mtype_local : MTYPE_NC; 1182 } else { 1183 /* dGPU */ 1184 if (is_local) 1185 mtype = mtype_local; 1186 else if (is_vram) 1187 mtype = MTYPE_NC; 1188 else 1189 mtype = MTYPE_UC; 1190 } 1191 1192 break; 1193 default: 1194 if (uncached || coherent) 1195 mtype = MTYPE_UC; 1196 else 1197 mtype = MTYPE_NC; 1198 1199 /* FIXME: is this still needed? Or does 1200 * amdgpu_ttm_tt_pde_flags already handle this? 1201 */ 1202 if (!is_vram) 1203 snoop = true; 1204 } 1205 1206 if (mtype != MTYPE_NC) 1207 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1208 AMDGPU_PTE_MTYPE_VG10(mtype); 1209 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1210 } 1211 1212 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1213 struct amdgpu_bo_va_mapping *mapping, 1214 uint64_t *flags) 1215 { 1216 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1217 1218 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1219 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1220 1221 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1222 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1223 1224 if (mapping->flags & AMDGPU_PTE_PRT) { 1225 *flags |= AMDGPU_PTE_PRT; 1226 *flags &= ~AMDGPU_PTE_VALID; 1227 } 1228 1229 if (bo && bo->tbo.resource) 1230 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo, 1231 mapping, flags); 1232 } 1233 1234 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1235 struct amdgpu_vm *vm, 1236 uint64_t addr, uint64_t *flags) 1237 { 1238 int local_node, nid; 1239 1240 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system 1241 * memory can use more efficient MTYPEs. 1242 */ 1243 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) 1244 return; 1245 1246 /* Only direct-mapped memory allows us to determine the NUMA node from 1247 * the DMA address. 1248 */ 1249 if (!adev->ram_is_direct_mapped) { 1250 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n"); 1251 return; 1252 } 1253 1254 /* MTYPE_NC is the same default and can be overridden. 1255 * MTYPE_UC will be present if the memory is extended-coherent 1256 * and can also be overridden. 1257 */ 1258 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1259 AMDGPU_PTE_MTYPE_VG10(MTYPE_NC) && 1260 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1261 AMDGPU_PTE_MTYPE_VG10(MTYPE_UC)) { 1262 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n"); 1263 return; 1264 } 1265 1266 /* FIXME: Only supported on native mode for now. For carve-out, the 1267 * NUMA affinity of the GPU/VM needs to come from the PCI info because 1268 * memory partitions are not associated with different NUMA nodes. 1269 */ 1270 if (adev->gmc.is_app_apu && vm->mem_id >= 0) { 1271 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1272 } else { 1273 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n"); 1274 return; 1275 } 1276 1277 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1278 * page or NUMA nodes. 1279 */ 1280 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1281 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n"); 1282 return; 1283 } 1284 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1285 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1286 vm->mem_id, local_node, nid); 1287 if (nid == local_node) { 1288 uint64_t old_flags = *flags; 1289 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) == 1290 AMDGPU_PTE_MTYPE_VG10(MTYPE_NC)) { 1291 unsigned int mtype_local = MTYPE_RW; 1292 1293 if (amdgpu_mtype_local == 1) 1294 mtype_local = MTYPE_NC; 1295 else if (amdgpu_mtype_local == 2) 1296 mtype_local = MTYPE_CC; 1297 1298 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1299 AMDGPU_PTE_MTYPE_VG10(mtype_local); 1300 } else { 1301 /* MTYPE_UC case */ 1302 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1303 AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1304 } 1305 1306 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n", 1307 old_flags, *flags); 1308 } 1309 } 1310 1311 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1312 { 1313 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1314 unsigned int size; 1315 1316 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1317 1318 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1319 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1320 } else { 1321 u32 viewport; 1322 1323 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1324 case IP_VERSION(1, 0, 0): 1325 case IP_VERSION(1, 0, 1): 1326 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1327 size = (REG_GET_FIELD(viewport, 1328 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1329 REG_GET_FIELD(viewport, 1330 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1331 4); 1332 break; 1333 case IP_VERSION(2, 1, 0): 1334 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1335 size = (REG_GET_FIELD(viewport, 1336 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1337 REG_GET_FIELD(viewport, 1338 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1339 4); 1340 break; 1341 default: 1342 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1343 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1344 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1345 4); 1346 break; 1347 } 1348 } 1349 1350 return size; 1351 } 1352 1353 static enum amdgpu_memory_partition 1354 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes) 1355 { 1356 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE; 1357 1358 if (adev->nbio.funcs->get_memory_partition_mode) 1359 mode = adev->nbio.funcs->get_memory_partition_mode(adev, 1360 supp_modes); 1361 1362 return mode; 1363 } 1364 1365 static enum amdgpu_memory_partition 1366 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev) 1367 { 1368 if (amdgpu_sriov_vf(adev)) 1369 return AMDGPU_NPS1_PARTITION_MODE; 1370 1371 return gmc_v9_0_get_memory_partition(adev, NULL); 1372 } 1373 1374 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1375 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1376 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1377 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1378 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1379 .map_mtype = gmc_v9_0_map_mtype, 1380 .get_vm_pde = gmc_v9_0_get_vm_pde, 1381 .get_vm_pte = gmc_v9_0_get_vm_pte, 1382 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1383 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1384 .query_mem_partition_mode = &gmc_v9_0_query_memory_partition, 1385 }; 1386 1387 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1388 { 1389 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1390 } 1391 1392 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1393 { 1394 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1395 case IP_VERSION(6, 0, 0): 1396 adev->umc.funcs = &umc_v6_0_funcs; 1397 break; 1398 case IP_VERSION(6, 1, 1): 1399 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1400 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1401 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1402 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1403 adev->umc.retire_unit = 1; 1404 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1405 adev->umc.ras = &umc_v6_1_ras; 1406 break; 1407 case IP_VERSION(6, 1, 2): 1408 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1409 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1410 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1411 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1412 adev->umc.retire_unit = 1; 1413 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1414 adev->umc.ras = &umc_v6_1_ras; 1415 break; 1416 case IP_VERSION(6, 7, 0): 1417 adev->umc.max_ras_err_cnt_per_query = 1418 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1419 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1420 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1421 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1422 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1423 if (!adev->gmc.xgmi.connected_to_cpu) 1424 adev->umc.ras = &umc_v6_7_ras; 1425 if (1 & adev->smuio.funcs->get_die_id(adev)) 1426 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1427 else 1428 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1429 break; 1430 case IP_VERSION(12, 0, 0): 1431 adev->umc.max_ras_err_cnt_per_query = 1432 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1433 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM; 1434 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM; 1435 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM; 1436 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET; 1437 adev->umc.active_mask = adev->aid_mask; 1438 adev->umc.retire_unit = UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1439 adev->umc.channel_idx_tbl = &umc_v12_0_channel_idx_tbl[0][0][0]; 1440 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1441 adev->umc.ras = &umc_v12_0_ras; 1442 break; 1443 default: 1444 break; 1445 } 1446 } 1447 1448 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1449 { 1450 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1451 case IP_VERSION(9, 4, 1): 1452 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1453 break; 1454 case IP_VERSION(9, 4, 2): 1455 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1456 break; 1457 case IP_VERSION(1, 8, 0): 1458 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1459 break; 1460 default: 1461 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1462 break; 1463 } 1464 } 1465 1466 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1467 { 1468 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1469 case IP_VERSION(9, 4, 0): 1470 adev->mmhub.ras = &mmhub_v1_0_ras; 1471 break; 1472 case IP_VERSION(9, 4, 1): 1473 adev->mmhub.ras = &mmhub_v9_4_ras; 1474 break; 1475 case IP_VERSION(9, 4, 2): 1476 adev->mmhub.ras = &mmhub_v1_7_ras; 1477 break; 1478 case IP_VERSION(1, 8, 0): 1479 adev->mmhub.ras = &mmhub_v1_8_ras; 1480 break; 1481 default: 1482 /* mmhub ras is not available */ 1483 break; 1484 } 1485 } 1486 1487 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1488 { 1489 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 1490 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1491 else 1492 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1493 } 1494 1495 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1496 { 1497 adev->hdp.ras = &hdp_v4_0_ras; 1498 } 1499 1500 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1501 { 1502 struct amdgpu_mca *mca = &adev->mca; 1503 1504 /* is UMC the right IP to check for MCA? Maybe DF? */ 1505 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1506 case IP_VERSION(6, 7, 0): 1507 if (!adev->gmc.xgmi.connected_to_cpu) { 1508 mca->mp0.ras = &mca_v3_0_mp0_ras; 1509 mca->mp1.ras = &mca_v3_0_mp1_ras; 1510 mca->mpio.ras = &mca_v3_0_mpio_ras; 1511 } 1512 break; 1513 default: 1514 break; 1515 } 1516 } 1517 1518 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1519 { 1520 if (!adev->gmc.xgmi.connected_to_cpu) 1521 adev->gmc.xgmi.ras = &xgmi_ras; 1522 } 1523 1524 static int gmc_v9_0_early_init(void *handle) 1525 { 1526 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1527 1528 /* 1529 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1530 * in their IP discovery tables 1531 */ 1532 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) || 1533 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 1534 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 1535 adev->gmc.xgmi.supported = true; 1536 1537 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) { 1538 adev->gmc.xgmi.supported = true; 1539 adev->gmc.xgmi.connected_to_cpu = 1540 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1541 } 1542 1543 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 1544 enum amdgpu_pkg_type pkg_type = 1545 adev->smuio.funcs->get_pkg_type(adev); 1546 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1547 * and the APU, can be in used two possible modes: 1548 * - carveout mode 1549 * - native APU mode 1550 * "is_app_apu" can be used to identify the APU in the native 1551 * mode. 1552 */ 1553 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1554 !pci_resource_len(adev->pdev, 0)); 1555 } 1556 1557 gmc_v9_0_set_gmc_funcs(adev); 1558 gmc_v9_0_set_irq_funcs(adev); 1559 gmc_v9_0_set_umc_funcs(adev); 1560 gmc_v9_0_set_mmhub_funcs(adev); 1561 gmc_v9_0_set_mmhub_ras_funcs(adev); 1562 gmc_v9_0_set_gfxhub_funcs(adev); 1563 gmc_v9_0_set_hdp_ras_funcs(adev); 1564 gmc_v9_0_set_mca_ras_funcs(adev); 1565 gmc_v9_0_set_xgmi_ras_funcs(adev); 1566 1567 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1568 adev->gmc.shared_aperture_end = 1569 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1570 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1571 adev->gmc.private_aperture_end = 1572 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1573 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1574 1575 return 0; 1576 } 1577 1578 static int gmc_v9_0_late_init(void *handle) 1579 { 1580 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1581 int r; 1582 1583 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1584 if (r) 1585 return r; 1586 1587 /* 1588 * Workaround performance drop issue with VBIOS enables partial 1589 * writes, while disables HBM ECC for vega10. 1590 */ 1591 if (!amdgpu_sriov_vf(adev) && 1592 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) { 1593 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1594 if (adev->df.funcs && 1595 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1596 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1597 } 1598 } 1599 1600 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1601 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB); 1602 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP); 1603 } 1604 1605 r = amdgpu_gmc_ras_late_init(adev); 1606 if (r) 1607 return r; 1608 1609 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1610 } 1611 1612 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1613 struct amdgpu_gmc *mc) 1614 { 1615 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1616 1617 /* add the xgmi offset of the physical node */ 1618 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1619 if (adev->gmc.xgmi.connected_to_cpu) { 1620 amdgpu_gmc_sysvm_location(adev, mc); 1621 } else { 1622 amdgpu_gmc_vram_location(adev, mc, base); 1623 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 1624 if (!amdgpu_sriov_vf(adev)) 1625 amdgpu_gmc_agp_location(adev, mc); 1626 } 1627 /* base offset of vram pages */ 1628 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1629 1630 /* XXX: add the xgmi offset of the physical node? */ 1631 adev->vm_manager.vram_base_offset += 1632 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1633 } 1634 1635 /** 1636 * gmc_v9_0_mc_init - initialize the memory controller driver params 1637 * 1638 * @adev: amdgpu_device pointer 1639 * 1640 * Look up the amount of vram, vram width, and decide how to place 1641 * vram and gart within the GPU's physical address space. 1642 * Returns 0 for success. 1643 */ 1644 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1645 { 1646 int r; 1647 1648 /* size in MB on si */ 1649 if (!adev->gmc.is_app_apu) { 1650 adev->gmc.mc_vram_size = 1651 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1652 } else { 1653 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1654 adev->gmc.mc_vram_size = 0; 1655 } 1656 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1657 1658 if (!(adev->flags & AMD_IS_APU) && 1659 !adev->gmc.xgmi.connected_to_cpu) { 1660 r = amdgpu_device_resize_fb_bar(adev); 1661 if (r) 1662 return r; 1663 } 1664 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1665 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1666 1667 #ifdef CONFIG_X86_64 1668 /* 1669 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1670 * interface can use VRAM through here as it appears system reserved 1671 * memory in host address space. 1672 * 1673 * For APUs, VRAM is just the stolen system memory and can be accessed 1674 * directly. 1675 * 1676 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1677 */ 1678 1679 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1680 if ((!amdgpu_sriov_vf(adev) && 1681 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1682 (adev->gmc.xgmi.supported && 1683 adev->gmc.xgmi.connected_to_cpu)) { 1684 adev->gmc.aper_base = 1685 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1686 adev->gmc.xgmi.physical_node_id * 1687 adev->gmc.xgmi.node_segment_size; 1688 adev->gmc.aper_size = adev->gmc.real_vram_size; 1689 } 1690 1691 #endif 1692 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1693 1694 /* set the gart size */ 1695 if (amdgpu_gart_size == -1) { 1696 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1697 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1698 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1699 case IP_VERSION(9, 4, 0): 1700 case IP_VERSION(9, 4, 1): 1701 case IP_VERSION(9, 4, 2): 1702 case IP_VERSION(9, 4, 3): 1703 default: 1704 adev->gmc.gart_size = 512ULL << 20; 1705 break; 1706 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1707 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1708 case IP_VERSION(9, 3, 0): 1709 adev->gmc.gart_size = 1024ULL << 20; 1710 break; 1711 } 1712 } else { 1713 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1714 } 1715 1716 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1717 1718 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1719 1720 return 0; 1721 } 1722 1723 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1724 { 1725 int r; 1726 1727 if (adev->gart.bo) { 1728 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1729 return 0; 1730 } 1731 1732 if (adev->gmc.xgmi.connected_to_cpu) { 1733 adev->gmc.vmid0_page_table_depth = 1; 1734 adev->gmc.vmid0_page_table_block_size = 12; 1735 } else { 1736 adev->gmc.vmid0_page_table_depth = 0; 1737 adev->gmc.vmid0_page_table_block_size = 0; 1738 } 1739 1740 /* Initialize common gart structure */ 1741 r = amdgpu_gart_init(adev); 1742 if (r) 1743 return r; 1744 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1745 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1746 AMDGPU_PTE_EXECUTABLE; 1747 1748 if (!adev->gmc.real_vram_size) { 1749 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1750 r = amdgpu_gart_table_ram_alloc(adev); 1751 if (r) 1752 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1753 } else { 1754 r = amdgpu_gart_table_vram_alloc(adev); 1755 if (r) 1756 return r; 1757 1758 if (adev->gmc.xgmi.connected_to_cpu) 1759 r = amdgpu_gmc_pdb0_alloc(adev); 1760 } 1761 1762 return r; 1763 } 1764 1765 /** 1766 * gmc_v9_0_save_registers - saves regs 1767 * 1768 * @adev: amdgpu_device pointer 1769 * 1770 * This saves potential register values that should be 1771 * restored upon resume 1772 */ 1773 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1774 { 1775 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1776 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) 1777 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1778 } 1779 1780 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev) 1781 { 1782 enum amdgpu_memory_partition mode; 1783 u32 supp_modes; 1784 bool valid; 1785 1786 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes); 1787 1788 /* Mode detected by hardware not present in supported modes */ 1789 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && 1790 !(BIT(mode - 1) & supp_modes)) 1791 return false; 1792 1793 switch (mode) { 1794 case UNKNOWN_MEMORY_PARTITION_MODE: 1795 case AMDGPU_NPS1_PARTITION_MODE: 1796 valid = (adev->gmc.num_mem_partitions == 1); 1797 break; 1798 case AMDGPU_NPS2_PARTITION_MODE: 1799 valid = (adev->gmc.num_mem_partitions == 2); 1800 break; 1801 case AMDGPU_NPS4_PARTITION_MODE: 1802 valid = (adev->gmc.num_mem_partitions == 3 || 1803 adev->gmc.num_mem_partitions == 4); 1804 break; 1805 default: 1806 valid = false; 1807 } 1808 1809 return valid; 1810 } 1811 1812 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid) 1813 { 1814 int i; 1815 1816 /* Check if node with id 'nid' is present in 'node_ids' array */ 1817 for (i = 0; i < num_ids; ++i) 1818 if (node_ids[i] == nid) 1819 return true; 1820 1821 return false; 1822 } 1823 1824 static void 1825 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev, 1826 struct amdgpu_mem_partition_info *mem_ranges) 1827 { 1828 struct amdgpu_numa_info numa_info; 1829 int node_ids[MAX_MEM_RANGES]; 1830 int num_ranges = 0, ret; 1831 int num_xcc, xcc_id; 1832 uint32_t xcc_mask; 1833 1834 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1835 xcc_mask = (1U << num_xcc) - 1; 1836 1837 for_each_inst(xcc_id, xcc_mask) { 1838 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 1839 if (ret) 1840 continue; 1841 1842 if (numa_info.nid == NUMA_NO_NODE) { 1843 mem_ranges[0].size = numa_info.size; 1844 mem_ranges[0].numa.node = numa_info.nid; 1845 num_ranges = 1; 1846 break; 1847 } 1848 1849 if (gmc_v9_0_is_node_present(node_ids, num_ranges, 1850 numa_info.nid)) 1851 continue; 1852 1853 node_ids[num_ranges] = numa_info.nid; 1854 mem_ranges[num_ranges].numa.node = numa_info.nid; 1855 mem_ranges[num_ranges].size = numa_info.size; 1856 ++num_ranges; 1857 } 1858 1859 adev->gmc.num_mem_partitions = num_ranges; 1860 } 1861 1862 static void 1863 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, 1864 struct amdgpu_mem_partition_info *mem_ranges) 1865 { 1866 enum amdgpu_memory_partition mode; 1867 u32 start_addr = 0, size; 1868 int i; 1869 1870 mode = gmc_v9_0_query_memory_partition(adev); 1871 1872 switch (mode) { 1873 case UNKNOWN_MEMORY_PARTITION_MODE: 1874 case AMDGPU_NPS1_PARTITION_MODE: 1875 adev->gmc.num_mem_partitions = 1; 1876 break; 1877 case AMDGPU_NPS2_PARTITION_MODE: 1878 adev->gmc.num_mem_partitions = 2; 1879 break; 1880 case AMDGPU_NPS4_PARTITION_MODE: 1881 if (adev->flags & AMD_IS_APU) 1882 adev->gmc.num_mem_partitions = 3; 1883 else 1884 adev->gmc.num_mem_partitions = 4; 1885 break; 1886 default: 1887 adev->gmc.num_mem_partitions = 1; 1888 break; 1889 } 1890 1891 size = adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT; 1892 size /= adev->gmc.num_mem_partitions; 1893 1894 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 1895 mem_ranges[i].range.fpfn = start_addr; 1896 mem_ranges[i].size = ((u64)size << AMDGPU_GPU_PAGE_SHIFT); 1897 mem_ranges[i].range.lpfn = start_addr + size - 1; 1898 start_addr += size; 1899 } 1900 1901 /* Adjust the last one */ 1902 mem_ranges[adev->gmc.num_mem_partitions - 1].range.lpfn = 1903 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; 1904 mem_ranges[adev->gmc.num_mem_partitions - 1].size = 1905 adev->gmc.real_vram_size - 1906 ((u64)mem_ranges[adev->gmc.num_mem_partitions - 1].range.fpfn 1907 << AMDGPU_GPU_PAGE_SHIFT); 1908 } 1909 1910 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev) 1911 { 1912 bool valid; 1913 1914 adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES, 1915 sizeof(struct amdgpu_mem_partition_info), 1916 GFP_KERNEL); 1917 if (!adev->gmc.mem_partitions) 1918 return -ENOMEM; 1919 1920 /* TODO : Get the range from PSP/Discovery for dGPU */ 1921 if (adev->gmc.is_app_apu) 1922 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); 1923 else 1924 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 1925 1926 if (amdgpu_sriov_vf(adev)) 1927 valid = true; 1928 else 1929 valid = gmc_v9_0_validate_partition_info(adev); 1930 if (!valid) { 1931 /* TODO: handle invalid case */ 1932 dev_WARN(adev->dev, 1933 "Mem ranges not matching with hardware config"); 1934 } 1935 1936 return 0; 1937 } 1938 1939 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 1940 { 1941 static const u32 regBIF_BIOS_SCRATCH_4 = 0x50; 1942 u32 vram_info; 1943 1944 if (!amdgpu_sriov_vf(adev)) { 1945 vram_info = RREG32(regBIF_BIOS_SCRATCH_4); 1946 adev->gmc.vram_vendor = vram_info & 0xF; 1947 } 1948 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1949 adev->gmc.vram_width = 128 * 64; 1950 } 1951 1952 static int gmc_v9_0_sw_init(void *handle) 1953 { 1954 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 1955 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1956 unsigned long inst_mask = adev->aid_mask; 1957 1958 adev->gfxhub.funcs->init(adev); 1959 1960 adev->mmhub.funcs->init(adev); 1961 1962 spin_lock_init(&adev->gmc.invalidate_lock); 1963 1964 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 1965 gmc_v9_4_3_init_vram_info(adev); 1966 } else if (!adev->bios) { 1967 if (adev->flags & AMD_IS_APU) { 1968 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 1969 adev->gmc.vram_width = 64 * 64; 1970 } else { 1971 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1972 adev->gmc.vram_width = 128 * 64; 1973 } 1974 } else { 1975 r = amdgpu_atomfirmware_get_vram_info(adev, 1976 &vram_width, &vram_type, &vram_vendor); 1977 if (amdgpu_sriov_vf(adev)) 1978 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1979 * and DF related registers is not readable, seems hardcord is the 1980 * only way to set the correct vram_width 1981 */ 1982 adev->gmc.vram_width = 2048; 1983 else if (amdgpu_emu_mode != 1) 1984 adev->gmc.vram_width = vram_width; 1985 1986 if (!adev->gmc.vram_width) { 1987 int chansize, numchan; 1988 1989 /* hbm memory channel size */ 1990 if (adev->flags & AMD_IS_APU) 1991 chansize = 64; 1992 else 1993 chansize = 128; 1994 if (adev->df.funcs && 1995 adev->df.funcs->get_hbm_channel_number) { 1996 numchan = adev->df.funcs->get_hbm_channel_number(adev); 1997 adev->gmc.vram_width = numchan * chansize; 1998 } 1999 } 2000 2001 adev->gmc.vram_type = vram_type; 2002 adev->gmc.vram_vendor = vram_vendor; 2003 } 2004 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2005 case IP_VERSION(9, 1, 0): 2006 case IP_VERSION(9, 2, 2): 2007 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2008 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2009 2010 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 2011 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2012 } else { 2013 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 2014 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 2015 adev->gmc.translate_further = 2016 adev->vm_manager.num_level > 1; 2017 } 2018 break; 2019 case IP_VERSION(9, 0, 1): 2020 case IP_VERSION(9, 2, 1): 2021 case IP_VERSION(9, 4, 0): 2022 case IP_VERSION(9, 3, 0): 2023 case IP_VERSION(9, 4, 2): 2024 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2025 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2026 2027 /* 2028 * To fulfill 4-level page support, 2029 * vm size is 256TB (48bit), maximum size of Vega10, 2030 * block size 512 (9bit) 2031 */ 2032 2033 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2034 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 2035 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2036 break; 2037 case IP_VERSION(9, 4, 1): 2038 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2039 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2040 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 2041 2042 /* Keep the vm size same with Vega20 */ 2043 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2044 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2045 break; 2046 case IP_VERSION(9, 4, 3): 2047 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 2048 NUM_XCC(adev->gfx.xcc_mask)); 2049 2050 inst_mask <<= AMDGPU_MMHUB0(0); 2051 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 2052 2053 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2054 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2055 break; 2056 default: 2057 break; 2058 } 2059 2060 /* This interrupt is VMC page fault.*/ 2061 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 2062 &adev->gmc.vm_fault); 2063 if (r) 2064 return r; 2065 2066 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) { 2067 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 2068 &adev->gmc.vm_fault); 2069 if (r) 2070 return r; 2071 } 2072 2073 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 2074 &adev->gmc.vm_fault); 2075 2076 if (r) 2077 return r; 2078 2079 if (!amdgpu_sriov_vf(adev) && 2080 !adev->gmc.xgmi.connected_to_cpu && 2081 !adev->gmc.is_app_apu) { 2082 /* interrupt sent to DF. */ 2083 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 2084 &adev->gmc.ecc_irq); 2085 if (r) 2086 return r; 2087 } 2088 2089 /* Set the internal MC address mask 2090 * This is the max address of the GPU's 2091 * internal address space. 2092 */ 2093 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 2094 2095 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= 2096 IP_VERSION(9, 4, 2) ? 2097 48 : 2098 44; 2099 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 2100 if (r) { 2101 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 2102 return r; 2103 } 2104 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 2105 2106 r = gmc_v9_0_mc_init(adev); 2107 if (r) 2108 return r; 2109 2110 amdgpu_gmc_get_vbios_allocations(adev); 2111 2112 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 2113 r = gmc_v9_0_init_mem_ranges(adev); 2114 if (r) 2115 return r; 2116 } 2117 2118 /* Memory manager */ 2119 r = amdgpu_bo_init(adev); 2120 if (r) 2121 return r; 2122 2123 r = gmc_v9_0_gart_init(adev); 2124 if (r) 2125 return r; 2126 2127 /* 2128 * number of VMs 2129 * VMID 0 is reserved for System 2130 * amdgpu graphics/compute will use VMIDs 1..n-1 2131 * amdkfd will use VMIDs n..15 2132 * 2133 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2134 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2135 * for video processing. 2136 */ 2137 adev->vm_manager.first_kfd_vmid = 2138 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 2139 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 2140 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) ? 2141 3 : 2142 8; 2143 2144 amdgpu_vm_manager_init(adev); 2145 2146 gmc_v9_0_save_registers(adev); 2147 2148 r = amdgpu_gmc_ras_sw_init(adev); 2149 if (r) 2150 return r; 2151 2152 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 2153 amdgpu_gmc_sysfs_init(adev); 2154 2155 return 0; 2156 } 2157 2158 static int gmc_v9_0_sw_fini(void *handle) 2159 { 2160 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2161 2162 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 2163 amdgpu_gmc_sysfs_fini(adev); 2164 adev->gmc.num_mem_partitions = 0; 2165 kfree(adev->gmc.mem_partitions); 2166 2167 amdgpu_gmc_ras_fini(adev); 2168 amdgpu_gem_force_release(adev); 2169 amdgpu_vm_manager_fini(adev); 2170 if (!adev->gmc.real_vram_size) { 2171 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2172 amdgpu_gart_table_ram_free(adev); 2173 } else { 2174 amdgpu_gart_table_vram_free(adev); 2175 } 2176 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2177 amdgpu_bo_fini(adev); 2178 2179 return 0; 2180 } 2181 2182 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2183 { 2184 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 2185 case IP_VERSION(9, 0, 0): 2186 if (amdgpu_sriov_vf(adev)) 2187 break; 2188 fallthrough; 2189 case IP_VERSION(9, 4, 0): 2190 soc15_program_register_sequence(adev, 2191 golden_settings_mmhub_1_0_0, 2192 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2193 soc15_program_register_sequence(adev, 2194 golden_settings_athub_1_0_0, 2195 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2196 break; 2197 case IP_VERSION(9, 1, 0): 2198 case IP_VERSION(9, 2, 0): 2199 /* TODO for renoir */ 2200 soc15_program_register_sequence(adev, 2201 golden_settings_athub_1_0_0, 2202 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2203 break; 2204 default: 2205 break; 2206 } 2207 } 2208 2209 /** 2210 * gmc_v9_0_restore_registers - restores regs 2211 * 2212 * @adev: amdgpu_device pointer 2213 * 2214 * This restores register values, saved at suspend. 2215 */ 2216 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2217 { 2218 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 2219 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) { 2220 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2221 WARN_ON(adev->gmc.sdpif_register != 2222 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2223 } 2224 } 2225 2226 /** 2227 * gmc_v9_0_gart_enable - gart enable 2228 * 2229 * @adev: amdgpu_device pointer 2230 */ 2231 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2232 { 2233 int r; 2234 2235 if (adev->gmc.xgmi.connected_to_cpu) 2236 amdgpu_gmc_init_pdb0(adev); 2237 2238 if (adev->gart.bo == NULL) { 2239 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2240 return -EINVAL; 2241 } 2242 2243 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2244 2245 if (!adev->in_s0ix) { 2246 r = adev->gfxhub.funcs->gart_enable(adev); 2247 if (r) 2248 return r; 2249 } 2250 2251 r = adev->mmhub.funcs->gart_enable(adev); 2252 if (r) 2253 return r; 2254 2255 DRM_INFO("PCIE GART of %uM enabled.\n", 2256 (unsigned int)(adev->gmc.gart_size >> 20)); 2257 if (adev->gmc.pdb0_bo) 2258 DRM_INFO("PDB0 located at 0x%016llX\n", 2259 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2260 DRM_INFO("PTB located at 0x%016llX\n", 2261 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2262 2263 return 0; 2264 } 2265 2266 static int gmc_v9_0_hw_init(void *handle) 2267 { 2268 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2269 bool value; 2270 int i, r; 2271 2272 adev->gmc.flush_pasid_uses_kiq = true; 2273 2274 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush 2275 * (type 2), which flushes both. Due to a race condition with 2276 * concurrent memory accesses using the same TLB cache line, we still 2277 * need a second TLB flush after this. 2278 */ 2279 adev->gmc.flush_tlb_needs_extra_type_2 = 2280 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) && 2281 adev->gmc.xgmi.num_physical_nodes; 2282 /* 2283 * TODO: This workaround is badly documented and had a buggy 2284 * implementation. We should probably verify what we do here. 2285 */ 2286 adev->gmc.flush_tlb_needs_extra_type_0 = 2287 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 2288 adev->rev_id == 0; 2289 2290 /* The sequence of these two function calls matters.*/ 2291 gmc_v9_0_init_golden_registers(adev); 2292 2293 if (adev->mode_info.num_crtc) { 2294 /* Lockout access through VGA aperture*/ 2295 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2296 /* disable VGA render */ 2297 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2298 } 2299 2300 if (adev->mmhub.funcs->update_power_gating) 2301 adev->mmhub.funcs->update_power_gating(adev, true); 2302 2303 adev->hdp.funcs->init_registers(adev); 2304 2305 /* After HDP is initialized, flush HDP.*/ 2306 adev->hdp.funcs->flush_hdp(adev, NULL); 2307 2308 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2309 value = false; 2310 else 2311 value = true; 2312 2313 if (!amdgpu_sriov_vf(adev)) { 2314 if (!adev->in_s0ix) 2315 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2316 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2317 } 2318 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2319 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2320 continue; 2321 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2322 } 2323 2324 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2325 adev->umc.funcs->init_registers(adev); 2326 2327 r = gmc_v9_0_gart_enable(adev); 2328 if (r) 2329 return r; 2330 2331 if (amdgpu_emu_mode == 1) 2332 return amdgpu_gmc_vram_checking(adev); 2333 else 2334 return r; 2335 } 2336 2337 /** 2338 * gmc_v9_0_gart_disable - gart disable 2339 * 2340 * @adev: amdgpu_device pointer 2341 * 2342 * This disables all VM page table. 2343 */ 2344 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2345 { 2346 if (!adev->in_s0ix) 2347 adev->gfxhub.funcs->gart_disable(adev); 2348 adev->mmhub.funcs->gart_disable(adev); 2349 } 2350 2351 static int gmc_v9_0_hw_fini(void *handle) 2352 { 2353 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2354 2355 gmc_v9_0_gart_disable(adev); 2356 2357 if (amdgpu_sriov_vf(adev)) { 2358 /* full access mode, so don't touch any GMC register */ 2359 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2360 return 0; 2361 } 2362 2363 /* 2364 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2365 * a correct cached state for GMC. Otherwise, the "gate" again 2366 * operation on S3 resuming will fail due to wrong cached state. 2367 */ 2368 if (adev->mmhub.funcs->update_power_gating) 2369 adev->mmhub.funcs->update_power_gating(adev, false); 2370 2371 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2372 2373 return 0; 2374 } 2375 2376 static int gmc_v9_0_suspend(void *handle) 2377 { 2378 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2379 2380 return gmc_v9_0_hw_fini(adev); 2381 } 2382 2383 static int gmc_v9_0_resume(void *handle) 2384 { 2385 int r; 2386 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2387 2388 r = gmc_v9_0_hw_init(adev); 2389 if (r) 2390 return r; 2391 2392 amdgpu_vmid_reset_all(adev); 2393 2394 return 0; 2395 } 2396 2397 static bool gmc_v9_0_is_idle(void *handle) 2398 { 2399 /* MC is always ready in GMC v9.*/ 2400 return true; 2401 } 2402 2403 static int gmc_v9_0_wait_for_idle(void *handle) 2404 { 2405 /* There is no need to wait for MC idle in GMC v9.*/ 2406 return 0; 2407 } 2408 2409 static int gmc_v9_0_soft_reset(void *handle) 2410 { 2411 /* XXX for emulation.*/ 2412 return 0; 2413 } 2414 2415 static int gmc_v9_0_set_clockgating_state(void *handle, 2416 enum amd_clockgating_state state) 2417 { 2418 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2419 2420 adev->mmhub.funcs->set_clockgating(adev, state); 2421 2422 athub_v1_0_set_clockgating(adev, state); 2423 2424 return 0; 2425 } 2426 2427 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 2428 { 2429 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2430 2431 adev->mmhub.funcs->get_clockgating(adev, flags); 2432 2433 athub_v1_0_get_clockgating(adev, flags); 2434 } 2435 2436 static int gmc_v9_0_set_powergating_state(void *handle, 2437 enum amd_powergating_state state) 2438 { 2439 return 0; 2440 } 2441 2442 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2443 .name = "gmc_v9_0", 2444 .early_init = gmc_v9_0_early_init, 2445 .late_init = gmc_v9_0_late_init, 2446 .sw_init = gmc_v9_0_sw_init, 2447 .sw_fini = gmc_v9_0_sw_fini, 2448 .hw_init = gmc_v9_0_hw_init, 2449 .hw_fini = gmc_v9_0_hw_fini, 2450 .suspend = gmc_v9_0_suspend, 2451 .resume = gmc_v9_0_resume, 2452 .is_idle = gmc_v9_0_is_idle, 2453 .wait_for_idle = gmc_v9_0_wait_for_idle, 2454 .soft_reset = gmc_v9_0_soft_reset, 2455 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2456 .set_powergating_state = gmc_v9_0_set_powergating_state, 2457 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2458 }; 2459 2460 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = { 2461 .type = AMD_IP_BLOCK_TYPE_GMC, 2462 .major = 9, 2463 .minor = 0, 2464 .rev = 0, 2465 .funcs = &gmc_v9_0_ip_funcs, 2466 }; 2467