1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "umc_v12_0.h" 60 #include "hdp_v4_0.h" 61 #include "mca_v3_0.h" 62 63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 64 65 #include "amdgpu_ras.h" 66 #include "amdgpu_xgmi.h" 67 68 /* add these here since we already include dce12 headers and these are for DCN */ 69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 77 78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 80 81 #define MAX_MEM_RANGES 8 82 83 static const char * const gfxhub_client_ids[] = { 84 "CB", 85 "DB", 86 "IA", 87 "WD", 88 "CPF", 89 "CPC", 90 "CPG", 91 "RLC", 92 "TCP", 93 "SQC (inst)", 94 "SQC (data)", 95 "SQG", 96 "PA", 97 }; 98 99 static const char *mmhub_client_ids_raven[][2] = { 100 [0][0] = "MP1", 101 [1][0] = "MP0", 102 [2][0] = "VCN", 103 [3][0] = "VCNU", 104 [4][0] = "HDP", 105 [5][0] = "DCE", 106 [13][0] = "UTCL2", 107 [19][0] = "TLS", 108 [26][0] = "OSS", 109 [27][0] = "SDMA0", 110 [0][1] = "MP1", 111 [1][1] = "MP0", 112 [2][1] = "VCN", 113 [3][1] = "VCNU", 114 [4][1] = "HDP", 115 [5][1] = "XDP", 116 [6][1] = "DBGU0", 117 [7][1] = "DCE", 118 [8][1] = "DCEDWB0", 119 [9][1] = "DCEDWB1", 120 [26][1] = "OSS", 121 [27][1] = "SDMA0", 122 }; 123 124 static const char *mmhub_client_ids_renoir[][2] = { 125 [0][0] = "MP1", 126 [1][0] = "MP0", 127 [2][0] = "HDP", 128 [4][0] = "DCEDMC", 129 [5][0] = "DCEVGA", 130 [13][0] = "UTCL2", 131 [19][0] = "TLS", 132 [26][0] = "OSS", 133 [27][0] = "SDMA0", 134 [28][0] = "VCN", 135 [29][0] = "VCNU", 136 [30][0] = "JPEG", 137 [0][1] = "MP1", 138 [1][1] = "MP0", 139 [2][1] = "HDP", 140 [3][1] = "XDP", 141 [6][1] = "DBGU0", 142 [7][1] = "DCEDMC", 143 [8][1] = "DCEVGA", 144 [9][1] = "DCEDWB", 145 [26][1] = "OSS", 146 [27][1] = "SDMA0", 147 [28][1] = "VCN", 148 [29][1] = "VCNU", 149 [30][1] = "JPEG", 150 }; 151 152 static const char *mmhub_client_ids_vega10[][2] = { 153 [0][0] = "MP0", 154 [1][0] = "UVD", 155 [2][0] = "UVDU", 156 [3][0] = "HDP", 157 [13][0] = "UTCL2", 158 [14][0] = "OSS", 159 [15][0] = "SDMA1", 160 [32+0][0] = "VCE0", 161 [32+1][0] = "VCE0U", 162 [32+2][0] = "XDMA", 163 [32+3][0] = "DCE", 164 [32+4][0] = "MP1", 165 [32+14][0] = "SDMA0", 166 [0][1] = "MP0", 167 [1][1] = "UVD", 168 [2][1] = "UVDU", 169 [3][1] = "DBGU0", 170 [4][1] = "HDP", 171 [5][1] = "XDP", 172 [14][1] = "OSS", 173 [15][1] = "SDMA0", 174 [32+0][1] = "VCE0", 175 [32+1][1] = "VCE0U", 176 [32+2][1] = "XDMA", 177 [32+3][1] = "DCE", 178 [32+4][1] = "DCEDWB", 179 [32+5][1] = "MP1", 180 [32+6][1] = "DBGU1", 181 [32+14][1] = "SDMA1", 182 }; 183 184 static const char *mmhub_client_ids_vega12[][2] = { 185 [0][0] = "MP0", 186 [1][0] = "VCE0", 187 [2][0] = "VCE0U", 188 [3][0] = "HDP", 189 [13][0] = "UTCL2", 190 [14][0] = "OSS", 191 [15][0] = "SDMA1", 192 [32+0][0] = "DCE", 193 [32+1][0] = "XDMA", 194 [32+2][0] = "UVD", 195 [32+3][0] = "UVDU", 196 [32+4][0] = "MP1", 197 [32+15][0] = "SDMA0", 198 [0][1] = "MP0", 199 [1][1] = "VCE0", 200 [2][1] = "VCE0U", 201 [3][1] = "DBGU0", 202 [4][1] = "HDP", 203 [5][1] = "XDP", 204 [14][1] = "OSS", 205 [15][1] = "SDMA0", 206 [32+0][1] = "DCE", 207 [32+1][1] = "DCEDWB", 208 [32+2][1] = "XDMA", 209 [32+3][1] = "UVD", 210 [32+4][1] = "UVDU", 211 [32+5][1] = "MP1", 212 [32+6][1] = "DBGU1", 213 [32+15][1] = "SDMA1", 214 }; 215 216 static const char *mmhub_client_ids_vega20[][2] = { 217 [0][0] = "XDMA", 218 [1][0] = "DCE", 219 [2][0] = "VCE0", 220 [3][0] = "VCE0U", 221 [4][0] = "UVD", 222 [5][0] = "UVD1U", 223 [13][0] = "OSS", 224 [14][0] = "HDP", 225 [15][0] = "SDMA0", 226 [32+0][0] = "UVD", 227 [32+1][0] = "UVDU", 228 [32+2][0] = "MP1", 229 [32+3][0] = "MP0", 230 [32+12][0] = "UTCL2", 231 [32+14][0] = "SDMA1", 232 [0][1] = "XDMA", 233 [1][1] = "DCE", 234 [2][1] = "DCEDWB", 235 [3][1] = "VCE0", 236 [4][1] = "VCE0U", 237 [5][1] = "UVD1", 238 [6][1] = "UVD1U", 239 [7][1] = "DBGU0", 240 [8][1] = "XDP", 241 [13][1] = "OSS", 242 [14][1] = "HDP", 243 [15][1] = "SDMA0", 244 [32+0][1] = "UVD", 245 [32+1][1] = "UVDU", 246 [32+2][1] = "DBGU1", 247 [32+3][1] = "MP1", 248 [32+4][1] = "MP0", 249 [32+14][1] = "SDMA1", 250 }; 251 252 static const char *mmhub_client_ids_arcturus[][2] = { 253 [0][0] = "DBGU1", 254 [1][0] = "XDP", 255 [2][0] = "MP1", 256 [14][0] = "HDP", 257 [171][0] = "JPEG", 258 [172][0] = "VCN", 259 [173][0] = "VCNU", 260 [203][0] = "JPEG1", 261 [204][0] = "VCN1", 262 [205][0] = "VCN1U", 263 [256][0] = "SDMA0", 264 [257][0] = "SDMA1", 265 [258][0] = "SDMA2", 266 [259][0] = "SDMA3", 267 [260][0] = "SDMA4", 268 [261][0] = "SDMA5", 269 [262][0] = "SDMA6", 270 [263][0] = "SDMA7", 271 [384][0] = "OSS", 272 [0][1] = "DBGU1", 273 [1][1] = "XDP", 274 [2][1] = "MP1", 275 [14][1] = "HDP", 276 [171][1] = "JPEG", 277 [172][1] = "VCN", 278 [173][1] = "VCNU", 279 [203][1] = "JPEG1", 280 [204][1] = "VCN1", 281 [205][1] = "VCN1U", 282 [256][1] = "SDMA0", 283 [257][1] = "SDMA1", 284 [258][1] = "SDMA2", 285 [259][1] = "SDMA3", 286 [260][1] = "SDMA4", 287 [261][1] = "SDMA5", 288 [262][1] = "SDMA6", 289 [263][1] = "SDMA7", 290 [384][1] = "OSS", 291 }; 292 293 static const char *mmhub_client_ids_aldebaran[][2] = { 294 [2][0] = "MP1", 295 [3][0] = "MP0", 296 [32+1][0] = "DBGU_IO0", 297 [32+2][0] = "DBGU_IO2", 298 [32+4][0] = "MPIO", 299 [96+11][0] = "JPEG0", 300 [96+12][0] = "VCN0", 301 [96+13][0] = "VCNU0", 302 [128+11][0] = "JPEG1", 303 [128+12][0] = "VCN1", 304 [128+13][0] = "VCNU1", 305 [160+1][0] = "XDP", 306 [160+14][0] = "HDP", 307 [256+0][0] = "SDMA0", 308 [256+1][0] = "SDMA1", 309 [256+2][0] = "SDMA2", 310 [256+3][0] = "SDMA3", 311 [256+4][0] = "SDMA4", 312 [384+0][0] = "OSS", 313 [2][1] = "MP1", 314 [3][1] = "MP0", 315 [32+1][1] = "DBGU_IO0", 316 [32+2][1] = "DBGU_IO2", 317 [32+4][1] = "MPIO", 318 [96+11][1] = "JPEG0", 319 [96+12][1] = "VCN0", 320 [96+13][1] = "VCNU0", 321 [128+11][1] = "JPEG1", 322 [128+12][1] = "VCN1", 323 [128+13][1] = "VCNU1", 324 [160+1][1] = "XDP", 325 [160+14][1] = "HDP", 326 [256+0][1] = "SDMA0", 327 [256+1][1] = "SDMA1", 328 [256+2][1] = "SDMA2", 329 [256+3][1] = "SDMA3", 330 [256+4][1] = "SDMA4", 331 [384+0][1] = "OSS", 332 }; 333 334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { 335 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 336 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 337 }; 338 339 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { 340 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 341 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 342 }; 343 344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 345 (0x000143c0 + 0x00000000), 346 (0x000143c0 + 0x00000800), 347 (0x000143c0 + 0x00001000), 348 (0x000143c0 + 0x00001800), 349 (0x000543c0 + 0x00000000), 350 (0x000543c0 + 0x00000800), 351 (0x000543c0 + 0x00001000), 352 (0x000543c0 + 0x00001800), 353 (0x000943c0 + 0x00000000), 354 (0x000943c0 + 0x00000800), 355 (0x000943c0 + 0x00001000), 356 (0x000943c0 + 0x00001800), 357 (0x000d43c0 + 0x00000000), 358 (0x000d43c0 + 0x00000800), 359 (0x000d43c0 + 0x00001000), 360 (0x000d43c0 + 0x00001800), 361 (0x001143c0 + 0x00000000), 362 (0x001143c0 + 0x00000800), 363 (0x001143c0 + 0x00001000), 364 (0x001143c0 + 0x00001800), 365 (0x001543c0 + 0x00000000), 366 (0x001543c0 + 0x00000800), 367 (0x001543c0 + 0x00001000), 368 (0x001543c0 + 0x00001800), 369 (0x001943c0 + 0x00000000), 370 (0x001943c0 + 0x00000800), 371 (0x001943c0 + 0x00001000), 372 (0x001943c0 + 0x00001800), 373 (0x001d43c0 + 0x00000000), 374 (0x001d43c0 + 0x00000800), 375 (0x001d43c0 + 0x00001000), 376 (0x001d43c0 + 0x00001800), 377 }; 378 379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 380 (0x000143e0 + 0x00000000), 381 (0x000143e0 + 0x00000800), 382 (0x000143e0 + 0x00001000), 383 (0x000143e0 + 0x00001800), 384 (0x000543e0 + 0x00000000), 385 (0x000543e0 + 0x00000800), 386 (0x000543e0 + 0x00001000), 387 (0x000543e0 + 0x00001800), 388 (0x000943e0 + 0x00000000), 389 (0x000943e0 + 0x00000800), 390 (0x000943e0 + 0x00001000), 391 (0x000943e0 + 0x00001800), 392 (0x000d43e0 + 0x00000000), 393 (0x000d43e0 + 0x00000800), 394 (0x000d43e0 + 0x00001000), 395 (0x000d43e0 + 0x00001800), 396 (0x001143e0 + 0x00000000), 397 (0x001143e0 + 0x00000800), 398 (0x001143e0 + 0x00001000), 399 (0x001143e0 + 0x00001800), 400 (0x001543e0 + 0x00000000), 401 (0x001543e0 + 0x00000800), 402 (0x001543e0 + 0x00001000), 403 (0x001543e0 + 0x00001800), 404 (0x001943e0 + 0x00000000), 405 (0x001943e0 + 0x00000800), 406 (0x001943e0 + 0x00001000), 407 (0x001943e0 + 0x00001800), 408 (0x001d43e0 + 0x00000000), 409 (0x001d43e0 + 0x00000800), 410 (0x001d43e0 + 0x00001000), 411 (0x001d43e0 + 0x00001800), 412 }; 413 414 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 415 struct amdgpu_irq_src *src, 416 unsigned int type, 417 enum amdgpu_interrupt_state state) 418 { 419 u32 bits, i, tmp, reg; 420 421 /* Devices newer then VEGA10/12 shall have these programming 422 * sequences performed by PSP BL 423 */ 424 if (adev->asic_type >= CHIP_VEGA20) 425 return 0; 426 427 bits = 0x7f; 428 429 switch (state) { 430 case AMDGPU_IRQ_STATE_DISABLE: 431 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 432 reg = ecc_umc_mcumc_ctrl_addrs[i]; 433 tmp = RREG32(reg); 434 tmp &= ~bits; 435 WREG32(reg, tmp); 436 } 437 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 438 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 439 tmp = RREG32(reg); 440 tmp &= ~bits; 441 WREG32(reg, tmp); 442 } 443 break; 444 case AMDGPU_IRQ_STATE_ENABLE: 445 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 446 reg = ecc_umc_mcumc_ctrl_addrs[i]; 447 tmp = RREG32(reg); 448 tmp |= bits; 449 WREG32(reg, tmp); 450 } 451 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 452 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 453 tmp = RREG32(reg); 454 tmp |= bits; 455 WREG32(reg, tmp); 456 } 457 break; 458 default: 459 break; 460 } 461 462 return 0; 463 } 464 465 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 466 struct amdgpu_irq_src *src, 467 unsigned int type, 468 enum amdgpu_interrupt_state state) 469 { 470 struct amdgpu_vmhub *hub; 471 u32 tmp, reg, bits, i, j; 472 473 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 479 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 480 481 switch (state) { 482 case AMDGPU_IRQ_STATE_DISABLE: 483 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 484 hub = &adev->vmhub[j]; 485 for (i = 0; i < 16; i++) { 486 reg = hub->vm_context0_cntl + i; 487 488 /* This works because this interrupt is only 489 * enabled at init/resume and disabled in 490 * fini/suspend, so the overall state doesn't 491 * change over the course of suspend/resume. 492 */ 493 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 494 continue; 495 496 if (j >= AMDGPU_MMHUB0(0)) 497 tmp = RREG32_SOC15_IP(MMHUB, reg); 498 else 499 tmp = RREG32_XCC(reg, j); 500 501 tmp &= ~bits; 502 503 if (j >= AMDGPU_MMHUB0(0)) 504 WREG32_SOC15_IP(MMHUB, reg, tmp); 505 else 506 WREG32_XCC(reg, tmp, j); 507 } 508 } 509 break; 510 case AMDGPU_IRQ_STATE_ENABLE: 511 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 512 hub = &adev->vmhub[j]; 513 for (i = 0; i < 16; i++) { 514 reg = hub->vm_context0_cntl + i; 515 516 /* This works because this interrupt is only 517 * enabled at init/resume and disabled in 518 * fini/suspend, so the overall state doesn't 519 * change over the course of suspend/resume. 520 */ 521 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 522 continue; 523 524 if (j >= AMDGPU_MMHUB0(0)) 525 tmp = RREG32_SOC15_IP(MMHUB, reg); 526 else 527 tmp = RREG32_XCC(reg, j); 528 529 tmp |= bits; 530 531 if (j >= AMDGPU_MMHUB0(0)) 532 WREG32_SOC15_IP(MMHUB, reg, tmp); 533 else 534 WREG32_XCC(reg, tmp, j); 535 } 536 } 537 break; 538 default: 539 break; 540 } 541 542 return 0; 543 } 544 545 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 546 struct amdgpu_irq_src *source, 547 struct amdgpu_iv_entry *entry) 548 { 549 bool retry_fault = !!(entry->src_data[1] & 0x80); 550 bool write_fault = !!(entry->src_data[1] & 0x20); 551 uint32_t status = 0, cid = 0, rw = 0, fed = 0; 552 struct amdgpu_task_info *task_info; 553 struct amdgpu_vmhub *hub; 554 const char *mmhub_cid; 555 const char *hub_name; 556 unsigned int vmhub; 557 u64 addr; 558 uint32_t cam_index = 0; 559 int ret, xcc_id = 0; 560 uint32_t node_id; 561 562 node_id = entry->node_id; 563 564 addr = (u64)entry->src_data[0] << 12; 565 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 566 567 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 568 hub_name = "mmhub0"; 569 vmhub = AMDGPU_MMHUB0(node_id / 4); 570 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 571 hub_name = "mmhub1"; 572 vmhub = AMDGPU_MMHUB1(0); 573 } else { 574 hub_name = "gfxhub0"; 575 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 577 node_id); 578 if (xcc_id < 0) 579 xcc_id = 0; 580 } 581 vmhub = xcc_id; 582 } 583 hub = &adev->vmhub[vmhub]; 584 585 if (retry_fault) { 586 if (adev->irq.retry_cam_enabled) { 587 /* Delegate it to a different ring if the hardware hasn't 588 * already done it. 589 */ 590 if (entry->ih == &adev->irq.ih) { 591 amdgpu_irq_delegate(adev, entry, 8); 592 return 1; 593 } 594 595 cam_index = entry->src_data[2] & 0x3ff; 596 597 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 598 addr, write_fault); 599 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 600 if (ret) 601 return 1; 602 } else { 603 /* Process it onyl if it's the first fault for this address */ 604 if (entry->ih != &adev->irq.ih_soft && 605 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 606 entry->timestamp)) 607 return 1; 608 609 /* Delegate it to a different ring if the hardware hasn't 610 * already done it. 611 */ 612 if (entry->ih == &adev->irq.ih) { 613 amdgpu_irq_delegate(adev, entry, 8); 614 return 1; 615 } 616 617 /* Try to handle the recoverable page faults by filling page 618 * tables 619 */ 620 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 621 addr, write_fault)) 622 return 1; 623 } 624 } 625 626 if (!printk_ratelimit()) 627 return 0; 628 629 dev_err(adev->dev, 630 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name, 631 retry_fault ? "retry" : "no-retry", 632 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 633 634 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 635 if (task_info) { 636 dev_err(adev->dev, 637 " for process %s pid %d thread %s pid %d)\n", 638 task_info->process_name, task_info->tgid, 639 task_info->task_name, task_info->pid); 640 amdgpu_vm_put_task_info(task_info); 641 } 642 643 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 644 addr, entry->client_id, 645 soc15_ih_clientid_name[entry->client_id]); 646 647 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 648 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 649 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 650 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 651 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 652 653 if (amdgpu_sriov_vf(adev)) 654 return 0; 655 656 /* 657 * Issue a dummy read to wait for the status register to 658 * be updated to avoid reading an incorrect value due to 659 * the new fast GRBM interface. 660 */ 661 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 662 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 663 RREG32(hub->vm_l2_pro_fault_status); 664 665 status = RREG32(hub->vm_l2_pro_fault_status); 666 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 667 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 668 fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED); 669 670 /* for fed error, kfd will handle it, return directly */ 671 if (fed && amdgpu_ras_is_poison_mode_supported(adev) && 672 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2))) 673 return 0; 674 675 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 676 677 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub); 678 679 dev_err(adev->dev, 680 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 681 status); 682 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 683 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 684 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 685 gfxhub_client_ids[cid], 686 cid); 687 } else { 688 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 689 case IP_VERSION(9, 0, 0): 690 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 691 break; 692 case IP_VERSION(9, 3, 0): 693 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 694 break; 695 case IP_VERSION(9, 4, 0): 696 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 697 break; 698 case IP_VERSION(9, 4, 1): 699 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 700 break; 701 case IP_VERSION(9, 1, 0): 702 case IP_VERSION(9, 2, 0): 703 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 704 break; 705 case IP_VERSION(1, 5, 0): 706 case IP_VERSION(2, 4, 0): 707 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 708 break; 709 case IP_VERSION(1, 8, 0): 710 case IP_VERSION(9, 4, 2): 711 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 712 break; 713 default: 714 mmhub_cid = NULL; 715 break; 716 } 717 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 718 mmhub_cid ? mmhub_cid : "unknown", cid); 719 } 720 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 721 REG_GET_FIELD(status, 722 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 723 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 724 REG_GET_FIELD(status, 725 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 726 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 727 REG_GET_FIELD(status, 728 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 729 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 730 REG_GET_FIELD(status, 731 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 732 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 733 return 0; 734 } 735 736 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 737 .set = gmc_v9_0_vm_fault_interrupt_state, 738 .process = gmc_v9_0_process_interrupt, 739 }; 740 741 742 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 743 .set = gmc_v9_0_ecc_interrupt_state, 744 .process = amdgpu_umc_process_ecc_irq, 745 }; 746 747 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 748 { 749 adev->gmc.vm_fault.num_types = 1; 750 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 751 752 if (!amdgpu_sriov_vf(adev) && 753 !adev->gmc.xgmi.connected_to_cpu && 754 !adev->gmc.is_app_apu) { 755 adev->gmc.ecc_irq.num_types = 1; 756 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 757 } 758 } 759 760 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 761 uint32_t flush_type) 762 { 763 u32 req = 0; 764 765 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 766 PER_VMID_INVALIDATE_REQ, 1 << vmid); 767 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 768 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 769 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 770 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 771 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 772 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 773 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 774 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 775 776 return req; 777 } 778 779 /** 780 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 781 * 782 * @adev: amdgpu_device pointer 783 * @vmhub: vmhub type 784 * 785 */ 786 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 787 uint32_t vmhub) 788 { 789 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 790 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 791 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 792 return false; 793 794 return ((vmhub == AMDGPU_MMHUB0(0) || 795 vmhub == AMDGPU_MMHUB1(0)) && 796 (!amdgpu_sriov_vf(adev)) && 797 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 798 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 799 } 800 801 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 802 uint8_t vmid, uint16_t *p_pasid) 803 { 804 uint32_t value; 805 806 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 807 + vmid); 808 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 809 810 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 811 } 812 813 /* 814 * GART 815 * VMID 0 is the physical GPU addresses as used by the kernel. 816 * VMIDs 1-15 are used for userspace clients and are handled 817 * by the amdgpu vm/hsa code. 818 */ 819 820 /** 821 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 822 * 823 * @adev: amdgpu_device pointer 824 * @vmid: vm instance to flush 825 * @vmhub: which hub to flush 826 * @flush_type: the flush type 827 * 828 * Flush the TLB for the requested page table using certain type. 829 */ 830 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 831 uint32_t vmhub, uint32_t flush_type) 832 { 833 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 834 u32 j, inv_req, tmp, sem, req, ack, inst; 835 const unsigned int eng = 17; 836 struct amdgpu_vmhub *hub; 837 838 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 839 840 hub = &adev->vmhub[vmhub]; 841 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 842 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 843 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 844 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 845 846 if (vmhub >= AMDGPU_MMHUB0(0)) 847 inst = GET_INST(GC, 0); 848 else 849 inst = vmhub; 850 851 /* This is necessary for SRIOV as well as for GFXOFF to function 852 * properly under bare metal 853 */ 854 if (adev->gfx.kiq[inst].ring.sched.ready && 855 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 856 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 857 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 858 859 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 860 1 << vmid, inst); 861 return; 862 } 863 864 /* This path is needed before KIQ/MES/GFXOFF are set up */ 865 spin_lock(&adev->gmc.invalidate_lock); 866 867 /* 868 * It may lose gpuvm invalidate acknowldege state across power-gating 869 * off cycle, add semaphore acquire before invalidation and semaphore 870 * release after invalidation to avoid entering power gated state 871 * to WA the Issue 872 */ 873 874 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 875 if (use_semaphore) { 876 for (j = 0; j < adev->usec_timeout; j++) { 877 /* a read return value of 1 means semaphore acquire */ 878 if (vmhub >= AMDGPU_MMHUB0(0)) 879 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, inst); 880 else 881 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, inst); 882 if (tmp & 0x1) 883 break; 884 udelay(1); 885 } 886 887 if (j >= adev->usec_timeout) 888 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 889 } 890 891 if (vmhub >= AMDGPU_MMHUB0(0)) 892 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, inst); 893 else 894 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, inst); 895 896 /* 897 * Issue a dummy read to wait for the ACK register to 898 * be cleared to avoid a false ACK due to the new fast 899 * GRBM interface. 900 */ 901 if ((vmhub == AMDGPU_GFXHUB(0)) && 902 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 903 RREG32_NO_KIQ(req); 904 905 for (j = 0; j < adev->usec_timeout; j++) { 906 if (vmhub >= AMDGPU_MMHUB0(0)) 907 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, inst); 908 else 909 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, inst); 910 if (tmp & (1 << vmid)) 911 break; 912 udelay(1); 913 } 914 915 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 916 if (use_semaphore) { 917 /* 918 * add semaphore release after invalidation, 919 * write with 0 means semaphore release 920 */ 921 if (vmhub >= AMDGPU_MMHUB0(0)) 922 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, inst); 923 else 924 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, inst); 925 } 926 927 spin_unlock(&adev->gmc.invalidate_lock); 928 929 if (j < adev->usec_timeout) 930 return; 931 932 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 933 } 934 935 /** 936 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 937 * 938 * @adev: amdgpu_device pointer 939 * @pasid: pasid to be flush 940 * @flush_type: the flush type 941 * @all_hub: flush all hubs 942 * @inst: is used to select which instance of KIQ to use for the invalidation 943 * 944 * Flush the TLB for the requested pasid. 945 */ 946 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 947 uint16_t pasid, uint32_t flush_type, 948 bool all_hub, uint32_t inst) 949 { 950 uint16_t queried; 951 int i, vmid; 952 953 for (vmid = 1; vmid < 16; vmid++) { 954 bool valid; 955 956 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 957 &queried); 958 if (!valid || queried != pasid) 959 continue; 960 961 if (all_hub) { 962 for_each_set_bit(i, adev->vmhubs_mask, 963 AMDGPU_MAX_VMHUBS) 964 gmc_v9_0_flush_gpu_tlb(adev, vmid, i, 965 flush_type); 966 } else { 967 gmc_v9_0_flush_gpu_tlb(adev, vmid, 968 AMDGPU_GFXHUB(0), 969 flush_type); 970 } 971 } 972 } 973 974 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 975 unsigned int vmid, uint64_t pd_addr) 976 { 977 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 978 struct amdgpu_device *adev = ring->adev; 979 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 980 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 981 unsigned int eng = ring->vm_inv_eng; 982 983 /* 984 * It may lose gpuvm invalidate acknowldege state across power-gating 985 * off cycle, add semaphore acquire before invalidation and semaphore 986 * release after invalidation to avoid entering power gated state 987 * to WA the Issue 988 */ 989 990 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 991 if (use_semaphore) 992 /* a read return value of 1 means semaphore acuqire */ 993 amdgpu_ring_emit_reg_wait(ring, 994 hub->vm_inv_eng0_sem + 995 hub->eng_distance * eng, 0x1, 0x1); 996 997 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 998 (hub->ctx_addr_distance * vmid), 999 lower_32_bits(pd_addr)); 1000 1001 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1002 (hub->ctx_addr_distance * vmid), 1003 upper_32_bits(pd_addr)); 1004 1005 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 1006 hub->eng_distance * eng, 1007 hub->vm_inv_eng0_ack + 1008 hub->eng_distance * eng, 1009 req, 1 << vmid); 1010 1011 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1012 if (use_semaphore) 1013 /* 1014 * add semaphore release after invalidation, 1015 * write with 0 means semaphore release 1016 */ 1017 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1018 hub->eng_distance * eng, 0); 1019 1020 return pd_addr; 1021 } 1022 1023 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 1024 unsigned int pasid) 1025 { 1026 struct amdgpu_device *adev = ring->adev; 1027 uint32_t reg; 1028 1029 /* Do nothing because there's no lut register for mmhub1. */ 1030 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 1031 return; 1032 1033 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 1034 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1035 else 1036 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1037 1038 amdgpu_ring_emit_wreg(ring, reg, pasid); 1039 } 1040 1041 /* 1042 * PTE format on VEGA 10: 1043 * 63:59 reserved 1044 * 58:57 mtype 1045 * 56 F 1046 * 55 L 1047 * 54 P 1048 * 53 SW 1049 * 52 T 1050 * 50:48 reserved 1051 * 47:12 4k physical page base address 1052 * 11:7 fragment 1053 * 6 write 1054 * 5 read 1055 * 4 exe 1056 * 3 Z 1057 * 2 snooped 1058 * 1 system 1059 * 0 valid 1060 * 1061 * PDE format on VEGA 10: 1062 * 63:59 block fragment size 1063 * 58:55 reserved 1064 * 54 P 1065 * 53:48 reserved 1066 * 47:6 physical base address of PD or PTE 1067 * 5:3 reserved 1068 * 2 C 1069 * 1 system 1070 * 0 valid 1071 */ 1072 1073 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1074 1075 { 1076 switch (flags) { 1077 case AMDGPU_VM_MTYPE_DEFAULT: 1078 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1079 case AMDGPU_VM_MTYPE_NC: 1080 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1081 case AMDGPU_VM_MTYPE_WC: 1082 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 1083 case AMDGPU_VM_MTYPE_RW: 1084 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 1085 case AMDGPU_VM_MTYPE_CC: 1086 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1087 case AMDGPU_VM_MTYPE_UC: 1088 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 1089 default: 1090 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1091 } 1092 } 1093 1094 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1095 uint64_t *addr, uint64_t *flags) 1096 { 1097 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1098 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1099 BUG_ON(*addr & 0xFFFF00000000003FULL); 1100 1101 if (!adev->gmc.translate_further) 1102 return; 1103 1104 if (level == AMDGPU_VM_PDB1) { 1105 /* Set the block fragment size */ 1106 if (!(*flags & AMDGPU_PDE_PTE)) 1107 *flags |= AMDGPU_PDE_BFS(0x9); 1108 1109 } else if (level == AMDGPU_VM_PDB0) { 1110 if (*flags & AMDGPU_PDE_PTE) { 1111 *flags &= ~AMDGPU_PDE_PTE; 1112 if (!(*flags & AMDGPU_PTE_VALID)) 1113 *addr |= 1 << PAGE_SHIFT; 1114 } else { 1115 *flags |= AMDGPU_PTE_TF; 1116 } 1117 } 1118 } 1119 1120 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1121 struct amdgpu_bo *bo, 1122 struct amdgpu_bo_va_mapping *mapping, 1123 uint64_t *flags) 1124 { 1125 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1126 bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM; 1127 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | AMDGPU_GEM_CREATE_EXT_COHERENT); 1128 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; 1129 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1130 struct amdgpu_vm *vm = mapping->bo_va->base.vm; 1131 unsigned int mtype_local, mtype; 1132 bool snoop = false; 1133 bool is_local; 1134 1135 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1136 case IP_VERSION(9, 4, 1): 1137 case IP_VERSION(9, 4, 2): 1138 if (is_vram) { 1139 if (bo_adev == adev) { 1140 if (uncached) 1141 mtype = MTYPE_UC; 1142 else if (coherent) 1143 mtype = MTYPE_CC; 1144 else 1145 mtype = MTYPE_RW; 1146 /* FIXME: is this still needed? Or does 1147 * amdgpu_ttm_tt_pde_flags already handle this? 1148 */ 1149 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 1150 IP_VERSION(9, 4, 2) || 1151 amdgpu_ip_version(adev, GC_HWIP, 0) == 1152 IP_VERSION(9, 4, 3)) && 1153 adev->gmc.xgmi.connected_to_cpu) 1154 snoop = true; 1155 } else { 1156 if (uncached || coherent) 1157 mtype = MTYPE_UC; 1158 else 1159 mtype = MTYPE_NC; 1160 if (mapping->bo_va->is_xgmi) 1161 snoop = true; 1162 } 1163 } else { 1164 if (uncached || coherent) 1165 mtype = MTYPE_UC; 1166 else 1167 mtype = MTYPE_NC; 1168 /* FIXME: is this still needed? Or does 1169 * amdgpu_ttm_tt_pde_flags already handle this? 1170 */ 1171 snoop = true; 1172 } 1173 break; 1174 case IP_VERSION(9, 4, 3): 1175 case IP_VERSION(9, 4, 4): 1176 /* Only local VRAM BOs or system memory on non-NUMA APUs 1177 * can be assumed to be local in their entirety. Choose 1178 * MTYPE_NC as safe fallback for all system memory BOs on 1179 * NUMA systems. Their MTYPE can be overridden per-page in 1180 * gmc_v9_0_override_vm_pte_flags. 1181 */ 1182 mtype_local = MTYPE_RW; 1183 if (amdgpu_mtype_local == 1) { 1184 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); 1185 mtype_local = MTYPE_NC; 1186 } else if (amdgpu_mtype_local == 2) { 1187 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n"); 1188 mtype_local = MTYPE_CC; 1189 } else { 1190 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); 1191 } 1192 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1193 num_possible_nodes() <= 1) || 1194 (is_vram && adev == bo_adev && 1195 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id); 1196 snoop = true; 1197 if (uncached) { 1198 mtype = MTYPE_UC; 1199 } else if (ext_coherent) { 1200 if (adev->rev_id) 1201 mtype = is_local ? MTYPE_CC : MTYPE_UC; 1202 else 1203 mtype = MTYPE_UC; 1204 } else if (adev->flags & AMD_IS_APU) { 1205 mtype = is_local ? mtype_local : MTYPE_NC; 1206 } else { 1207 /* dGPU */ 1208 if (is_local) 1209 mtype = mtype_local; 1210 else if (is_vram) 1211 mtype = MTYPE_NC; 1212 else 1213 mtype = MTYPE_UC; 1214 } 1215 1216 break; 1217 default: 1218 if (uncached || coherent) 1219 mtype = MTYPE_UC; 1220 else 1221 mtype = MTYPE_NC; 1222 1223 /* FIXME: is this still needed? Or does 1224 * amdgpu_ttm_tt_pde_flags already handle this? 1225 */ 1226 if (!is_vram) 1227 snoop = true; 1228 } 1229 1230 if (mtype != MTYPE_NC) 1231 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1232 AMDGPU_PTE_MTYPE_VG10(mtype); 1233 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1234 } 1235 1236 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1237 struct amdgpu_bo_va_mapping *mapping, 1238 uint64_t *flags) 1239 { 1240 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1241 1242 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1243 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1244 1245 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1246 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1247 1248 if (mapping->flags & AMDGPU_PTE_PRT) { 1249 *flags |= AMDGPU_PTE_PRT; 1250 *flags &= ~AMDGPU_PTE_VALID; 1251 } 1252 1253 if (bo && bo->tbo.resource) 1254 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo, 1255 mapping, flags); 1256 } 1257 1258 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1259 struct amdgpu_vm *vm, 1260 uint64_t addr, uint64_t *flags) 1261 { 1262 int local_node, nid; 1263 1264 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system 1265 * memory can use more efficient MTYPEs. 1266 */ 1267 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3) && 1268 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) 1269 return; 1270 1271 /* Only direct-mapped memory allows us to determine the NUMA node from 1272 * the DMA address. 1273 */ 1274 if (!adev->ram_is_direct_mapped) { 1275 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n"); 1276 return; 1277 } 1278 1279 /* MTYPE_NC is the same default and can be overridden. 1280 * MTYPE_UC will be present if the memory is extended-coherent 1281 * and can also be overridden. 1282 */ 1283 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1284 AMDGPU_PTE_MTYPE_VG10(MTYPE_NC) && 1285 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1286 AMDGPU_PTE_MTYPE_VG10(MTYPE_UC)) { 1287 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n"); 1288 return; 1289 } 1290 1291 /* FIXME: Only supported on native mode for now. For carve-out, the 1292 * NUMA affinity of the GPU/VM needs to come from the PCI info because 1293 * memory partitions are not associated with different NUMA nodes. 1294 */ 1295 if (adev->gmc.is_app_apu && vm->mem_id >= 0) { 1296 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1297 } else { 1298 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n"); 1299 return; 1300 } 1301 1302 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1303 * page or NUMA nodes. 1304 */ 1305 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1306 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n"); 1307 return; 1308 } 1309 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1310 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1311 vm->mem_id, local_node, nid); 1312 if (nid == local_node) { 1313 uint64_t old_flags = *flags; 1314 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) == 1315 AMDGPU_PTE_MTYPE_VG10(MTYPE_NC)) { 1316 unsigned int mtype_local = MTYPE_RW; 1317 1318 if (amdgpu_mtype_local == 1) 1319 mtype_local = MTYPE_NC; 1320 else if (amdgpu_mtype_local == 2) 1321 mtype_local = MTYPE_CC; 1322 1323 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1324 AMDGPU_PTE_MTYPE_VG10(mtype_local); 1325 } else if (adev->rev_id) { 1326 /* MTYPE_UC case */ 1327 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1328 AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1329 } 1330 1331 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n", 1332 old_flags, *flags); 1333 } 1334 } 1335 1336 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1337 { 1338 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1339 unsigned int size; 1340 1341 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1342 1343 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1344 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1345 } else { 1346 u32 viewport; 1347 1348 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1349 case IP_VERSION(1, 0, 0): 1350 case IP_VERSION(1, 0, 1): 1351 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1352 size = (REG_GET_FIELD(viewport, 1353 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1354 REG_GET_FIELD(viewport, 1355 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1356 4); 1357 break; 1358 case IP_VERSION(2, 1, 0): 1359 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1360 size = (REG_GET_FIELD(viewport, 1361 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1362 REG_GET_FIELD(viewport, 1363 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1364 4); 1365 break; 1366 default: 1367 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1368 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1369 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1370 4); 1371 break; 1372 } 1373 } 1374 1375 return size; 1376 } 1377 1378 static enum amdgpu_memory_partition 1379 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes) 1380 { 1381 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE; 1382 1383 if (adev->nbio.funcs->get_memory_partition_mode) 1384 mode = adev->nbio.funcs->get_memory_partition_mode(adev, 1385 supp_modes); 1386 1387 return mode; 1388 } 1389 1390 static enum amdgpu_memory_partition 1391 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev) 1392 { 1393 if (amdgpu_sriov_vf(adev)) 1394 return AMDGPU_NPS1_PARTITION_MODE; 1395 1396 return gmc_v9_0_get_memory_partition(adev, NULL); 1397 } 1398 1399 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1400 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1401 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1402 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1403 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1404 .map_mtype = gmc_v9_0_map_mtype, 1405 .get_vm_pde = gmc_v9_0_get_vm_pde, 1406 .get_vm_pte = gmc_v9_0_get_vm_pte, 1407 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1408 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1409 .query_mem_partition_mode = &gmc_v9_0_query_memory_partition, 1410 }; 1411 1412 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1413 { 1414 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1415 } 1416 1417 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1418 { 1419 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1420 case IP_VERSION(6, 0, 0): 1421 adev->umc.funcs = &umc_v6_0_funcs; 1422 break; 1423 case IP_VERSION(6, 1, 1): 1424 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1425 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1426 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1427 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1428 adev->umc.retire_unit = 1; 1429 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1430 adev->umc.ras = &umc_v6_1_ras; 1431 break; 1432 case IP_VERSION(6, 1, 2): 1433 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1434 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1435 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1436 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1437 adev->umc.retire_unit = 1; 1438 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1439 adev->umc.ras = &umc_v6_1_ras; 1440 break; 1441 case IP_VERSION(6, 7, 0): 1442 adev->umc.max_ras_err_cnt_per_query = 1443 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1444 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1445 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1446 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1447 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1448 if (!adev->gmc.xgmi.connected_to_cpu) 1449 adev->umc.ras = &umc_v6_7_ras; 1450 if (1 & adev->smuio.funcs->get_die_id(adev)) 1451 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1452 else 1453 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1454 break; 1455 case IP_VERSION(12, 0, 0): 1456 adev->umc.max_ras_err_cnt_per_query = 1457 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1458 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM; 1459 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM; 1460 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM; 1461 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET; 1462 adev->umc.active_mask = adev->aid_mask; 1463 adev->umc.retire_unit = UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1464 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1465 adev->umc.ras = &umc_v12_0_ras; 1466 break; 1467 default: 1468 break; 1469 } 1470 } 1471 1472 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1473 { 1474 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1475 case IP_VERSION(9, 4, 1): 1476 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1477 break; 1478 case IP_VERSION(9, 4, 2): 1479 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1480 break; 1481 case IP_VERSION(1, 8, 0): 1482 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1483 break; 1484 default: 1485 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1486 break; 1487 } 1488 } 1489 1490 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1491 { 1492 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1493 case IP_VERSION(9, 4, 0): 1494 adev->mmhub.ras = &mmhub_v1_0_ras; 1495 break; 1496 case IP_VERSION(9, 4, 1): 1497 adev->mmhub.ras = &mmhub_v9_4_ras; 1498 break; 1499 case IP_VERSION(9, 4, 2): 1500 adev->mmhub.ras = &mmhub_v1_7_ras; 1501 break; 1502 case IP_VERSION(1, 8, 0): 1503 adev->mmhub.ras = &mmhub_v1_8_ras; 1504 break; 1505 default: 1506 /* mmhub ras is not available */ 1507 break; 1508 } 1509 } 1510 1511 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1512 { 1513 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1514 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 1515 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1516 else 1517 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1518 } 1519 1520 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1521 { 1522 adev->hdp.ras = &hdp_v4_0_ras; 1523 } 1524 1525 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1526 { 1527 struct amdgpu_mca *mca = &adev->mca; 1528 1529 /* is UMC the right IP to check for MCA? Maybe DF? */ 1530 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1531 case IP_VERSION(6, 7, 0): 1532 if (!adev->gmc.xgmi.connected_to_cpu) { 1533 mca->mp0.ras = &mca_v3_0_mp0_ras; 1534 mca->mp1.ras = &mca_v3_0_mp1_ras; 1535 mca->mpio.ras = &mca_v3_0_mpio_ras; 1536 } 1537 break; 1538 default: 1539 break; 1540 } 1541 } 1542 1543 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1544 { 1545 if (!adev->gmc.xgmi.connected_to_cpu) 1546 adev->gmc.xgmi.ras = &xgmi_ras; 1547 } 1548 1549 static int gmc_v9_0_early_init(void *handle) 1550 { 1551 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1552 1553 /* 1554 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1555 * in their IP discovery tables 1556 */ 1557 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) || 1558 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 1559 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1560 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 1561 adev->gmc.xgmi.supported = true; 1562 1563 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) { 1564 adev->gmc.xgmi.supported = true; 1565 adev->gmc.xgmi.connected_to_cpu = 1566 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1567 } 1568 1569 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1570 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { 1571 enum amdgpu_pkg_type pkg_type = 1572 adev->smuio.funcs->get_pkg_type(adev); 1573 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1574 * and the APU, can be in used two possible modes: 1575 * - carveout mode 1576 * - native APU mode 1577 * "is_app_apu" can be used to identify the APU in the native 1578 * mode. 1579 */ 1580 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1581 !pci_resource_len(adev->pdev, 0)); 1582 } 1583 1584 gmc_v9_0_set_gmc_funcs(adev); 1585 gmc_v9_0_set_irq_funcs(adev); 1586 gmc_v9_0_set_umc_funcs(adev); 1587 gmc_v9_0_set_mmhub_funcs(adev); 1588 gmc_v9_0_set_mmhub_ras_funcs(adev); 1589 gmc_v9_0_set_gfxhub_funcs(adev); 1590 gmc_v9_0_set_hdp_ras_funcs(adev); 1591 gmc_v9_0_set_mca_ras_funcs(adev); 1592 gmc_v9_0_set_xgmi_ras_funcs(adev); 1593 1594 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1595 adev->gmc.shared_aperture_end = 1596 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1597 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1598 adev->gmc.private_aperture_end = 1599 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1600 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1601 1602 return 0; 1603 } 1604 1605 static int gmc_v9_0_late_init(void *handle) 1606 { 1607 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1608 int r; 1609 1610 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1611 if (r) 1612 return r; 1613 1614 /* 1615 * Workaround performance drop issue with VBIOS enables partial 1616 * writes, while disables HBM ECC for vega10. 1617 */ 1618 if (!amdgpu_sriov_vf(adev) && 1619 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) { 1620 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1621 if (adev->df.funcs && 1622 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1623 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1624 } 1625 } 1626 1627 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1628 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB); 1629 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP); 1630 } 1631 1632 r = amdgpu_gmc_ras_late_init(adev); 1633 if (r) 1634 return r; 1635 1636 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1637 } 1638 1639 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1640 struct amdgpu_gmc *mc) 1641 { 1642 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1643 1644 amdgpu_gmc_set_agp_default(adev, mc); 1645 1646 /* add the xgmi offset of the physical node */ 1647 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1648 if (adev->gmc.xgmi.connected_to_cpu) { 1649 amdgpu_gmc_sysvm_location(adev, mc); 1650 } else { 1651 amdgpu_gmc_vram_location(adev, mc, base); 1652 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 1653 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 1654 amdgpu_gmc_agp_location(adev, mc); 1655 } 1656 /* base offset of vram pages */ 1657 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1658 1659 /* XXX: add the xgmi offset of the physical node? */ 1660 adev->vm_manager.vram_base_offset += 1661 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1662 } 1663 1664 /** 1665 * gmc_v9_0_mc_init - initialize the memory controller driver params 1666 * 1667 * @adev: amdgpu_device pointer 1668 * 1669 * Look up the amount of vram, vram width, and decide how to place 1670 * vram and gart within the GPU's physical address space. 1671 * Returns 0 for success. 1672 */ 1673 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1674 { 1675 int r; 1676 1677 /* size in MB on si */ 1678 if (!adev->gmc.is_app_apu) { 1679 adev->gmc.mc_vram_size = 1680 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1681 } else { 1682 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1683 adev->gmc.mc_vram_size = 0; 1684 } 1685 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1686 1687 if (!(adev->flags & AMD_IS_APU) && 1688 !adev->gmc.xgmi.connected_to_cpu) { 1689 r = amdgpu_device_resize_fb_bar(adev); 1690 if (r) 1691 return r; 1692 } 1693 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1694 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1695 1696 #ifdef CONFIG_X86_64 1697 /* 1698 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1699 * interface can use VRAM through here as it appears system reserved 1700 * memory in host address space. 1701 * 1702 * For APUs, VRAM is just the stolen system memory and can be accessed 1703 * directly. 1704 * 1705 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1706 */ 1707 1708 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1709 if ((!amdgpu_sriov_vf(adev) && 1710 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1711 (adev->gmc.xgmi.supported && 1712 adev->gmc.xgmi.connected_to_cpu)) { 1713 adev->gmc.aper_base = 1714 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1715 adev->gmc.xgmi.physical_node_id * 1716 adev->gmc.xgmi.node_segment_size; 1717 adev->gmc.aper_size = adev->gmc.real_vram_size; 1718 } 1719 1720 #endif 1721 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1722 1723 /* set the gart size */ 1724 if (amdgpu_gart_size == -1) { 1725 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1726 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1727 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1728 case IP_VERSION(9, 4, 0): 1729 case IP_VERSION(9, 4, 1): 1730 case IP_VERSION(9, 4, 2): 1731 case IP_VERSION(9, 4, 3): 1732 case IP_VERSION(9, 4, 4): 1733 default: 1734 adev->gmc.gart_size = 512ULL << 20; 1735 break; 1736 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1737 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1738 case IP_VERSION(9, 3, 0): 1739 adev->gmc.gart_size = 1024ULL << 20; 1740 break; 1741 } 1742 } else { 1743 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1744 } 1745 1746 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1747 1748 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1749 1750 return 0; 1751 } 1752 1753 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1754 { 1755 int r; 1756 1757 if (adev->gart.bo) { 1758 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1759 return 0; 1760 } 1761 1762 if (adev->gmc.xgmi.connected_to_cpu) { 1763 adev->gmc.vmid0_page_table_depth = 1; 1764 adev->gmc.vmid0_page_table_block_size = 12; 1765 } else { 1766 adev->gmc.vmid0_page_table_depth = 0; 1767 adev->gmc.vmid0_page_table_block_size = 0; 1768 } 1769 1770 /* Initialize common gart structure */ 1771 r = amdgpu_gart_init(adev); 1772 if (r) 1773 return r; 1774 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1775 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1776 AMDGPU_PTE_EXECUTABLE; 1777 1778 if (!adev->gmc.real_vram_size) { 1779 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1780 r = amdgpu_gart_table_ram_alloc(adev); 1781 if (r) 1782 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1783 } else { 1784 r = amdgpu_gart_table_vram_alloc(adev); 1785 if (r) 1786 return r; 1787 1788 if (adev->gmc.xgmi.connected_to_cpu) 1789 r = amdgpu_gmc_pdb0_alloc(adev); 1790 } 1791 1792 return r; 1793 } 1794 1795 /** 1796 * gmc_v9_0_save_registers - saves regs 1797 * 1798 * @adev: amdgpu_device pointer 1799 * 1800 * This saves potential register values that should be 1801 * restored upon resume 1802 */ 1803 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1804 { 1805 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1806 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) 1807 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1808 } 1809 1810 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev) 1811 { 1812 enum amdgpu_memory_partition mode; 1813 u32 supp_modes; 1814 bool valid; 1815 1816 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes); 1817 1818 /* Mode detected by hardware not present in supported modes */ 1819 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && 1820 !(BIT(mode - 1) & supp_modes)) 1821 return false; 1822 1823 switch (mode) { 1824 case UNKNOWN_MEMORY_PARTITION_MODE: 1825 case AMDGPU_NPS1_PARTITION_MODE: 1826 valid = (adev->gmc.num_mem_partitions == 1); 1827 break; 1828 case AMDGPU_NPS2_PARTITION_MODE: 1829 valid = (adev->gmc.num_mem_partitions == 2); 1830 break; 1831 case AMDGPU_NPS4_PARTITION_MODE: 1832 valid = (adev->gmc.num_mem_partitions == 3 || 1833 adev->gmc.num_mem_partitions == 4); 1834 break; 1835 default: 1836 valid = false; 1837 } 1838 1839 return valid; 1840 } 1841 1842 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid) 1843 { 1844 int i; 1845 1846 /* Check if node with id 'nid' is present in 'node_ids' array */ 1847 for (i = 0; i < num_ids; ++i) 1848 if (node_ids[i] == nid) 1849 return true; 1850 1851 return false; 1852 } 1853 1854 static void 1855 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev, 1856 struct amdgpu_mem_partition_info *mem_ranges) 1857 { 1858 struct amdgpu_numa_info numa_info; 1859 int node_ids[MAX_MEM_RANGES]; 1860 int num_ranges = 0, ret; 1861 int num_xcc, xcc_id; 1862 uint32_t xcc_mask; 1863 1864 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1865 xcc_mask = (1U << num_xcc) - 1; 1866 1867 for_each_inst(xcc_id, xcc_mask) { 1868 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 1869 if (ret) 1870 continue; 1871 1872 if (numa_info.nid == NUMA_NO_NODE) { 1873 mem_ranges[0].size = numa_info.size; 1874 mem_ranges[0].numa.node = numa_info.nid; 1875 num_ranges = 1; 1876 break; 1877 } 1878 1879 if (gmc_v9_0_is_node_present(node_ids, num_ranges, 1880 numa_info.nid)) 1881 continue; 1882 1883 node_ids[num_ranges] = numa_info.nid; 1884 mem_ranges[num_ranges].numa.node = numa_info.nid; 1885 mem_ranges[num_ranges].size = numa_info.size; 1886 ++num_ranges; 1887 } 1888 1889 adev->gmc.num_mem_partitions = num_ranges; 1890 } 1891 1892 static void 1893 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, 1894 struct amdgpu_mem_partition_info *mem_ranges) 1895 { 1896 enum amdgpu_memory_partition mode; 1897 u32 start_addr = 0, size; 1898 int i; 1899 1900 mode = gmc_v9_0_query_memory_partition(adev); 1901 1902 switch (mode) { 1903 case UNKNOWN_MEMORY_PARTITION_MODE: 1904 case AMDGPU_NPS1_PARTITION_MODE: 1905 adev->gmc.num_mem_partitions = 1; 1906 break; 1907 case AMDGPU_NPS2_PARTITION_MODE: 1908 adev->gmc.num_mem_partitions = 2; 1909 break; 1910 case AMDGPU_NPS4_PARTITION_MODE: 1911 if (adev->flags & AMD_IS_APU) 1912 adev->gmc.num_mem_partitions = 3; 1913 else 1914 adev->gmc.num_mem_partitions = 4; 1915 break; 1916 default: 1917 adev->gmc.num_mem_partitions = 1; 1918 break; 1919 } 1920 1921 size = adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT; 1922 size /= adev->gmc.num_mem_partitions; 1923 1924 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 1925 mem_ranges[i].range.fpfn = start_addr; 1926 mem_ranges[i].size = ((u64)size << AMDGPU_GPU_PAGE_SHIFT); 1927 mem_ranges[i].range.lpfn = start_addr + size - 1; 1928 start_addr += size; 1929 } 1930 1931 /* Adjust the last one */ 1932 mem_ranges[adev->gmc.num_mem_partitions - 1].range.lpfn = 1933 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; 1934 mem_ranges[adev->gmc.num_mem_partitions - 1].size = 1935 adev->gmc.real_vram_size - 1936 ((u64)mem_ranges[adev->gmc.num_mem_partitions - 1].range.fpfn 1937 << AMDGPU_GPU_PAGE_SHIFT); 1938 } 1939 1940 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev) 1941 { 1942 bool valid; 1943 1944 adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES, 1945 sizeof(struct amdgpu_mem_partition_info), 1946 GFP_KERNEL); 1947 if (!adev->gmc.mem_partitions) 1948 return -ENOMEM; 1949 1950 /* TODO : Get the range from PSP/Discovery for dGPU */ 1951 if (adev->gmc.is_app_apu) 1952 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); 1953 else 1954 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 1955 1956 if (amdgpu_sriov_vf(adev)) 1957 valid = true; 1958 else 1959 valid = gmc_v9_0_validate_partition_info(adev); 1960 if (!valid) { 1961 /* TODO: handle invalid case */ 1962 dev_WARN(adev->dev, 1963 "Mem ranges not matching with hardware config"); 1964 } 1965 1966 return 0; 1967 } 1968 1969 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 1970 { 1971 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1972 adev->gmc.vram_width = 128 * 64; 1973 } 1974 1975 static int gmc_v9_0_sw_init(void *handle) 1976 { 1977 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 1978 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1979 unsigned long inst_mask = adev->aid_mask; 1980 1981 adev->gfxhub.funcs->init(adev); 1982 1983 adev->mmhub.funcs->init(adev); 1984 1985 spin_lock_init(&adev->gmc.invalidate_lock); 1986 1987 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1988 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { 1989 gmc_v9_4_3_init_vram_info(adev); 1990 } else if (!adev->bios) { 1991 if (adev->flags & AMD_IS_APU) { 1992 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 1993 adev->gmc.vram_width = 64 * 64; 1994 } else { 1995 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1996 adev->gmc.vram_width = 128 * 64; 1997 } 1998 } else { 1999 r = amdgpu_atomfirmware_get_vram_info(adev, 2000 &vram_width, &vram_type, &vram_vendor); 2001 if (amdgpu_sriov_vf(adev)) 2002 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 2003 * and DF related registers is not readable, seems hardcord is the 2004 * only way to set the correct vram_width 2005 */ 2006 adev->gmc.vram_width = 2048; 2007 else if (amdgpu_emu_mode != 1) 2008 adev->gmc.vram_width = vram_width; 2009 2010 if (!adev->gmc.vram_width) { 2011 int chansize, numchan; 2012 2013 /* hbm memory channel size */ 2014 if (adev->flags & AMD_IS_APU) 2015 chansize = 64; 2016 else 2017 chansize = 128; 2018 if (adev->df.funcs && 2019 adev->df.funcs->get_hbm_channel_number) { 2020 numchan = adev->df.funcs->get_hbm_channel_number(adev); 2021 adev->gmc.vram_width = numchan * chansize; 2022 } 2023 } 2024 2025 adev->gmc.vram_type = vram_type; 2026 adev->gmc.vram_vendor = vram_vendor; 2027 } 2028 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2029 case IP_VERSION(9, 1, 0): 2030 case IP_VERSION(9, 2, 2): 2031 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2032 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2033 2034 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 2035 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2036 } else { 2037 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 2038 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 2039 adev->gmc.translate_further = 2040 adev->vm_manager.num_level > 1; 2041 } 2042 break; 2043 case IP_VERSION(9, 0, 1): 2044 case IP_VERSION(9, 2, 1): 2045 case IP_VERSION(9, 4, 0): 2046 case IP_VERSION(9, 3, 0): 2047 case IP_VERSION(9, 4, 2): 2048 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2049 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2050 2051 /* 2052 * To fulfill 4-level page support, 2053 * vm size is 256TB (48bit), maximum size of Vega10, 2054 * block size 512 (9bit) 2055 */ 2056 2057 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2058 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 2059 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2060 break; 2061 case IP_VERSION(9, 4, 1): 2062 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2063 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2064 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 2065 2066 /* Keep the vm size same with Vega20 */ 2067 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2068 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2069 break; 2070 case IP_VERSION(9, 4, 3): 2071 case IP_VERSION(9, 4, 4): 2072 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 2073 NUM_XCC(adev->gfx.xcc_mask)); 2074 2075 inst_mask <<= AMDGPU_MMHUB0(0); 2076 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 2077 2078 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2079 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2080 break; 2081 default: 2082 break; 2083 } 2084 2085 /* This interrupt is VMC page fault.*/ 2086 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 2087 &adev->gmc.vm_fault); 2088 if (r) 2089 return r; 2090 2091 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) { 2092 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 2093 &adev->gmc.vm_fault); 2094 if (r) 2095 return r; 2096 } 2097 2098 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 2099 &adev->gmc.vm_fault); 2100 2101 if (r) 2102 return r; 2103 2104 if (!amdgpu_sriov_vf(adev) && 2105 !adev->gmc.xgmi.connected_to_cpu && 2106 !adev->gmc.is_app_apu) { 2107 /* interrupt sent to DF. */ 2108 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 2109 &adev->gmc.ecc_irq); 2110 if (r) 2111 return r; 2112 } 2113 2114 /* Set the internal MC address mask 2115 * This is the max address of the GPU's 2116 * internal address space. 2117 */ 2118 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 2119 2120 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= 2121 IP_VERSION(9, 4, 2) ? 2122 48 : 2123 44; 2124 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 2125 if (r) { 2126 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 2127 return r; 2128 } 2129 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 2130 2131 r = gmc_v9_0_mc_init(adev); 2132 if (r) 2133 return r; 2134 2135 amdgpu_gmc_get_vbios_allocations(adev); 2136 2137 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2138 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { 2139 r = gmc_v9_0_init_mem_ranges(adev); 2140 if (r) 2141 return r; 2142 } 2143 2144 /* Memory manager */ 2145 r = amdgpu_bo_init(adev); 2146 if (r) 2147 return r; 2148 2149 r = gmc_v9_0_gart_init(adev); 2150 if (r) 2151 return r; 2152 2153 /* 2154 * number of VMs 2155 * VMID 0 is reserved for System 2156 * amdgpu graphics/compute will use VMIDs 1..n-1 2157 * amdkfd will use VMIDs n..15 2158 * 2159 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2160 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2161 * for video processing. 2162 */ 2163 adev->vm_manager.first_kfd_vmid = 2164 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 2165 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 2166 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2167 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) ? 2168 3 : 2169 8; 2170 2171 amdgpu_vm_manager_init(adev); 2172 2173 gmc_v9_0_save_registers(adev); 2174 2175 r = amdgpu_gmc_ras_sw_init(adev); 2176 if (r) 2177 return r; 2178 2179 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2180 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 2181 amdgpu_gmc_sysfs_init(adev); 2182 2183 return 0; 2184 } 2185 2186 static int gmc_v9_0_sw_fini(void *handle) 2187 { 2188 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2189 2190 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2191 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 2192 amdgpu_gmc_sysfs_fini(adev); 2193 2194 amdgpu_gmc_ras_fini(adev); 2195 amdgpu_gem_force_release(adev); 2196 amdgpu_vm_manager_fini(adev); 2197 if (!adev->gmc.real_vram_size) { 2198 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2199 amdgpu_gart_table_ram_free(adev); 2200 } else { 2201 amdgpu_gart_table_vram_free(adev); 2202 } 2203 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2204 amdgpu_bo_fini(adev); 2205 2206 adev->gmc.num_mem_partitions = 0; 2207 kfree(adev->gmc.mem_partitions); 2208 2209 return 0; 2210 } 2211 2212 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2213 { 2214 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 2215 case IP_VERSION(9, 0, 0): 2216 if (amdgpu_sriov_vf(adev)) 2217 break; 2218 fallthrough; 2219 case IP_VERSION(9, 4, 0): 2220 soc15_program_register_sequence(adev, 2221 golden_settings_mmhub_1_0_0, 2222 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2223 soc15_program_register_sequence(adev, 2224 golden_settings_athub_1_0_0, 2225 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2226 break; 2227 case IP_VERSION(9, 1, 0): 2228 case IP_VERSION(9, 2, 0): 2229 /* TODO for renoir */ 2230 soc15_program_register_sequence(adev, 2231 golden_settings_athub_1_0_0, 2232 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2233 break; 2234 default: 2235 break; 2236 } 2237 } 2238 2239 /** 2240 * gmc_v9_0_restore_registers - restores regs 2241 * 2242 * @adev: amdgpu_device pointer 2243 * 2244 * This restores register values, saved at suspend. 2245 */ 2246 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2247 { 2248 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 2249 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) { 2250 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2251 WARN_ON(adev->gmc.sdpif_register != 2252 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2253 } 2254 } 2255 2256 /** 2257 * gmc_v9_0_gart_enable - gart enable 2258 * 2259 * @adev: amdgpu_device pointer 2260 */ 2261 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2262 { 2263 int r; 2264 2265 if (adev->gmc.xgmi.connected_to_cpu) 2266 amdgpu_gmc_init_pdb0(adev); 2267 2268 if (adev->gart.bo == NULL) { 2269 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2270 return -EINVAL; 2271 } 2272 2273 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2274 2275 if (!adev->in_s0ix) { 2276 r = adev->gfxhub.funcs->gart_enable(adev); 2277 if (r) 2278 return r; 2279 } 2280 2281 r = adev->mmhub.funcs->gart_enable(adev); 2282 if (r) 2283 return r; 2284 2285 DRM_INFO("PCIE GART of %uM enabled.\n", 2286 (unsigned int)(adev->gmc.gart_size >> 20)); 2287 if (adev->gmc.pdb0_bo) 2288 DRM_INFO("PDB0 located at 0x%016llX\n", 2289 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2290 DRM_INFO("PTB located at 0x%016llX\n", 2291 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2292 2293 return 0; 2294 } 2295 2296 static int gmc_v9_0_hw_init(void *handle) 2297 { 2298 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2299 bool value; 2300 int i, r; 2301 2302 adev->gmc.flush_pasid_uses_kiq = true; 2303 2304 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush 2305 * (type 2), which flushes both. Due to a race condition with 2306 * concurrent memory accesses using the same TLB cache line, we still 2307 * need a second TLB flush after this. 2308 */ 2309 adev->gmc.flush_tlb_needs_extra_type_2 = 2310 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) && 2311 adev->gmc.xgmi.num_physical_nodes; 2312 /* 2313 * TODO: This workaround is badly documented and had a buggy 2314 * implementation. We should probably verify what we do here. 2315 */ 2316 adev->gmc.flush_tlb_needs_extra_type_0 = 2317 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 2318 adev->rev_id == 0; 2319 2320 /* The sequence of these two function calls matters.*/ 2321 gmc_v9_0_init_golden_registers(adev); 2322 2323 if (adev->mode_info.num_crtc) { 2324 /* Lockout access through VGA aperture*/ 2325 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2326 /* disable VGA render */ 2327 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2328 } 2329 2330 if (adev->mmhub.funcs->update_power_gating) 2331 adev->mmhub.funcs->update_power_gating(adev, true); 2332 2333 adev->hdp.funcs->init_registers(adev); 2334 2335 /* After HDP is initialized, flush HDP.*/ 2336 adev->hdp.funcs->flush_hdp(adev, NULL); 2337 2338 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2339 value = false; 2340 else 2341 value = true; 2342 2343 if (!amdgpu_sriov_vf(adev)) { 2344 if (!adev->in_s0ix) 2345 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2346 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2347 } 2348 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2349 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2350 continue; 2351 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2352 } 2353 2354 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2355 adev->umc.funcs->init_registers(adev); 2356 2357 r = gmc_v9_0_gart_enable(adev); 2358 if (r) 2359 return r; 2360 2361 if (amdgpu_emu_mode == 1) 2362 return amdgpu_gmc_vram_checking(adev); 2363 2364 return 0; 2365 } 2366 2367 /** 2368 * gmc_v9_0_gart_disable - gart disable 2369 * 2370 * @adev: amdgpu_device pointer 2371 * 2372 * This disables all VM page table. 2373 */ 2374 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2375 { 2376 if (!adev->in_s0ix) 2377 adev->gfxhub.funcs->gart_disable(adev); 2378 adev->mmhub.funcs->gart_disable(adev); 2379 } 2380 2381 static int gmc_v9_0_hw_fini(void *handle) 2382 { 2383 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2384 2385 gmc_v9_0_gart_disable(adev); 2386 2387 if (amdgpu_sriov_vf(adev)) { 2388 /* full access mode, so don't touch any GMC register */ 2389 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2390 return 0; 2391 } 2392 2393 /* 2394 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2395 * a correct cached state for GMC. Otherwise, the "gate" again 2396 * operation on S3 resuming will fail due to wrong cached state. 2397 */ 2398 if (adev->mmhub.funcs->update_power_gating) 2399 adev->mmhub.funcs->update_power_gating(adev, false); 2400 2401 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2402 2403 if (adev->gmc.ecc_irq.funcs && 2404 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2405 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 2406 2407 return 0; 2408 } 2409 2410 static int gmc_v9_0_suspend(void *handle) 2411 { 2412 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2413 2414 return gmc_v9_0_hw_fini(adev); 2415 } 2416 2417 static int gmc_v9_0_resume(void *handle) 2418 { 2419 int r; 2420 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2421 2422 r = gmc_v9_0_hw_init(adev); 2423 if (r) 2424 return r; 2425 2426 amdgpu_vmid_reset_all(adev); 2427 2428 return 0; 2429 } 2430 2431 static bool gmc_v9_0_is_idle(void *handle) 2432 { 2433 /* MC is always ready in GMC v9.*/ 2434 return true; 2435 } 2436 2437 static int gmc_v9_0_wait_for_idle(void *handle) 2438 { 2439 /* There is no need to wait for MC idle in GMC v9.*/ 2440 return 0; 2441 } 2442 2443 static int gmc_v9_0_soft_reset(void *handle) 2444 { 2445 /* XXX for emulation.*/ 2446 return 0; 2447 } 2448 2449 static int gmc_v9_0_set_clockgating_state(void *handle, 2450 enum amd_clockgating_state state) 2451 { 2452 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2453 2454 adev->mmhub.funcs->set_clockgating(adev, state); 2455 2456 athub_v1_0_set_clockgating(adev, state); 2457 2458 return 0; 2459 } 2460 2461 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 2462 { 2463 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2464 2465 adev->mmhub.funcs->get_clockgating(adev, flags); 2466 2467 athub_v1_0_get_clockgating(adev, flags); 2468 } 2469 2470 static int gmc_v9_0_set_powergating_state(void *handle, 2471 enum amd_powergating_state state) 2472 { 2473 return 0; 2474 } 2475 2476 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2477 .name = "gmc_v9_0", 2478 .early_init = gmc_v9_0_early_init, 2479 .late_init = gmc_v9_0_late_init, 2480 .sw_init = gmc_v9_0_sw_init, 2481 .sw_fini = gmc_v9_0_sw_fini, 2482 .hw_init = gmc_v9_0_hw_init, 2483 .hw_fini = gmc_v9_0_hw_fini, 2484 .suspend = gmc_v9_0_suspend, 2485 .resume = gmc_v9_0_resume, 2486 .is_idle = gmc_v9_0_is_idle, 2487 .wait_for_idle = gmc_v9_0_wait_for_idle, 2488 .soft_reset = gmc_v9_0_soft_reset, 2489 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2490 .set_powergating_state = gmc_v9_0_set_powergating_state, 2491 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2492 }; 2493 2494 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = { 2495 .type = AMD_IP_BLOCK_TYPE_GMC, 2496 .major = 9, 2497 .minor = 0, 2498 .rev = 0, 2499 .funcs = &gmc_v9_0_ip_funcs, 2500 }; 2501