1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "umc_v12_0.h" 60 #include "hdp_v4_0.h" 61 #include "mca_v3_0.h" 62 63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 64 65 #include "amdgpu_ras.h" 66 #include "amdgpu_xgmi.h" 67 68 /* add these here since we already include dce12 headers and these are for DCN */ 69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 77 78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 80 81 #define MAX_MEM_RANGES 8 82 83 static const char * const gfxhub_client_ids[] = { 84 "CB", 85 "DB", 86 "IA", 87 "WD", 88 "CPF", 89 "CPC", 90 "CPG", 91 "RLC", 92 "TCP", 93 "SQC (inst)", 94 "SQC (data)", 95 "SQG", 96 "PA", 97 }; 98 99 static const char *mmhub_client_ids_raven[][2] = { 100 [0][0] = "MP1", 101 [1][0] = "MP0", 102 [2][0] = "VCN", 103 [3][0] = "VCNU", 104 [4][0] = "HDP", 105 [5][0] = "DCE", 106 [13][0] = "UTCL2", 107 [19][0] = "TLS", 108 [26][0] = "OSS", 109 [27][0] = "SDMA0", 110 [0][1] = "MP1", 111 [1][1] = "MP0", 112 [2][1] = "VCN", 113 [3][1] = "VCNU", 114 [4][1] = "HDP", 115 [5][1] = "XDP", 116 [6][1] = "DBGU0", 117 [7][1] = "DCE", 118 [8][1] = "DCEDWB0", 119 [9][1] = "DCEDWB1", 120 [26][1] = "OSS", 121 [27][1] = "SDMA0", 122 }; 123 124 static const char *mmhub_client_ids_renoir[][2] = { 125 [0][0] = "MP1", 126 [1][0] = "MP0", 127 [2][0] = "HDP", 128 [4][0] = "DCEDMC", 129 [5][0] = "DCEVGA", 130 [13][0] = "UTCL2", 131 [19][0] = "TLS", 132 [26][0] = "OSS", 133 [27][0] = "SDMA0", 134 [28][0] = "VCN", 135 [29][0] = "VCNU", 136 [30][0] = "JPEG", 137 [0][1] = "MP1", 138 [1][1] = "MP0", 139 [2][1] = "HDP", 140 [3][1] = "XDP", 141 [6][1] = "DBGU0", 142 [7][1] = "DCEDMC", 143 [8][1] = "DCEVGA", 144 [9][1] = "DCEDWB", 145 [26][1] = "OSS", 146 [27][1] = "SDMA0", 147 [28][1] = "VCN", 148 [29][1] = "VCNU", 149 [30][1] = "JPEG", 150 }; 151 152 static const char *mmhub_client_ids_vega10[][2] = { 153 [0][0] = "MP0", 154 [1][0] = "UVD", 155 [2][0] = "UVDU", 156 [3][0] = "HDP", 157 [13][0] = "UTCL2", 158 [14][0] = "OSS", 159 [15][0] = "SDMA1", 160 [32+0][0] = "VCE0", 161 [32+1][0] = "VCE0U", 162 [32+2][0] = "XDMA", 163 [32+3][0] = "DCE", 164 [32+4][0] = "MP1", 165 [32+14][0] = "SDMA0", 166 [0][1] = "MP0", 167 [1][1] = "UVD", 168 [2][1] = "UVDU", 169 [3][1] = "DBGU0", 170 [4][1] = "HDP", 171 [5][1] = "XDP", 172 [14][1] = "OSS", 173 [15][1] = "SDMA0", 174 [32+0][1] = "VCE0", 175 [32+1][1] = "VCE0U", 176 [32+2][1] = "XDMA", 177 [32+3][1] = "DCE", 178 [32+4][1] = "DCEDWB", 179 [32+5][1] = "MP1", 180 [32+6][1] = "DBGU1", 181 [32+14][1] = "SDMA1", 182 }; 183 184 static const char *mmhub_client_ids_vega12[][2] = { 185 [0][0] = "MP0", 186 [1][0] = "VCE0", 187 [2][0] = "VCE0U", 188 [3][0] = "HDP", 189 [13][0] = "UTCL2", 190 [14][0] = "OSS", 191 [15][0] = "SDMA1", 192 [32+0][0] = "DCE", 193 [32+1][0] = "XDMA", 194 [32+2][0] = "UVD", 195 [32+3][0] = "UVDU", 196 [32+4][0] = "MP1", 197 [32+15][0] = "SDMA0", 198 [0][1] = "MP0", 199 [1][1] = "VCE0", 200 [2][1] = "VCE0U", 201 [3][1] = "DBGU0", 202 [4][1] = "HDP", 203 [5][1] = "XDP", 204 [14][1] = "OSS", 205 [15][1] = "SDMA0", 206 [32+0][1] = "DCE", 207 [32+1][1] = "DCEDWB", 208 [32+2][1] = "XDMA", 209 [32+3][1] = "UVD", 210 [32+4][1] = "UVDU", 211 [32+5][1] = "MP1", 212 [32+6][1] = "DBGU1", 213 [32+15][1] = "SDMA1", 214 }; 215 216 static const char *mmhub_client_ids_vega20[][2] = { 217 [0][0] = "XDMA", 218 [1][0] = "DCE", 219 [2][0] = "VCE0", 220 [3][0] = "VCE0U", 221 [4][0] = "UVD", 222 [5][0] = "UVD1U", 223 [13][0] = "OSS", 224 [14][0] = "HDP", 225 [15][0] = "SDMA0", 226 [32+0][0] = "UVD", 227 [32+1][0] = "UVDU", 228 [32+2][0] = "MP1", 229 [32+3][0] = "MP0", 230 [32+12][0] = "UTCL2", 231 [32+14][0] = "SDMA1", 232 [0][1] = "XDMA", 233 [1][1] = "DCE", 234 [2][1] = "DCEDWB", 235 [3][1] = "VCE0", 236 [4][1] = "VCE0U", 237 [5][1] = "UVD1", 238 [6][1] = "UVD1U", 239 [7][1] = "DBGU0", 240 [8][1] = "XDP", 241 [13][1] = "OSS", 242 [14][1] = "HDP", 243 [15][1] = "SDMA0", 244 [32+0][1] = "UVD", 245 [32+1][1] = "UVDU", 246 [32+2][1] = "DBGU1", 247 [32+3][1] = "MP1", 248 [32+4][1] = "MP0", 249 [32+14][1] = "SDMA1", 250 }; 251 252 static const char *mmhub_client_ids_arcturus[][2] = { 253 [0][0] = "DBGU1", 254 [1][0] = "XDP", 255 [2][0] = "MP1", 256 [14][0] = "HDP", 257 [171][0] = "JPEG", 258 [172][0] = "VCN", 259 [173][0] = "VCNU", 260 [203][0] = "JPEG1", 261 [204][0] = "VCN1", 262 [205][0] = "VCN1U", 263 [256][0] = "SDMA0", 264 [257][0] = "SDMA1", 265 [258][0] = "SDMA2", 266 [259][0] = "SDMA3", 267 [260][0] = "SDMA4", 268 [261][0] = "SDMA5", 269 [262][0] = "SDMA6", 270 [263][0] = "SDMA7", 271 [384][0] = "OSS", 272 [0][1] = "DBGU1", 273 [1][1] = "XDP", 274 [2][1] = "MP1", 275 [14][1] = "HDP", 276 [171][1] = "JPEG", 277 [172][1] = "VCN", 278 [173][1] = "VCNU", 279 [203][1] = "JPEG1", 280 [204][1] = "VCN1", 281 [205][1] = "VCN1U", 282 [256][1] = "SDMA0", 283 [257][1] = "SDMA1", 284 [258][1] = "SDMA2", 285 [259][1] = "SDMA3", 286 [260][1] = "SDMA4", 287 [261][1] = "SDMA5", 288 [262][1] = "SDMA6", 289 [263][1] = "SDMA7", 290 [384][1] = "OSS", 291 }; 292 293 static const char *mmhub_client_ids_aldebaran[][2] = { 294 [2][0] = "MP1", 295 [3][0] = "MP0", 296 [32+1][0] = "DBGU_IO0", 297 [32+2][0] = "DBGU_IO2", 298 [32+4][0] = "MPIO", 299 [96+11][0] = "JPEG0", 300 [96+12][0] = "VCN0", 301 [96+13][0] = "VCNU0", 302 [128+11][0] = "JPEG1", 303 [128+12][0] = "VCN1", 304 [128+13][0] = "VCNU1", 305 [160+1][0] = "XDP", 306 [160+14][0] = "HDP", 307 [256+0][0] = "SDMA0", 308 [256+1][0] = "SDMA1", 309 [256+2][0] = "SDMA2", 310 [256+3][0] = "SDMA3", 311 [256+4][0] = "SDMA4", 312 [384+0][0] = "OSS", 313 [2][1] = "MP1", 314 [3][1] = "MP0", 315 [32+1][1] = "DBGU_IO0", 316 [32+2][1] = "DBGU_IO2", 317 [32+4][1] = "MPIO", 318 [96+11][1] = "JPEG0", 319 [96+12][1] = "VCN0", 320 [96+13][1] = "VCNU0", 321 [128+11][1] = "JPEG1", 322 [128+12][1] = "VCN1", 323 [128+13][1] = "VCNU1", 324 [160+1][1] = "XDP", 325 [160+14][1] = "HDP", 326 [256+0][1] = "SDMA0", 327 [256+1][1] = "SDMA1", 328 [256+2][1] = "SDMA2", 329 [256+3][1] = "SDMA3", 330 [256+4][1] = "SDMA4", 331 [384+0][1] = "OSS", 332 }; 333 334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { 335 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 336 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 337 }; 338 339 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { 340 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 341 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 342 }; 343 344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 345 (0x000143c0 + 0x00000000), 346 (0x000143c0 + 0x00000800), 347 (0x000143c0 + 0x00001000), 348 (0x000143c0 + 0x00001800), 349 (0x000543c0 + 0x00000000), 350 (0x000543c0 + 0x00000800), 351 (0x000543c0 + 0x00001000), 352 (0x000543c0 + 0x00001800), 353 (0x000943c0 + 0x00000000), 354 (0x000943c0 + 0x00000800), 355 (0x000943c0 + 0x00001000), 356 (0x000943c0 + 0x00001800), 357 (0x000d43c0 + 0x00000000), 358 (0x000d43c0 + 0x00000800), 359 (0x000d43c0 + 0x00001000), 360 (0x000d43c0 + 0x00001800), 361 (0x001143c0 + 0x00000000), 362 (0x001143c0 + 0x00000800), 363 (0x001143c0 + 0x00001000), 364 (0x001143c0 + 0x00001800), 365 (0x001543c0 + 0x00000000), 366 (0x001543c0 + 0x00000800), 367 (0x001543c0 + 0x00001000), 368 (0x001543c0 + 0x00001800), 369 (0x001943c0 + 0x00000000), 370 (0x001943c0 + 0x00000800), 371 (0x001943c0 + 0x00001000), 372 (0x001943c0 + 0x00001800), 373 (0x001d43c0 + 0x00000000), 374 (0x001d43c0 + 0x00000800), 375 (0x001d43c0 + 0x00001000), 376 (0x001d43c0 + 0x00001800), 377 }; 378 379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 380 (0x000143e0 + 0x00000000), 381 (0x000143e0 + 0x00000800), 382 (0x000143e0 + 0x00001000), 383 (0x000143e0 + 0x00001800), 384 (0x000543e0 + 0x00000000), 385 (0x000543e0 + 0x00000800), 386 (0x000543e0 + 0x00001000), 387 (0x000543e0 + 0x00001800), 388 (0x000943e0 + 0x00000000), 389 (0x000943e0 + 0x00000800), 390 (0x000943e0 + 0x00001000), 391 (0x000943e0 + 0x00001800), 392 (0x000d43e0 + 0x00000000), 393 (0x000d43e0 + 0x00000800), 394 (0x000d43e0 + 0x00001000), 395 (0x000d43e0 + 0x00001800), 396 (0x001143e0 + 0x00000000), 397 (0x001143e0 + 0x00000800), 398 (0x001143e0 + 0x00001000), 399 (0x001143e0 + 0x00001800), 400 (0x001543e0 + 0x00000000), 401 (0x001543e0 + 0x00000800), 402 (0x001543e0 + 0x00001000), 403 (0x001543e0 + 0x00001800), 404 (0x001943e0 + 0x00000000), 405 (0x001943e0 + 0x00000800), 406 (0x001943e0 + 0x00001000), 407 (0x001943e0 + 0x00001800), 408 (0x001d43e0 + 0x00000000), 409 (0x001d43e0 + 0x00000800), 410 (0x001d43e0 + 0x00001000), 411 (0x001d43e0 + 0x00001800), 412 }; 413 414 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 415 struct amdgpu_irq_src *src, 416 unsigned int type, 417 enum amdgpu_interrupt_state state) 418 { 419 u32 bits, i, tmp, reg; 420 421 /* Devices newer then VEGA10/12 shall have these programming 422 * sequences performed by PSP BL 423 */ 424 if (adev->asic_type >= CHIP_VEGA20) 425 return 0; 426 427 bits = 0x7f; 428 429 switch (state) { 430 case AMDGPU_IRQ_STATE_DISABLE: 431 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 432 reg = ecc_umc_mcumc_ctrl_addrs[i]; 433 tmp = RREG32(reg); 434 tmp &= ~bits; 435 WREG32(reg, tmp); 436 } 437 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 438 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 439 tmp = RREG32(reg); 440 tmp &= ~bits; 441 WREG32(reg, tmp); 442 } 443 break; 444 case AMDGPU_IRQ_STATE_ENABLE: 445 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 446 reg = ecc_umc_mcumc_ctrl_addrs[i]; 447 tmp = RREG32(reg); 448 tmp |= bits; 449 WREG32(reg, tmp); 450 } 451 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 452 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 453 tmp = RREG32(reg); 454 tmp |= bits; 455 WREG32(reg, tmp); 456 } 457 break; 458 default: 459 break; 460 } 461 462 return 0; 463 } 464 465 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 466 struct amdgpu_irq_src *src, 467 unsigned int type, 468 enum amdgpu_interrupt_state state) 469 { 470 struct amdgpu_vmhub *hub; 471 u32 tmp, reg, bits, i, j; 472 473 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 479 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 480 481 switch (state) { 482 case AMDGPU_IRQ_STATE_DISABLE: 483 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 484 hub = &adev->vmhub[j]; 485 for (i = 0; i < 16; i++) { 486 reg = hub->vm_context0_cntl + i; 487 488 /* This works because this interrupt is only 489 * enabled at init/resume and disabled in 490 * fini/suspend, so the overall state doesn't 491 * change over the course of suspend/resume. 492 */ 493 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 494 continue; 495 496 if (j >= AMDGPU_MMHUB0(0)) 497 tmp = RREG32_SOC15_IP(MMHUB, reg); 498 else 499 tmp = RREG32_SOC15_IP(GC, reg); 500 501 tmp &= ~bits; 502 503 if (j >= AMDGPU_MMHUB0(0)) 504 WREG32_SOC15_IP(MMHUB, reg, tmp); 505 else 506 WREG32_SOC15_IP(GC, reg, tmp); 507 } 508 } 509 break; 510 case AMDGPU_IRQ_STATE_ENABLE: 511 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 512 hub = &adev->vmhub[j]; 513 for (i = 0; i < 16; i++) { 514 reg = hub->vm_context0_cntl + i; 515 516 /* This works because this interrupt is only 517 * enabled at init/resume and disabled in 518 * fini/suspend, so the overall state doesn't 519 * change over the course of suspend/resume. 520 */ 521 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 522 continue; 523 524 if (j >= AMDGPU_MMHUB0(0)) 525 tmp = RREG32_SOC15_IP(MMHUB, reg); 526 else 527 tmp = RREG32_SOC15_IP(GC, reg); 528 529 tmp |= bits; 530 531 if (j >= AMDGPU_MMHUB0(0)) 532 WREG32_SOC15_IP(MMHUB, reg, tmp); 533 else 534 WREG32_SOC15_IP(GC, reg, tmp); 535 } 536 } 537 break; 538 default: 539 break; 540 } 541 542 return 0; 543 } 544 545 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 546 struct amdgpu_irq_src *source, 547 struct amdgpu_iv_entry *entry) 548 { 549 bool retry_fault = !!(entry->src_data[1] & 0x80); 550 bool write_fault = !!(entry->src_data[1] & 0x20); 551 uint32_t status = 0, cid = 0, rw = 0; 552 struct amdgpu_task_info task_info; 553 struct amdgpu_vmhub *hub; 554 const char *mmhub_cid; 555 const char *hub_name; 556 unsigned int vmhub; 557 u64 addr; 558 uint32_t cam_index = 0; 559 int ret, xcc_id = 0; 560 uint32_t node_id; 561 562 node_id = entry->node_id; 563 564 addr = (u64)entry->src_data[0] << 12; 565 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 566 567 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 568 hub_name = "mmhub0"; 569 vmhub = AMDGPU_MMHUB0(node_id / 4); 570 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 571 hub_name = "mmhub1"; 572 vmhub = AMDGPU_MMHUB1(0); 573 } else { 574 hub_name = "gfxhub0"; 575 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 577 node_id); 578 if (xcc_id < 0) 579 xcc_id = 0; 580 } 581 vmhub = xcc_id; 582 } 583 hub = &adev->vmhub[vmhub]; 584 585 if (retry_fault) { 586 if (adev->irq.retry_cam_enabled) { 587 /* Delegate it to a different ring if the hardware hasn't 588 * already done it. 589 */ 590 if (entry->ih == &adev->irq.ih) { 591 amdgpu_irq_delegate(adev, entry, 8); 592 return 1; 593 } 594 595 cam_index = entry->src_data[2] & 0x3ff; 596 597 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 598 addr, write_fault); 599 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 600 if (ret) 601 return 1; 602 } else { 603 /* Process it onyl if it's the first fault for this address */ 604 if (entry->ih != &adev->irq.ih_soft && 605 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 606 entry->timestamp)) 607 return 1; 608 609 /* Delegate it to a different ring if the hardware hasn't 610 * already done it. 611 */ 612 if (entry->ih == &adev->irq.ih) { 613 amdgpu_irq_delegate(adev, entry, 8); 614 return 1; 615 } 616 617 /* Try to handle the recoverable page faults by filling page 618 * tables 619 */ 620 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 621 addr, write_fault)) 622 return 1; 623 } 624 } 625 626 if (!printk_ratelimit()) 627 return 0; 628 629 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 630 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 631 632 dev_err(adev->dev, 633 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n", 634 hub_name, retry_fault ? "retry" : "no-retry", 635 entry->src_id, entry->ring_id, entry->vmid, 636 entry->pasid, task_info.process_name, task_info.tgid, 637 task_info.task_name, task_info.pid); 638 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 639 addr, entry->client_id, 640 soc15_ih_clientid_name[entry->client_id]); 641 642 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 643 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 644 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 645 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 646 647 if (amdgpu_sriov_vf(adev)) 648 return 0; 649 650 /* 651 * Issue a dummy read to wait for the status register to 652 * be updated to avoid reading an incorrect value due to 653 * the new fast GRBM interface. 654 */ 655 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 656 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 657 RREG32(hub->vm_l2_pro_fault_status); 658 659 status = RREG32(hub->vm_l2_pro_fault_status); 660 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 661 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 662 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 663 664 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub); 665 666 dev_err(adev->dev, 667 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 668 status); 669 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 670 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 671 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 672 gfxhub_client_ids[cid], 673 cid); 674 } else { 675 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 676 case IP_VERSION(9, 0, 0): 677 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 678 break; 679 case IP_VERSION(9, 3, 0): 680 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 681 break; 682 case IP_VERSION(9, 4, 0): 683 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 684 break; 685 case IP_VERSION(9, 4, 1): 686 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 687 break; 688 case IP_VERSION(9, 1, 0): 689 case IP_VERSION(9, 2, 0): 690 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 691 break; 692 case IP_VERSION(1, 5, 0): 693 case IP_VERSION(2, 4, 0): 694 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 695 break; 696 case IP_VERSION(1, 8, 0): 697 case IP_VERSION(9, 4, 2): 698 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 699 break; 700 default: 701 mmhub_cid = NULL; 702 break; 703 } 704 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 705 mmhub_cid ? mmhub_cid : "unknown", cid); 706 } 707 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 708 REG_GET_FIELD(status, 709 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 710 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 711 REG_GET_FIELD(status, 712 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 713 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 714 REG_GET_FIELD(status, 715 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 716 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 717 REG_GET_FIELD(status, 718 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 719 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 720 return 0; 721 } 722 723 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 724 .set = gmc_v9_0_vm_fault_interrupt_state, 725 .process = gmc_v9_0_process_interrupt, 726 }; 727 728 729 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 730 .set = gmc_v9_0_ecc_interrupt_state, 731 .process = amdgpu_umc_process_ecc_irq, 732 }; 733 734 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 735 { 736 adev->gmc.vm_fault.num_types = 1; 737 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 738 739 if (!amdgpu_sriov_vf(adev) && 740 !adev->gmc.xgmi.connected_to_cpu && 741 !adev->gmc.is_app_apu) { 742 adev->gmc.ecc_irq.num_types = 1; 743 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 744 } 745 } 746 747 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 748 uint32_t flush_type) 749 { 750 u32 req = 0; 751 752 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 753 PER_VMID_INVALIDATE_REQ, 1 << vmid); 754 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 755 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 756 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 757 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 758 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 759 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 760 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 761 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 762 763 return req; 764 } 765 766 /** 767 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 768 * 769 * @adev: amdgpu_device pointer 770 * @vmhub: vmhub type 771 * 772 */ 773 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 774 uint32_t vmhub) 775 { 776 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 777 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 778 return false; 779 780 return ((vmhub == AMDGPU_MMHUB0(0) || 781 vmhub == AMDGPU_MMHUB1(0)) && 782 (!amdgpu_sriov_vf(adev)) && 783 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 784 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 785 } 786 787 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 788 uint8_t vmid, uint16_t *p_pasid) 789 { 790 uint32_t value; 791 792 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 793 + vmid); 794 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 795 796 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 797 } 798 799 /* 800 * GART 801 * VMID 0 is the physical GPU addresses as used by the kernel. 802 * VMIDs 1-15 are used for userspace clients and are handled 803 * by the amdgpu vm/hsa code. 804 */ 805 806 /** 807 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 808 * 809 * @adev: amdgpu_device pointer 810 * @vmid: vm instance to flush 811 * @vmhub: which hub to flush 812 * @flush_type: the flush type 813 * 814 * Flush the TLB for the requested page table using certain type. 815 */ 816 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 817 uint32_t vmhub, uint32_t flush_type) 818 { 819 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 820 u32 j, inv_req, tmp, sem, req, ack, inst; 821 const unsigned int eng = 17; 822 struct amdgpu_vmhub *hub; 823 824 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 825 826 hub = &adev->vmhub[vmhub]; 827 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 828 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 829 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 830 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 831 832 if (vmhub >= AMDGPU_MMHUB0(0)) 833 inst = GET_INST(GC, 0); 834 else 835 inst = vmhub; 836 837 /* This is necessary for SRIOV as well as for GFXOFF to function 838 * properly under bare metal 839 */ 840 if (adev->gfx.kiq[inst].ring.sched.ready && 841 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 842 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 843 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 844 845 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 846 1 << vmid, inst); 847 return; 848 } 849 850 /* This path is needed before KIQ/MES/GFXOFF are set up */ 851 spin_lock(&adev->gmc.invalidate_lock); 852 853 /* 854 * It may lose gpuvm invalidate acknowldege state across power-gating 855 * off cycle, add semaphore acquire before invalidation and semaphore 856 * release after invalidation to avoid entering power gated state 857 * to WA the Issue 858 */ 859 860 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 861 if (use_semaphore) { 862 for (j = 0; j < adev->usec_timeout; j++) { 863 /* a read return value of 1 means semaphore acquire */ 864 if (vmhub >= AMDGPU_MMHUB0(0)) 865 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, inst); 866 else 867 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, inst); 868 if (tmp & 0x1) 869 break; 870 udelay(1); 871 } 872 873 if (j >= adev->usec_timeout) 874 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 875 } 876 877 if (vmhub >= AMDGPU_MMHUB0(0)) 878 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, inst); 879 else 880 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, inst); 881 882 /* 883 * Issue a dummy read to wait for the ACK register to 884 * be cleared to avoid a false ACK due to the new fast 885 * GRBM interface. 886 */ 887 if ((vmhub == AMDGPU_GFXHUB(0)) && 888 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 889 RREG32_NO_KIQ(req); 890 891 for (j = 0; j < adev->usec_timeout; j++) { 892 if (vmhub >= AMDGPU_MMHUB0(0)) 893 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, inst); 894 else 895 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, inst); 896 if (tmp & (1 << vmid)) 897 break; 898 udelay(1); 899 } 900 901 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 902 if (use_semaphore) { 903 /* 904 * add semaphore release after invalidation, 905 * write with 0 means semaphore release 906 */ 907 if (vmhub >= AMDGPU_MMHUB0(0)) 908 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, inst); 909 else 910 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, inst); 911 } 912 913 spin_unlock(&adev->gmc.invalidate_lock); 914 915 if (j < adev->usec_timeout) 916 return; 917 918 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 919 } 920 921 /** 922 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 923 * 924 * @adev: amdgpu_device pointer 925 * @pasid: pasid to be flush 926 * @flush_type: the flush type 927 * @all_hub: flush all hubs 928 * @inst: is used to select which instance of KIQ to use for the invalidation 929 * 930 * Flush the TLB for the requested pasid. 931 */ 932 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 933 uint16_t pasid, uint32_t flush_type, 934 bool all_hub, uint32_t inst) 935 { 936 uint16_t queried; 937 int i, vmid; 938 939 for (vmid = 1; vmid < 16; vmid++) { 940 bool valid; 941 942 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 943 &queried); 944 if (!valid || queried != pasid) 945 continue; 946 947 if (all_hub) { 948 for_each_set_bit(i, adev->vmhubs_mask, 949 AMDGPU_MAX_VMHUBS) 950 gmc_v9_0_flush_gpu_tlb(adev, vmid, i, 951 flush_type); 952 } else { 953 gmc_v9_0_flush_gpu_tlb(adev, vmid, 954 AMDGPU_GFXHUB(0), 955 flush_type); 956 } 957 } 958 } 959 960 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 961 unsigned int vmid, uint64_t pd_addr) 962 { 963 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 964 struct amdgpu_device *adev = ring->adev; 965 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 966 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 967 unsigned int eng = ring->vm_inv_eng; 968 969 /* 970 * It may lose gpuvm invalidate acknowldege state across power-gating 971 * off cycle, add semaphore acquire before invalidation and semaphore 972 * release after invalidation to avoid entering power gated state 973 * to WA the Issue 974 */ 975 976 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 977 if (use_semaphore) 978 /* a read return value of 1 means semaphore acuqire */ 979 amdgpu_ring_emit_reg_wait(ring, 980 hub->vm_inv_eng0_sem + 981 hub->eng_distance * eng, 0x1, 0x1); 982 983 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 984 (hub->ctx_addr_distance * vmid), 985 lower_32_bits(pd_addr)); 986 987 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 988 (hub->ctx_addr_distance * vmid), 989 upper_32_bits(pd_addr)); 990 991 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 992 hub->eng_distance * eng, 993 hub->vm_inv_eng0_ack + 994 hub->eng_distance * eng, 995 req, 1 << vmid); 996 997 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 998 if (use_semaphore) 999 /* 1000 * add semaphore release after invalidation, 1001 * write with 0 means semaphore release 1002 */ 1003 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1004 hub->eng_distance * eng, 0); 1005 1006 return pd_addr; 1007 } 1008 1009 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 1010 unsigned int pasid) 1011 { 1012 struct amdgpu_device *adev = ring->adev; 1013 uint32_t reg; 1014 1015 /* Do nothing because there's no lut register for mmhub1. */ 1016 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 1017 return; 1018 1019 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 1020 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1021 else 1022 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1023 1024 amdgpu_ring_emit_wreg(ring, reg, pasid); 1025 } 1026 1027 /* 1028 * PTE format on VEGA 10: 1029 * 63:59 reserved 1030 * 58:57 mtype 1031 * 56 F 1032 * 55 L 1033 * 54 P 1034 * 53 SW 1035 * 52 T 1036 * 50:48 reserved 1037 * 47:12 4k physical page base address 1038 * 11:7 fragment 1039 * 6 write 1040 * 5 read 1041 * 4 exe 1042 * 3 Z 1043 * 2 snooped 1044 * 1 system 1045 * 0 valid 1046 * 1047 * PDE format on VEGA 10: 1048 * 63:59 block fragment size 1049 * 58:55 reserved 1050 * 54 P 1051 * 53:48 reserved 1052 * 47:6 physical base address of PD or PTE 1053 * 5:3 reserved 1054 * 2 C 1055 * 1 system 1056 * 0 valid 1057 */ 1058 1059 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1060 1061 { 1062 switch (flags) { 1063 case AMDGPU_VM_MTYPE_DEFAULT: 1064 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1065 case AMDGPU_VM_MTYPE_NC: 1066 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1067 case AMDGPU_VM_MTYPE_WC: 1068 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 1069 case AMDGPU_VM_MTYPE_RW: 1070 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 1071 case AMDGPU_VM_MTYPE_CC: 1072 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1073 case AMDGPU_VM_MTYPE_UC: 1074 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 1075 default: 1076 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1077 } 1078 } 1079 1080 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1081 uint64_t *addr, uint64_t *flags) 1082 { 1083 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1084 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1085 BUG_ON(*addr & 0xFFFF00000000003FULL); 1086 1087 if (!adev->gmc.translate_further) 1088 return; 1089 1090 if (level == AMDGPU_VM_PDB1) { 1091 /* Set the block fragment size */ 1092 if (!(*flags & AMDGPU_PDE_PTE)) 1093 *flags |= AMDGPU_PDE_BFS(0x9); 1094 1095 } else if (level == AMDGPU_VM_PDB0) { 1096 if (*flags & AMDGPU_PDE_PTE) { 1097 *flags &= ~AMDGPU_PDE_PTE; 1098 if (!(*flags & AMDGPU_PTE_VALID)) 1099 *addr |= 1 << PAGE_SHIFT; 1100 } else { 1101 *flags |= AMDGPU_PTE_TF; 1102 } 1103 } 1104 } 1105 1106 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1107 struct amdgpu_bo *bo, 1108 struct amdgpu_bo_va_mapping *mapping, 1109 uint64_t *flags) 1110 { 1111 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1112 bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM; 1113 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | AMDGPU_GEM_CREATE_EXT_COHERENT); 1114 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; 1115 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1116 struct amdgpu_vm *vm = mapping->bo_va->base.vm; 1117 unsigned int mtype_local, mtype; 1118 bool snoop = false; 1119 bool is_local; 1120 1121 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1122 case IP_VERSION(9, 4, 1): 1123 case IP_VERSION(9, 4, 2): 1124 if (is_vram) { 1125 if (bo_adev == adev) { 1126 if (uncached) 1127 mtype = MTYPE_UC; 1128 else if (coherent) 1129 mtype = MTYPE_CC; 1130 else 1131 mtype = MTYPE_RW; 1132 /* FIXME: is this still needed? Or does 1133 * amdgpu_ttm_tt_pde_flags already handle this? 1134 */ 1135 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 1136 IP_VERSION(9, 4, 2) || 1137 amdgpu_ip_version(adev, GC_HWIP, 0) == 1138 IP_VERSION(9, 4, 3)) && 1139 adev->gmc.xgmi.connected_to_cpu) 1140 snoop = true; 1141 } else { 1142 if (uncached || coherent) 1143 mtype = MTYPE_UC; 1144 else 1145 mtype = MTYPE_NC; 1146 if (mapping->bo_va->is_xgmi) 1147 snoop = true; 1148 } 1149 } else { 1150 if (uncached || coherent) 1151 mtype = MTYPE_UC; 1152 else 1153 mtype = MTYPE_NC; 1154 /* FIXME: is this still needed? Or does 1155 * amdgpu_ttm_tt_pde_flags already handle this? 1156 */ 1157 snoop = true; 1158 } 1159 break; 1160 case IP_VERSION(9, 4, 3): 1161 /* Only local VRAM BOs or system memory on non-NUMA APUs 1162 * can be assumed to be local in their entirety. Choose 1163 * MTYPE_NC as safe fallback for all system memory BOs on 1164 * NUMA systems. Their MTYPE can be overridden per-page in 1165 * gmc_v9_0_override_vm_pte_flags. 1166 */ 1167 mtype_local = MTYPE_RW; 1168 if (amdgpu_mtype_local == 1) { 1169 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); 1170 mtype_local = MTYPE_NC; 1171 } else if (amdgpu_mtype_local == 2) { 1172 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n"); 1173 mtype_local = MTYPE_CC; 1174 } else { 1175 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); 1176 } 1177 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1178 num_possible_nodes() <= 1) || 1179 (is_vram && adev == bo_adev && 1180 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id); 1181 snoop = true; 1182 if (uncached) { 1183 mtype = MTYPE_UC; 1184 } else if (ext_coherent) { 1185 if (adev->rev_id) 1186 mtype = is_local ? MTYPE_CC : MTYPE_UC; 1187 else 1188 mtype = MTYPE_UC; 1189 } else if (adev->flags & AMD_IS_APU) { 1190 mtype = is_local ? mtype_local : MTYPE_NC; 1191 } else { 1192 /* dGPU */ 1193 if (is_local) 1194 mtype = mtype_local; 1195 else if (is_vram) 1196 mtype = MTYPE_NC; 1197 else 1198 mtype = MTYPE_UC; 1199 } 1200 1201 break; 1202 default: 1203 if (uncached || coherent) 1204 mtype = MTYPE_UC; 1205 else 1206 mtype = MTYPE_NC; 1207 1208 /* FIXME: is this still needed? Or does 1209 * amdgpu_ttm_tt_pde_flags already handle this? 1210 */ 1211 if (!is_vram) 1212 snoop = true; 1213 } 1214 1215 if (mtype != MTYPE_NC) 1216 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1217 AMDGPU_PTE_MTYPE_VG10(mtype); 1218 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1219 } 1220 1221 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1222 struct amdgpu_bo_va_mapping *mapping, 1223 uint64_t *flags) 1224 { 1225 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1226 1227 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1228 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1229 1230 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1231 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1232 1233 if (mapping->flags & AMDGPU_PTE_PRT) { 1234 *flags |= AMDGPU_PTE_PRT; 1235 *flags &= ~AMDGPU_PTE_VALID; 1236 } 1237 1238 if (bo && bo->tbo.resource) 1239 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo, 1240 mapping, flags); 1241 } 1242 1243 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1244 struct amdgpu_vm *vm, 1245 uint64_t addr, uint64_t *flags) 1246 { 1247 int local_node, nid; 1248 1249 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system 1250 * memory can use more efficient MTYPEs. 1251 */ 1252 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) 1253 return; 1254 1255 /* Only direct-mapped memory allows us to determine the NUMA node from 1256 * the DMA address. 1257 */ 1258 if (!adev->ram_is_direct_mapped) { 1259 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n"); 1260 return; 1261 } 1262 1263 /* MTYPE_NC is the same default and can be overridden. 1264 * MTYPE_UC will be present if the memory is extended-coherent 1265 * and can also be overridden. 1266 */ 1267 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1268 AMDGPU_PTE_MTYPE_VG10(MTYPE_NC) && 1269 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1270 AMDGPU_PTE_MTYPE_VG10(MTYPE_UC)) { 1271 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n"); 1272 return; 1273 } 1274 1275 /* FIXME: Only supported on native mode for now. For carve-out, the 1276 * NUMA affinity of the GPU/VM needs to come from the PCI info because 1277 * memory partitions are not associated with different NUMA nodes. 1278 */ 1279 if (adev->gmc.is_app_apu && vm->mem_id >= 0) { 1280 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1281 } else { 1282 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n"); 1283 return; 1284 } 1285 1286 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1287 * page or NUMA nodes. 1288 */ 1289 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1290 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n"); 1291 return; 1292 } 1293 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1294 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1295 vm->mem_id, local_node, nid); 1296 if (nid == local_node) { 1297 uint64_t old_flags = *flags; 1298 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) == 1299 AMDGPU_PTE_MTYPE_VG10(MTYPE_NC)) { 1300 unsigned int mtype_local = MTYPE_RW; 1301 1302 if (amdgpu_mtype_local == 1) 1303 mtype_local = MTYPE_NC; 1304 else if (amdgpu_mtype_local == 2) 1305 mtype_local = MTYPE_CC; 1306 1307 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1308 AMDGPU_PTE_MTYPE_VG10(mtype_local); 1309 } else if (adev->rev_id) { 1310 /* MTYPE_UC case */ 1311 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1312 AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1313 } 1314 1315 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n", 1316 old_flags, *flags); 1317 } 1318 } 1319 1320 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1321 { 1322 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1323 unsigned int size; 1324 1325 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1326 1327 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1328 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1329 } else { 1330 u32 viewport; 1331 1332 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1333 case IP_VERSION(1, 0, 0): 1334 case IP_VERSION(1, 0, 1): 1335 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1336 size = (REG_GET_FIELD(viewport, 1337 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1338 REG_GET_FIELD(viewport, 1339 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1340 4); 1341 break; 1342 case IP_VERSION(2, 1, 0): 1343 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1344 size = (REG_GET_FIELD(viewport, 1345 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1346 REG_GET_FIELD(viewport, 1347 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1348 4); 1349 break; 1350 default: 1351 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1352 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1353 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1354 4); 1355 break; 1356 } 1357 } 1358 1359 return size; 1360 } 1361 1362 static enum amdgpu_memory_partition 1363 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes) 1364 { 1365 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE; 1366 1367 if (adev->nbio.funcs->get_memory_partition_mode) 1368 mode = adev->nbio.funcs->get_memory_partition_mode(adev, 1369 supp_modes); 1370 1371 return mode; 1372 } 1373 1374 static enum amdgpu_memory_partition 1375 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev) 1376 { 1377 if (amdgpu_sriov_vf(adev)) 1378 return AMDGPU_NPS1_PARTITION_MODE; 1379 1380 return gmc_v9_0_get_memory_partition(adev, NULL); 1381 } 1382 1383 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1384 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1385 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1386 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1387 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1388 .map_mtype = gmc_v9_0_map_mtype, 1389 .get_vm_pde = gmc_v9_0_get_vm_pde, 1390 .get_vm_pte = gmc_v9_0_get_vm_pte, 1391 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1392 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1393 .query_mem_partition_mode = &gmc_v9_0_query_memory_partition, 1394 }; 1395 1396 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1397 { 1398 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1399 } 1400 1401 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1402 { 1403 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1404 case IP_VERSION(6, 0, 0): 1405 adev->umc.funcs = &umc_v6_0_funcs; 1406 break; 1407 case IP_VERSION(6, 1, 1): 1408 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1409 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1410 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1411 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1412 adev->umc.retire_unit = 1; 1413 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1414 adev->umc.ras = &umc_v6_1_ras; 1415 break; 1416 case IP_VERSION(6, 1, 2): 1417 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1418 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1419 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1420 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1421 adev->umc.retire_unit = 1; 1422 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1423 adev->umc.ras = &umc_v6_1_ras; 1424 break; 1425 case IP_VERSION(6, 7, 0): 1426 adev->umc.max_ras_err_cnt_per_query = 1427 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1428 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1429 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1430 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1431 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1432 if (!adev->gmc.xgmi.connected_to_cpu) 1433 adev->umc.ras = &umc_v6_7_ras; 1434 if (1 & adev->smuio.funcs->get_die_id(adev)) 1435 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1436 else 1437 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1438 break; 1439 case IP_VERSION(12, 0, 0): 1440 adev->umc.max_ras_err_cnt_per_query = 1441 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1442 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM; 1443 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM; 1444 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM; 1445 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET; 1446 adev->umc.active_mask = adev->aid_mask; 1447 adev->umc.retire_unit = UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1448 adev->umc.channel_idx_tbl = &umc_v12_0_channel_idx_tbl[0][0][0]; 1449 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1450 adev->umc.ras = &umc_v12_0_ras; 1451 break; 1452 default: 1453 break; 1454 } 1455 } 1456 1457 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1458 { 1459 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1460 case IP_VERSION(9, 4, 1): 1461 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1462 break; 1463 case IP_VERSION(9, 4, 2): 1464 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1465 break; 1466 case IP_VERSION(1, 8, 0): 1467 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1468 break; 1469 default: 1470 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1471 break; 1472 } 1473 } 1474 1475 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1476 { 1477 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1478 case IP_VERSION(9, 4, 0): 1479 adev->mmhub.ras = &mmhub_v1_0_ras; 1480 break; 1481 case IP_VERSION(9, 4, 1): 1482 adev->mmhub.ras = &mmhub_v9_4_ras; 1483 break; 1484 case IP_VERSION(9, 4, 2): 1485 adev->mmhub.ras = &mmhub_v1_7_ras; 1486 break; 1487 case IP_VERSION(1, 8, 0): 1488 adev->mmhub.ras = &mmhub_v1_8_ras; 1489 break; 1490 default: 1491 /* mmhub ras is not available */ 1492 break; 1493 } 1494 } 1495 1496 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1497 { 1498 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 1499 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1500 else 1501 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1502 } 1503 1504 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1505 { 1506 adev->hdp.ras = &hdp_v4_0_ras; 1507 } 1508 1509 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1510 { 1511 struct amdgpu_mca *mca = &adev->mca; 1512 1513 /* is UMC the right IP to check for MCA? Maybe DF? */ 1514 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1515 case IP_VERSION(6, 7, 0): 1516 if (!adev->gmc.xgmi.connected_to_cpu) { 1517 mca->mp0.ras = &mca_v3_0_mp0_ras; 1518 mca->mp1.ras = &mca_v3_0_mp1_ras; 1519 mca->mpio.ras = &mca_v3_0_mpio_ras; 1520 } 1521 break; 1522 default: 1523 break; 1524 } 1525 } 1526 1527 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1528 { 1529 if (!adev->gmc.xgmi.connected_to_cpu) 1530 adev->gmc.xgmi.ras = &xgmi_ras; 1531 } 1532 1533 static int gmc_v9_0_early_init(void *handle) 1534 { 1535 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1536 1537 /* 1538 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1539 * in their IP discovery tables 1540 */ 1541 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) || 1542 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 1543 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 1544 adev->gmc.xgmi.supported = true; 1545 1546 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) { 1547 adev->gmc.xgmi.supported = true; 1548 adev->gmc.xgmi.connected_to_cpu = 1549 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1550 } 1551 1552 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 1553 enum amdgpu_pkg_type pkg_type = 1554 adev->smuio.funcs->get_pkg_type(adev); 1555 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1556 * and the APU, can be in used two possible modes: 1557 * - carveout mode 1558 * - native APU mode 1559 * "is_app_apu" can be used to identify the APU in the native 1560 * mode. 1561 */ 1562 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1563 !pci_resource_len(adev->pdev, 0)); 1564 } 1565 1566 gmc_v9_0_set_gmc_funcs(adev); 1567 gmc_v9_0_set_irq_funcs(adev); 1568 gmc_v9_0_set_umc_funcs(adev); 1569 gmc_v9_0_set_mmhub_funcs(adev); 1570 gmc_v9_0_set_mmhub_ras_funcs(adev); 1571 gmc_v9_0_set_gfxhub_funcs(adev); 1572 gmc_v9_0_set_hdp_ras_funcs(adev); 1573 gmc_v9_0_set_mca_ras_funcs(adev); 1574 gmc_v9_0_set_xgmi_ras_funcs(adev); 1575 1576 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1577 adev->gmc.shared_aperture_end = 1578 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1579 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1580 adev->gmc.private_aperture_end = 1581 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1582 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1583 1584 return 0; 1585 } 1586 1587 static int gmc_v9_0_late_init(void *handle) 1588 { 1589 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1590 int r; 1591 1592 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1593 if (r) 1594 return r; 1595 1596 /* 1597 * Workaround performance drop issue with VBIOS enables partial 1598 * writes, while disables HBM ECC for vega10. 1599 */ 1600 if (!amdgpu_sriov_vf(adev) && 1601 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) { 1602 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1603 if (adev->df.funcs && 1604 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1605 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1606 } 1607 } 1608 1609 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1610 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB); 1611 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP); 1612 } 1613 1614 r = amdgpu_gmc_ras_late_init(adev); 1615 if (r) 1616 return r; 1617 1618 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1619 } 1620 1621 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1622 struct amdgpu_gmc *mc) 1623 { 1624 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1625 1626 amdgpu_gmc_set_agp_default(adev, mc); 1627 1628 /* add the xgmi offset of the physical node */ 1629 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1630 if (adev->gmc.xgmi.connected_to_cpu) { 1631 amdgpu_gmc_sysvm_location(adev, mc); 1632 } else { 1633 amdgpu_gmc_vram_location(adev, mc, base); 1634 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 1635 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 1636 amdgpu_gmc_agp_location(adev, mc); 1637 } 1638 /* base offset of vram pages */ 1639 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1640 1641 /* XXX: add the xgmi offset of the physical node? */ 1642 adev->vm_manager.vram_base_offset += 1643 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1644 } 1645 1646 /** 1647 * gmc_v9_0_mc_init - initialize the memory controller driver params 1648 * 1649 * @adev: amdgpu_device pointer 1650 * 1651 * Look up the amount of vram, vram width, and decide how to place 1652 * vram and gart within the GPU's physical address space. 1653 * Returns 0 for success. 1654 */ 1655 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1656 { 1657 int r; 1658 1659 /* size in MB on si */ 1660 if (!adev->gmc.is_app_apu) { 1661 adev->gmc.mc_vram_size = 1662 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1663 } else { 1664 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1665 adev->gmc.mc_vram_size = 0; 1666 } 1667 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1668 1669 if (!(adev->flags & AMD_IS_APU) && 1670 !adev->gmc.xgmi.connected_to_cpu) { 1671 r = amdgpu_device_resize_fb_bar(adev); 1672 if (r) 1673 return r; 1674 } 1675 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1676 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1677 1678 #ifdef CONFIG_X86_64 1679 /* 1680 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1681 * interface can use VRAM through here as it appears system reserved 1682 * memory in host address space. 1683 * 1684 * For APUs, VRAM is just the stolen system memory and can be accessed 1685 * directly. 1686 * 1687 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1688 */ 1689 1690 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1691 if ((!amdgpu_sriov_vf(adev) && 1692 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1693 (adev->gmc.xgmi.supported && 1694 adev->gmc.xgmi.connected_to_cpu)) { 1695 adev->gmc.aper_base = 1696 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1697 adev->gmc.xgmi.physical_node_id * 1698 adev->gmc.xgmi.node_segment_size; 1699 adev->gmc.aper_size = adev->gmc.real_vram_size; 1700 } 1701 1702 #endif 1703 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1704 1705 /* set the gart size */ 1706 if (amdgpu_gart_size == -1) { 1707 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1708 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1709 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1710 case IP_VERSION(9, 4, 0): 1711 case IP_VERSION(9, 4, 1): 1712 case IP_VERSION(9, 4, 2): 1713 case IP_VERSION(9, 4, 3): 1714 default: 1715 adev->gmc.gart_size = 512ULL << 20; 1716 break; 1717 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1718 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1719 case IP_VERSION(9, 3, 0): 1720 adev->gmc.gart_size = 1024ULL << 20; 1721 break; 1722 } 1723 } else { 1724 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1725 } 1726 1727 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1728 1729 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1730 1731 return 0; 1732 } 1733 1734 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1735 { 1736 int r; 1737 1738 if (adev->gart.bo) { 1739 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1740 return 0; 1741 } 1742 1743 if (adev->gmc.xgmi.connected_to_cpu) { 1744 adev->gmc.vmid0_page_table_depth = 1; 1745 adev->gmc.vmid0_page_table_block_size = 12; 1746 } else { 1747 adev->gmc.vmid0_page_table_depth = 0; 1748 adev->gmc.vmid0_page_table_block_size = 0; 1749 } 1750 1751 /* Initialize common gart structure */ 1752 r = amdgpu_gart_init(adev); 1753 if (r) 1754 return r; 1755 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1756 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1757 AMDGPU_PTE_EXECUTABLE; 1758 1759 if (!adev->gmc.real_vram_size) { 1760 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1761 r = amdgpu_gart_table_ram_alloc(adev); 1762 if (r) 1763 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1764 } else { 1765 r = amdgpu_gart_table_vram_alloc(adev); 1766 if (r) 1767 return r; 1768 1769 if (adev->gmc.xgmi.connected_to_cpu) 1770 r = amdgpu_gmc_pdb0_alloc(adev); 1771 } 1772 1773 return r; 1774 } 1775 1776 /** 1777 * gmc_v9_0_save_registers - saves regs 1778 * 1779 * @adev: amdgpu_device pointer 1780 * 1781 * This saves potential register values that should be 1782 * restored upon resume 1783 */ 1784 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1785 { 1786 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1787 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) 1788 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1789 } 1790 1791 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev) 1792 { 1793 enum amdgpu_memory_partition mode; 1794 u32 supp_modes; 1795 bool valid; 1796 1797 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes); 1798 1799 /* Mode detected by hardware not present in supported modes */ 1800 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && 1801 !(BIT(mode - 1) & supp_modes)) 1802 return false; 1803 1804 switch (mode) { 1805 case UNKNOWN_MEMORY_PARTITION_MODE: 1806 case AMDGPU_NPS1_PARTITION_MODE: 1807 valid = (adev->gmc.num_mem_partitions == 1); 1808 break; 1809 case AMDGPU_NPS2_PARTITION_MODE: 1810 valid = (adev->gmc.num_mem_partitions == 2); 1811 break; 1812 case AMDGPU_NPS4_PARTITION_MODE: 1813 valid = (adev->gmc.num_mem_partitions == 3 || 1814 adev->gmc.num_mem_partitions == 4); 1815 break; 1816 default: 1817 valid = false; 1818 } 1819 1820 return valid; 1821 } 1822 1823 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid) 1824 { 1825 int i; 1826 1827 /* Check if node with id 'nid' is present in 'node_ids' array */ 1828 for (i = 0; i < num_ids; ++i) 1829 if (node_ids[i] == nid) 1830 return true; 1831 1832 return false; 1833 } 1834 1835 static void 1836 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev, 1837 struct amdgpu_mem_partition_info *mem_ranges) 1838 { 1839 struct amdgpu_numa_info numa_info; 1840 int node_ids[MAX_MEM_RANGES]; 1841 int num_ranges = 0, ret; 1842 int num_xcc, xcc_id; 1843 uint32_t xcc_mask; 1844 1845 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1846 xcc_mask = (1U << num_xcc) - 1; 1847 1848 for_each_inst(xcc_id, xcc_mask) { 1849 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 1850 if (ret) 1851 continue; 1852 1853 if (numa_info.nid == NUMA_NO_NODE) { 1854 mem_ranges[0].size = numa_info.size; 1855 mem_ranges[0].numa.node = numa_info.nid; 1856 num_ranges = 1; 1857 break; 1858 } 1859 1860 if (gmc_v9_0_is_node_present(node_ids, num_ranges, 1861 numa_info.nid)) 1862 continue; 1863 1864 node_ids[num_ranges] = numa_info.nid; 1865 mem_ranges[num_ranges].numa.node = numa_info.nid; 1866 mem_ranges[num_ranges].size = numa_info.size; 1867 ++num_ranges; 1868 } 1869 1870 adev->gmc.num_mem_partitions = num_ranges; 1871 } 1872 1873 static void 1874 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, 1875 struct amdgpu_mem_partition_info *mem_ranges) 1876 { 1877 enum amdgpu_memory_partition mode; 1878 u32 start_addr = 0, size; 1879 int i; 1880 1881 mode = gmc_v9_0_query_memory_partition(adev); 1882 1883 switch (mode) { 1884 case UNKNOWN_MEMORY_PARTITION_MODE: 1885 case AMDGPU_NPS1_PARTITION_MODE: 1886 adev->gmc.num_mem_partitions = 1; 1887 break; 1888 case AMDGPU_NPS2_PARTITION_MODE: 1889 adev->gmc.num_mem_partitions = 2; 1890 break; 1891 case AMDGPU_NPS4_PARTITION_MODE: 1892 if (adev->flags & AMD_IS_APU) 1893 adev->gmc.num_mem_partitions = 3; 1894 else 1895 adev->gmc.num_mem_partitions = 4; 1896 break; 1897 default: 1898 adev->gmc.num_mem_partitions = 1; 1899 break; 1900 } 1901 1902 size = adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT; 1903 size /= adev->gmc.num_mem_partitions; 1904 1905 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 1906 mem_ranges[i].range.fpfn = start_addr; 1907 mem_ranges[i].size = ((u64)size << AMDGPU_GPU_PAGE_SHIFT); 1908 mem_ranges[i].range.lpfn = start_addr + size - 1; 1909 start_addr += size; 1910 } 1911 1912 /* Adjust the last one */ 1913 mem_ranges[adev->gmc.num_mem_partitions - 1].range.lpfn = 1914 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; 1915 mem_ranges[adev->gmc.num_mem_partitions - 1].size = 1916 adev->gmc.real_vram_size - 1917 ((u64)mem_ranges[adev->gmc.num_mem_partitions - 1].range.fpfn 1918 << AMDGPU_GPU_PAGE_SHIFT); 1919 } 1920 1921 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev) 1922 { 1923 bool valid; 1924 1925 adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES, 1926 sizeof(struct amdgpu_mem_partition_info), 1927 GFP_KERNEL); 1928 if (!adev->gmc.mem_partitions) 1929 return -ENOMEM; 1930 1931 /* TODO : Get the range from PSP/Discovery for dGPU */ 1932 if (adev->gmc.is_app_apu) 1933 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); 1934 else 1935 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 1936 1937 if (amdgpu_sriov_vf(adev)) 1938 valid = true; 1939 else 1940 valid = gmc_v9_0_validate_partition_info(adev); 1941 if (!valid) { 1942 /* TODO: handle invalid case */ 1943 dev_WARN(adev->dev, 1944 "Mem ranges not matching with hardware config"); 1945 } 1946 1947 return 0; 1948 } 1949 1950 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 1951 { 1952 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1953 adev->gmc.vram_width = 128 * 64; 1954 } 1955 1956 static int gmc_v9_0_sw_init(void *handle) 1957 { 1958 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 1959 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1960 unsigned long inst_mask = adev->aid_mask; 1961 1962 adev->gfxhub.funcs->init(adev); 1963 1964 adev->mmhub.funcs->init(adev); 1965 1966 spin_lock_init(&adev->gmc.invalidate_lock); 1967 1968 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 1969 gmc_v9_4_3_init_vram_info(adev); 1970 } else if (!adev->bios) { 1971 if (adev->flags & AMD_IS_APU) { 1972 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 1973 adev->gmc.vram_width = 64 * 64; 1974 } else { 1975 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1976 adev->gmc.vram_width = 128 * 64; 1977 } 1978 } else { 1979 r = amdgpu_atomfirmware_get_vram_info(adev, 1980 &vram_width, &vram_type, &vram_vendor); 1981 if (amdgpu_sriov_vf(adev)) 1982 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1983 * and DF related registers is not readable, seems hardcord is the 1984 * only way to set the correct vram_width 1985 */ 1986 adev->gmc.vram_width = 2048; 1987 else if (amdgpu_emu_mode != 1) 1988 adev->gmc.vram_width = vram_width; 1989 1990 if (!adev->gmc.vram_width) { 1991 int chansize, numchan; 1992 1993 /* hbm memory channel size */ 1994 if (adev->flags & AMD_IS_APU) 1995 chansize = 64; 1996 else 1997 chansize = 128; 1998 if (adev->df.funcs && 1999 adev->df.funcs->get_hbm_channel_number) { 2000 numchan = adev->df.funcs->get_hbm_channel_number(adev); 2001 adev->gmc.vram_width = numchan * chansize; 2002 } 2003 } 2004 2005 adev->gmc.vram_type = vram_type; 2006 adev->gmc.vram_vendor = vram_vendor; 2007 } 2008 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2009 case IP_VERSION(9, 1, 0): 2010 case IP_VERSION(9, 2, 2): 2011 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2012 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2013 2014 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 2015 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2016 } else { 2017 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 2018 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 2019 adev->gmc.translate_further = 2020 adev->vm_manager.num_level > 1; 2021 } 2022 break; 2023 case IP_VERSION(9, 0, 1): 2024 case IP_VERSION(9, 2, 1): 2025 case IP_VERSION(9, 4, 0): 2026 case IP_VERSION(9, 3, 0): 2027 case IP_VERSION(9, 4, 2): 2028 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2029 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2030 2031 /* 2032 * To fulfill 4-level page support, 2033 * vm size is 256TB (48bit), maximum size of Vega10, 2034 * block size 512 (9bit) 2035 */ 2036 2037 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2038 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 2039 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2040 break; 2041 case IP_VERSION(9, 4, 1): 2042 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2043 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2044 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 2045 2046 /* Keep the vm size same with Vega20 */ 2047 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2048 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2049 break; 2050 case IP_VERSION(9, 4, 3): 2051 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 2052 NUM_XCC(adev->gfx.xcc_mask)); 2053 2054 inst_mask <<= AMDGPU_MMHUB0(0); 2055 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 2056 2057 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2058 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2059 break; 2060 default: 2061 break; 2062 } 2063 2064 /* This interrupt is VMC page fault.*/ 2065 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 2066 &adev->gmc.vm_fault); 2067 if (r) 2068 return r; 2069 2070 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) { 2071 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 2072 &adev->gmc.vm_fault); 2073 if (r) 2074 return r; 2075 } 2076 2077 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 2078 &adev->gmc.vm_fault); 2079 2080 if (r) 2081 return r; 2082 2083 if (!amdgpu_sriov_vf(adev) && 2084 !adev->gmc.xgmi.connected_to_cpu && 2085 !adev->gmc.is_app_apu) { 2086 /* interrupt sent to DF. */ 2087 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 2088 &adev->gmc.ecc_irq); 2089 if (r) 2090 return r; 2091 } 2092 2093 /* Set the internal MC address mask 2094 * This is the max address of the GPU's 2095 * internal address space. 2096 */ 2097 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 2098 2099 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= 2100 IP_VERSION(9, 4, 2) ? 2101 48 : 2102 44; 2103 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 2104 if (r) { 2105 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 2106 return r; 2107 } 2108 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 2109 2110 r = gmc_v9_0_mc_init(adev); 2111 if (r) 2112 return r; 2113 2114 amdgpu_gmc_get_vbios_allocations(adev); 2115 2116 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 2117 r = gmc_v9_0_init_mem_ranges(adev); 2118 if (r) 2119 return r; 2120 } 2121 2122 /* Memory manager */ 2123 r = amdgpu_bo_init(adev); 2124 if (r) 2125 return r; 2126 2127 r = gmc_v9_0_gart_init(adev); 2128 if (r) 2129 return r; 2130 2131 /* 2132 * number of VMs 2133 * VMID 0 is reserved for System 2134 * amdgpu graphics/compute will use VMIDs 1..n-1 2135 * amdkfd will use VMIDs n..15 2136 * 2137 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2138 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2139 * for video processing. 2140 */ 2141 adev->vm_manager.first_kfd_vmid = 2142 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 2143 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 2144 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) ? 2145 3 : 2146 8; 2147 2148 amdgpu_vm_manager_init(adev); 2149 2150 gmc_v9_0_save_registers(adev); 2151 2152 r = amdgpu_gmc_ras_sw_init(adev); 2153 if (r) 2154 return r; 2155 2156 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 2157 amdgpu_gmc_sysfs_init(adev); 2158 2159 return 0; 2160 } 2161 2162 static int gmc_v9_0_sw_fini(void *handle) 2163 { 2164 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2165 2166 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 2167 amdgpu_gmc_sysfs_fini(adev); 2168 2169 amdgpu_gmc_ras_fini(adev); 2170 amdgpu_gem_force_release(adev); 2171 amdgpu_vm_manager_fini(adev); 2172 if (!adev->gmc.real_vram_size) { 2173 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2174 amdgpu_gart_table_ram_free(adev); 2175 } else { 2176 amdgpu_gart_table_vram_free(adev); 2177 } 2178 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2179 amdgpu_bo_fini(adev); 2180 2181 adev->gmc.num_mem_partitions = 0; 2182 kfree(adev->gmc.mem_partitions); 2183 2184 return 0; 2185 } 2186 2187 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2188 { 2189 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 2190 case IP_VERSION(9, 0, 0): 2191 if (amdgpu_sriov_vf(adev)) 2192 break; 2193 fallthrough; 2194 case IP_VERSION(9, 4, 0): 2195 soc15_program_register_sequence(adev, 2196 golden_settings_mmhub_1_0_0, 2197 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2198 soc15_program_register_sequence(adev, 2199 golden_settings_athub_1_0_0, 2200 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2201 break; 2202 case IP_VERSION(9, 1, 0): 2203 case IP_VERSION(9, 2, 0): 2204 /* TODO for renoir */ 2205 soc15_program_register_sequence(adev, 2206 golden_settings_athub_1_0_0, 2207 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2208 break; 2209 default: 2210 break; 2211 } 2212 } 2213 2214 /** 2215 * gmc_v9_0_restore_registers - restores regs 2216 * 2217 * @adev: amdgpu_device pointer 2218 * 2219 * This restores register values, saved at suspend. 2220 */ 2221 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2222 { 2223 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 2224 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) { 2225 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2226 WARN_ON(adev->gmc.sdpif_register != 2227 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2228 } 2229 } 2230 2231 /** 2232 * gmc_v9_0_gart_enable - gart enable 2233 * 2234 * @adev: amdgpu_device pointer 2235 */ 2236 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2237 { 2238 int r; 2239 2240 if (adev->gmc.xgmi.connected_to_cpu) 2241 amdgpu_gmc_init_pdb0(adev); 2242 2243 if (adev->gart.bo == NULL) { 2244 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2245 return -EINVAL; 2246 } 2247 2248 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2249 2250 if (!adev->in_s0ix) { 2251 r = adev->gfxhub.funcs->gart_enable(adev); 2252 if (r) 2253 return r; 2254 } 2255 2256 r = adev->mmhub.funcs->gart_enable(adev); 2257 if (r) 2258 return r; 2259 2260 DRM_INFO("PCIE GART of %uM enabled.\n", 2261 (unsigned int)(adev->gmc.gart_size >> 20)); 2262 if (adev->gmc.pdb0_bo) 2263 DRM_INFO("PDB0 located at 0x%016llX\n", 2264 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2265 DRM_INFO("PTB located at 0x%016llX\n", 2266 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2267 2268 return 0; 2269 } 2270 2271 static int gmc_v9_0_hw_init(void *handle) 2272 { 2273 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2274 bool value; 2275 int i, r; 2276 2277 adev->gmc.flush_pasid_uses_kiq = true; 2278 2279 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush 2280 * (type 2), which flushes both. Due to a race condition with 2281 * concurrent memory accesses using the same TLB cache line, we still 2282 * need a second TLB flush after this. 2283 */ 2284 adev->gmc.flush_tlb_needs_extra_type_2 = 2285 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) && 2286 adev->gmc.xgmi.num_physical_nodes; 2287 /* 2288 * TODO: This workaround is badly documented and had a buggy 2289 * implementation. We should probably verify what we do here. 2290 */ 2291 adev->gmc.flush_tlb_needs_extra_type_0 = 2292 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 2293 adev->rev_id == 0; 2294 2295 /* The sequence of these two function calls matters.*/ 2296 gmc_v9_0_init_golden_registers(adev); 2297 2298 if (adev->mode_info.num_crtc) { 2299 /* Lockout access through VGA aperture*/ 2300 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2301 /* disable VGA render */ 2302 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2303 } 2304 2305 if (adev->mmhub.funcs->update_power_gating) 2306 adev->mmhub.funcs->update_power_gating(adev, true); 2307 2308 adev->hdp.funcs->init_registers(adev); 2309 2310 /* After HDP is initialized, flush HDP.*/ 2311 adev->hdp.funcs->flush_hdp(adev, NULL); 2312 2313 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2314 value = false; 2315 else 2316 value = true; 2317 2318 if (!amdgpu_sriov_vf(adev)) { 2319 if (!adev->in_s0ix) 2320 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2321 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2322 } 2323 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2324 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2325 continue; 2326 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2327 } 2328 2329 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2330 adev->umc.funcs->init_registers(adev); 2331 2332 r = gmc_v9_0_gart_enable(adev); 2333 if (r) 2334 return r; 2335 2336 if (amdgpu_emu_mode == 1) 2337 return amdgpu_gmc_vram_checking(adev); 2338 2339 return 0; 2340 } 2341 2342 /** 2343 * gmc_v9_0_gart_disable - gart disable 2344 * 2345 * @adev: amdgpu_device pointer 2346 * 2347 * This disables all VM page table. 2348 */ 2349 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2350 { 2351 if (!adev->in_s0ix) 2352 adev->gfxhub.funcs->gart_disable(adev); 2353 adev->mmhub.funcs->gart_disable(adev); 2354 } 2355 2356 static int gmc_v9_0_hw_fini(void *handle) 2357 { 2358 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2359 2360 gmc_v9_0_gart_disable(adev); 2361 2362 if (amdgpu_sriov_vf(adev)) { 2363 /* full access mode, so don't touch any GMC register */ 2364 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2365 return 0; 2366 } 2367 2368 /* 2369 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2370 * a correct cached state for GMC. Otherwise, the "gate" again 2371 * operation on S3 resuming will fail due to wrong cached state. 2372 */ 2373 if (adev->mmhub.funcs->update_power_gating) 2374 adev->mmhub.funcs->update_power_gating(adev, false); 2375 2376 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2377 2378 if (adev->gmc.ecc_irq.funcs && 2379 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2380 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 2381 2382 return 0; 2383 } 2384 2385 static int gmc_v9_0_suspend(void *handle) 2386 { 2387 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2388 2389 return gmc_v9_0_hw_fini(adev); 2390 } 2391 2392 static int gmc_v9_0_resume(void *handle) 2393 { 2394 int r; 2395 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2396 2397 r = gmc_v9_0_hw_init(adev); 2398 if (r) 2399 return r; 2400 2401 amdgpu_vmid_reset_all(adev); 2402 2403 return 0; 2404 } 2405 2406 static bool gmc_v9_0_is_idle(void *handle) 2407 { 2408 /* MC is always ready in GMC v9.*/ 2409 return true; 2410 } 2411 2412 static int gmc_v9_0_wait_for_idle(void *handle) 2413 { 2414 /* There is no need to wait for MC idle in GMC v9.*/ 2415 return 0; 2416 } 2417 2418 static int gmc_v9_0_soft_reset(void *handle) 2419 { 2420 /* XXX for emulation.*/ 2421 return 0; 2422 } 2423 2424 static int gmc_v9_0_set_clockgating_state(void *handle, 2425 enum amd_clockgating_state state) 2426 { 2427 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2428 2429 adev->mmhub.funcs->set_clockgating(adev, state); 2430 2431 athub_v1_0_set_clockgating(adev, state); 2432 2433 return 0; 2434 } 2435 2436 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 2437 { 2438 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2439 2440 adev->mmhub.funcs->get_clockgating(adev, flags); 2441 2442 athub_v1_0_get_clockgating(adev, flags); 2443 } 2444 2445 static int gmc_v9_0_set_powergating_state(void *handle, 2446 enum amd_powergating_state state) 2447 { 2448 return 0; 2449 } 2450 2451 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2452 .name = "gmc_v9_0", 2453 .early_init = gmc_v9_0_early_init, 2454 .late_init = gmc_v9_0_late_init, 2455 .sw_init = gmc_v9_0_sw_init, 2456 .sw_fini = gmc_v9_0_sw_fini, 2457 .hw_init = gmc_v9_0_hw_init, 2458 .hw_fini = gmc_v9_0_hw_fini, 2459 .suspend = gmc_v9_0_suspend, 2460 .resume = gmc_v9_0_resume, 2461 .is_idle = gmc_v9_0_is_idle, 2462 .wait_for_idle = gmc_v9_0_wait_for_idle, 2463 .soft_reset = gmc_v9_0_soft_reset, 2464 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2465 .set_powergating_state = gmc_v9_0_set_powergating_state, 2466 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2467 }; 2468 2469 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = { 2470 .type = AMD_IP_BLOCK_TYPE_GMC, 2471 .major = 9, 2472 .minor = 0, 2473 .rev = 0, 2474 .funcs = &gmc_v9_0_ip_funcs, 2475 }; 2476