1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "hdp/hdp_4_0_offset.h" 35 #include "hdp/hdp_4_0_sh_mask.h" 36 #include "gc/gc_9_0_sh_mask.h" 37 #include "dce/dce_12_0_offset.h" 38 #include "dce/dce_12_0_sh_mask.h" 39 #include "vega10_enum.h" 40 #include "mmhub/mmhub_1_0_offset.h" 41 #include "athub/athub_1_0_offset.h" 42 #include "oss/osssys_4_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "mmhub_v9_4.h" 53 #include "umc_v6_1.h" 54 55 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 56 57 #include "amdgpu_ras.h" 58 59 /* add these here since we already include dce12 headers and these are for DCN */ 60 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 61 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 62 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 63 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 64 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 65 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 66 67 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ 68 #define AMDGPU_NUM_OF_VMIDS 8 69 70 static const u32 golden_settings_vega10_hdp[] = 71 { 72 0xf64, 0x0fffffff, 0x00000000, 73 0xf65, 0x0fffffff, 0x00000000, 74 0xf66, 0x0fffffff, 0x00000000, 75 0xf67, 0x0fffffff, 0x00000000, 76 0xf68, 0x0fffffff, 0x00000000, 77 0xf6a, 0x0fffffff, 0x00000000, 78 0xf6b, 0x0fffffff, 0x00000000, 79 0xf6c, 0x0fffffff, 0x00000000, 80 0xf6d, 0x0fffffff, 0x00000000, 81 0xf6e, 0x0fffffff, 0x00000000, 82 }; 83 84 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 85 { 86 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 87 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 88 }; 89 90 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 91 { 92 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 93 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 94 }; 95 96 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 97 (0x000143c0 + 0x00000000), 98 (0x000143c0 + 0x00000800), 99 (0x000143c0 + 0x00001000), 100 (0x000143c0 + 0x00001800), 101 (0x000543c0 + 0x00000000), 102 (0x000543c0 + 0x00000800), 103 (0x000543c0 + 0x00001000), 104 (0x000543c0 + 0x00001800), 105 (0x000943c0 + 0x00000000), 106 (0x000943c0 + 0x00000800), 107 (0x000943c0 + 0x00001000), 108 (0x000943c0 + 0x00001800), 109 (0x000d43c0 + 0x00000000), 110 (0x000d43c0 + 0x00000800), 111 (0x000d43c0 + 0x00001000), 112 (0x000d43c0 + 0x00001800), 113 (0x001143c0 + 0x00000000), 114 (0x001143c0 + 0x00000800), 115 (0x001143c0 + 0x00001000), 116 (0x001143c0 + 0x00001800), 117 (0x001543c0 + 0x00000000), 118 (0x001543c0 + 0x00000800), 119 (0x001543c0 + 0x00001000), 120 (0x001543c0 + 0x00001800), 121 (0x001943c0 + 0x00000000), 122 (0x001943c0 + 0x00000800), 123 (0x001943c0 + 0x00001000), 124 (0x001943c0 + 0x00001800), 125 (0x001d43c0 + 0x00000000), 126 (0x001d43c0 + 0x00000800), 127 (0x001d43c0 + 0x00001000), 128 (0x001d43c0 + 0x00001800), 129 }; 130 131 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 132 (0x000143e0 + 0x00000000), 133 (0x000143e0 + 0x00000800), 134 (0x000143e0 + 0x00001000), 135 (0x000143e0 + 0x00001800), 136 (0x000543e0 + 0x00000000), 137 (0x000543e0 + 0x00000800), 138 (0x000543e0 + 0x00001000), 139 (0x000543e0 + 0x00001800), 140 (0x000943e0 + 0x00000000), 141 (0x000943e0 + 0x00000800), 142 (0x000943e0 + 0x00001000), 143 (0x000943e0 + 0x00001800), 144 (0x000d43e0 + 0x00000000), 145 (0x000d43e0 + 0x00000800), 146 (0x000d43e0 + 0x00001000), 147 (0x000d43e0 + 0x00001800), 148 (0x001143e0 + 0x00000000), 149 (0x001143e0 + 0x00000800), 150 (0x001143e0 + 0x00001000), 151 (0x001143e0 + 0x00001800), 152 (0x001543e0 + 0x00000000), 153 (0x001543e0 + 0x00000800), 154 (0x001543e0 + 0x00001000), 155 (0x001543e0 + 0x00001800), 156 (0x001943e0 + 0x00000000), 157 (0x001943e0 + 0x00000800), 158 (0x001943e0 + 0x00001000), 159 (0x001943e0 + 0x00001800), 160 (0x001d43e0 + 0x00000000), 161 (0x001d43e0 + 0x00000800), 162 (0x001d43e0 + 0x00001000), 163 (0x001d43e0 + 0x00001800), 164 }; 165 166 static const uint32_t ecc_umc_mcumc_status_addrs[] = { 167 (0x000143c2 + 0x00000000), 168 (0x000143c2 + 0x00000800), 169 (0x000143c2 + 0x00001000), 170 (0x000143c2 + 0x00001800), 171 (0x000543c2 + 0x00000000), 172 (0x000543c2 + 0x00000800), 173 (0x000543c2 + 0x00001000), 174 (0x000543c2 + 0x00001800), 175 (0x000943c2 + 0x00000000), 176 (0x000943c2 + 0x00000800), 177 (0x000943c2 + 0x00001000), 178 (0x000943c2 + 0x00001800), 179 (0x000d43c2 + 0x00000000), 180 (0x000d43c2 + 0x00000800), 181 (0x000d43c2 + 0x00001000), 182 (0x000d43c2 + 0x00001800), 183 (0x001143c2 + 0x00000000), 184 (0x001143c2 + 0x00000800), 185 (0x001143c2 + 0x00001000), 186 (0x001143c2 + 0x00001800), 187 (0x001543c2 + 0x00000000), 188 (0x001543c2 + 0x00000800), 189 (0x001543c2 + 0x00001000), 190 (0x001543c2 + 0x00001800), 191 (0x001943c2 + 0x00000000), 192 (0x001943c2 + 0x00000800), 193 (0x001943c2 + 0x00001000), 194 (0x001943c2 + 0x00001800), 195 (0x001d43c2 + 0x00000000), 196 (0x001d43c2 + 0x00000800), 197 (0x001d43c2 + 0x00001000), 198 (0x001d43c2 + 0x00001800), 199 }; 200 201 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 202 struct amdgpu_irq_src *src, 203 unsigned type, 204 enum amdgpu_interrupt_state state) 205 { 206 u32 bits, i, tmp, reg; 207 208 bits = 0x7f; 209 210 switch (state) { 211 case AMDGPU_IRQ_STATE_DISABLE: 212 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 213 reg = ecc_umc_mcumc_ctrl_addrs[i]; 214 tmp = RREG32(reg); 215 tmp &= ~bits; 216 WREG32(reg, tmp); 217 } 218 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 219 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 220 tmp = RREG32(reg); 221 tmp &= ~bits; 222 WREG32(reg, tmp); 223 } 224 break; 225 case AMDGPU_IRQ_STATE_ENABLE: 226 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 227 reg = ecc_umc_mcumc_ctrl_addrs[i]; 228 tmp = RREG32(reg); 229 tmp |= bits; 230 WREG32(reg, tmp); 231 } 232 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 233 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 234 tmp = RREG32(reg); 235 tmp |= bits; 236 WREG32(reg, tmp); 237 } 238 break; 239 default: 240 break; 241 } 242 243 return 0; 244 } 245 246 static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev, 247 struct ras_err_data *err_data, 248 struct amdgpu_iv_entry *entry) 249 { 250 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 251 if (adev->umc.funcs->query_ras_error_count) 252 adev->umc.funcs->query_ras_error_count(adev, err_data); 253 /* umc query_ras_error_address is also responsible for clearing 254 * error status 255 */ 256 if (adev->umc.funcs->query_ras_error_address) 257 adev->umc.funcs->query_ras_error_address(adev, err_data); 258 259 /* only uncorrectable error needs gpu reset */ 260 if (err_data->ue_count) 261 amdgpu_ras_reset_gpu(adev, 0); 262 263 return AMDGPU_RAS_SUCCESS; 264 } 265 266 static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev, 267 struct amdgpu_irq_src *source, 268 struct amdgpu_iv_entry *entry) 269 { 270 struct ras_common_if *ras_if = adev->gmc.umc_ras_if; 271 struct ras_dispatch_if ih_data = { 272 .entry = entry, 273 }; 274 275 if (!ras_if) 276 return 0; 277 278 ih_data.head = *ras_if; 279 280 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 281 return 0; 282 } 283 284 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 285 struct amdgpu_irq_src *src, 286 unsigned type, 287 enum amdgpu_interrupt_state state) 288 { 289 struct amdgpu_vmhub *hub; 290 u32 tmp, reg, bits, i, j; 291 292 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 293 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 294 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 295 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 296 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 297 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 298 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 299 300 switch (state) { 301 case AMDGPU_IRQ_STATE_DISABLE: 302 for (j = 0; j < adev->num_vmhubs; j++) { 303 hub = &adev->vmhub[j]; 304 for (i = 0; i < 16; i++) { 305 reg = hub->vm_context0_cntl + i; 306 tmp = RREG32(reg); 307 tmp &= ~bits; 308 WREG32(reg, tmp); 309 } 310 } 311 break; 312 case AMDGPU_IRQ_STATE_ENABLE: 313 for (j = 0; j < adev->num_vmhubs; j++) { 314 hub = &adev->vmhub[j]; 315 for (i = 0; i < 16; i++) { 316 reg = hub->vm_context0_cntl + i; 317 tmp = RREG32(reg); 318 tmp |= bits; 319 WREG32(reg, tmp); 320 } 321 } 322 default: 323 break; 324 } 325 326 return 0; 327 } 328 329 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 330 struct amdgpu_irq_src *source, 331 struct amdgpu_iv_entry *entry) 332 { 333 struct amdgpu_vmhub *hub; 334 bool retry_fault = !!(entry->src_data[1] & 0x80); 335 uint32_t status = 0; 336 u64 addr; 337 char hub_name[10]; 338 339 addr = (u64)entry->src_data[0] << 12; 340 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 341 342 if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid, 343 entry->timestamp)) 344 return 1; /* This also prevents sending it to KFD */ 345 346 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 347 snprintf(hub_name, sizeof(hub_name), "mmhub0"); 348 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 349 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 350 snprintf(hub_name, sizeof(hub_name), "mmhub1"); 351 hub = &adev->vmhub[AMDGPU_MMHUB_1]; 352 } else { 353 snprintf(hub_name, sizeof(hub_name), "gfxhub0"); 354 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 355 } 356 357 /* If it's the first fault for this address, process it normally */ 358 if (!amdgpu_sriov_vf(adev)) { 359 status = RREG32(hub->vm_l2_pro_fault_status); 360 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 361 } 362 363 if (printk_ratelimit()) { 364 struct amdgpu_task_info task_info; 365 366 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 367 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 368 369 dev_err(adev->dev, 370 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 371 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 372 hub_name, retry_fault ? "retry" : "no-retry", 373 entry->src_id, entry->ring_id, entry->vmid, 374 entry->pasid, task_info.process_name, task_info.tgid, 375 task_info.task_name, task_info.pid); 376 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 377 addr, entry->client_id); 378 if (!amdgpu_sriov_vf(adev)) { 379 dev_err(adev->dev, 380 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 381 status); 382 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 383 REG_GET_FIELD(status, 384 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 385 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 386 REG_GET_FIELD(status, 387 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 388 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 389 REG_GET_FIELD(status, 390 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 391 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 392 REG_GET_FIELD(status, 393 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 394 395 } 396 } 397 398 return 0; 399 } 400 401 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 402 .set = gmc_v9_0_vm_fault_interrupt_state, 403 .process = gmc_v9_0_process_interrupt, 404 }; 405 406 407 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 408 .set = gmc_v9_0_ecc_interrupt_state, 409 .process = gmc_v9_0_process_ecc_irq, 410 }; 411 412 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 413 { 414 adev->gmc.vm_fault.num_types = 1; 415 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 416 417 adev->gmc.ecc_irq.num_types = 1; 418 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 419 } 420 421 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 422 uint32_t flush_type) 423 { 424 u32 req = 0; 425 426 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 427 PER_VMID_INVALIDATE_REQ, 1 << vmid); 428 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 429 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 430 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 431 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 432 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 433 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 434 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 435 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 436 437 return req; 438 } 439 440 /* 441 * GART 442 * VMID 0 is the physical GPU addresses as used by the kernel. 443 * VMIDs 1-15 are used for userspace clients and are handled 444 * by the amdgpu vm/hsa code. 445 */ 446 447 /** 448 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 449 * 450 * @adev: amdgpu_device pointer 451 * @vmid: vm instance to flush 452 * @flush_type: the flush type 453 * 454 * Flush the TLB for the requested page table using certain type. 455 */ 456 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, 457 uint32_t vmid, uint32_t flush_type) 458 { 459 const unsigned eng = 17; 460 unsigned i, j; 461 462 for (i = 0; i < adev->num_vmhubs; ++i) { 463 struct amdgpu_vmhub *hub = &adev->vmhub[i]; 464 u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); 465 466 /* This is necessary for a HW workaround under SRIOV as well 467 * as GFXOFF under bare metal 468 */ 469 if (adev->gfx.kiq.ring.sched.ready && 470 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 471 !adev->in_gpu_reset) { 472 uint32_t req = hub->vm_inv_eng0_req + eng; 473 uint32_t ack = hub->vm_inv_eng0_ack + eng; 474 475 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp, 476 1 << vmid); 477 continue; 478 } 479 480 spin_lock(&adev->gmc.invalidate_lock); 481 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); 482 for (j = 0; j < adev->usec_timeout; j++) { 483 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 484 if (tmp & (1 << vmid)) 485 break; 486 udelay(1); 487 } 488 spin_unlock(&adev->gmc.invalidate_lock); 489 if (j < adev->usec_timeout) 490 continue; 491 492 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 493 } 494 } 495 496 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 497 unsigned vmid, uint64_t pd_addr) 498 { 499 struct amdgpu_device *adev = ring->adev; 500 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 501 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 502 unsigned eng = ring->vm_inv_eng; 503 504 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), 505 lower_32_bits(pd_addr)); 506 507 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 508 upper_32_bits(pd_addr)); 509 510 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, 511 hub->vm_inv_eng0_ack + eng, 512 req, 1 << vmid); 513 514 return pd_addr; 515 } 516 517 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 518 unsigned pasid) 519 { 520 struct amdgpu_device *adev = ring->adev; 521 uint32_t reg; 522 523 /* Do nothing because there's no lut register for mmhub1. */ 524 if (ring->funcs->vmhub == AMDGPU_MMHUB_1) 525 return; 526 527 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 528 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 529 else 530 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 531 532 amdgpu_ring_emit_wreg(ring, reg, pasid); 533 } 534 535 /* 536 * PTE format on VEGA 10: 537 * 63:59 reserved 538 * 58:57 mtype 539 * 56 F 540 * 55 L 541 * 54 P 542 * 53 SW 543 * 52 T 544 * 50:48 reserved 545 * 47:12 4k physical page base address 546 * 11:7 fragment 547 * 6 write 548 * 5 read 549 * 4 exe 550 * 3 Z 551 * 2 snooped 552 * 1 system 553 * 0 valid 554 * 555 * PDE format on VEGA 10: 556 * 63:59 block fragment size 557 * 58:55 reserved 558 * 54 P 559 * 53:48 reserved 560 * 47:6 physical base address of PD or PTE 561 * 5:3 reserved 562 * 2 C 563 * 1 system 564 * 0 valid 565 */ 566 567 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, 568 uint32_t flags) 569 570 { 571 uint64_t pte_flag = 0; 572 573 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 574 pte_flag |= AMDGPU_PTE_EXECUTABLE; 575 if (flags & AMDGPU_VM_PAGE_READABLE) 576 pte_flag |= AMDGPU_PTE_READABLE; 577 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 578 pte_flag |= AMDGPU_PTE_WRITEABLE; 579 580 switch (flags & AMDGPU_VM_MTYPE_MASK) { 581 case AMDGPU_VM_MTYPE_DEFAULT: 582 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 583 break; 584 case AMDGPU_VM_MTYPE_NC: 585 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 586 break; 587 case AMDGPU_VM_MTYPE_WC: 588 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 589 break; 590 case AMDGPU_VM_MTYPE_CC: 591 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 592 break; 593 case AMDGPU_VM_MTYPE_UC: 594 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 595 break; 596 default: 597 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 598 break; 599 } 600 601 if (flags & AMDGPU_VM_PAGE_PRT) 602 pte_flag |= AMDGPU_PTE_PRT; 603 604 return pte_flag; 605 } 606 607 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 608 uint64_t *addr, uint64_t *flags) 609 { 610 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 611 *addr = adev->vm_manager.vram_base_offset + *addr - 612 adev->gmc.vram_start; 613 BUG_ON(*addr & 0xFFFF00000000003FULL); 614 615 if (!adev->gmc.translate_further) 616 return; 617 618 if (level == AMDGPU_VM_PDB1) { 619 /* Set the block fragment size */ 620 if (!(*flags & AMDGPU_PDE_PTE)) 621 *flags |= AMDGPU_PDE_BFS(0x9); 622 623 } else if (level == AMDGPU_VM_PDB0) { 624 if (*flags & AMDGPU_PDE_PTE) 625 *flags &= ~AMDGPU_PDE_PTE; 626 else 627 *flags |= AMDGPU_PTE_TF; 628 } 629 } 630 631 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 632 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 633 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 634 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 635 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags, 636 .get_vm_pde = gmc_v9_0_get_vm_pde 637 }; 638 639 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 640 { 641 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 642 } 643 644 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 645 { 646 switch (adev->asic_type) { 647 case CHIP_VEGA20: 648 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 649 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 650 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 651 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET; 652 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 653 adev->umc.funcs = &umc_v6_1_funcs; 654 break; 655 default: 656 break; 657 } 658 } 659 660 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 661 { 662 switch (adev->asic_type) { 663 case CHIP_VEGA20: 664 adev->mmhub_funcs = &mmhub_v1_0_funcs; 665 break; 666 default: 667 break; 668 } 669 } 670 671 static int gmc_v9_0_early_init(void *handle) 672 { 673 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 674 675 gmc_v9_0_set_gmc_funcs(adev); 676 gmc_v9_0_set_irq_funcs(adev); 677 gmc_v9_0_set_umc_funcs(adev); 678 gmc_v9_0_set_mmhub_funcs(adev); 679 680 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 681 adev->gmc.shared_aperture_end = 682 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 683 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 684 adev->gmc.private_aperture_end = 685 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 686 687 return 0; 688 } 689 690 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev) 691 { 692 693 /* 694 * TODO: 695 * Currently there is a bug where some memory client outside 696 * of the driver writes to first 8M of VRAM on S3 resume, 697 * this overrides GART which by default gets placed in first 8M and 698 * causes VM_FAULTS once GTT is accessed. 699 * Keep the stolen memory reservation until the while this is not solved. 700 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init 701 */ 702 switch (adev->asic_type) { 703 case CHIP_VEGA10: 704 case CHIP_RAVEN: 705 case CHIP_ARCTURUS: 706 return true; 707 case CHIP_VEGA12: 708 case CHIP_VEGA20: 709 default: 710 return false; 711 } 712 } 713 714 static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev) 715 { 716 struct amdgpu_ring *ring; 717 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = 718 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP, 719 GFXHUB_FREE_VM_INV_ENGS_BITMAP}; 720 unsigned i; 721 unsigned vmhub, inv_eng; 722 723 for (i = 0; i < adev->num_rings; ++i) { 724 ring = adev->rings[i]; 725 vmhub = ring->funcs->vmhub; 726 727 inv_eng = ffs(vm_inv_engs[vmhub]); 728 if (!inv_eng) { 729 dev_err(adev->dev, "no VM inv eng for ring %s\n", 730 ring->name); 731 return -EINVAL; 732 } 733 734 ring->vm_inv_eng = inv_eng - 1; 735 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 736 737 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 738 ring->name, ring->vm_inv_eng, ring->funcs->vmhub); 739 } 740 741 return 0; 742 } 743 744 static int gmc_v9_0_ecc_ras_block_late_init(void *handle, 745 struct ras_fs_if *fs_info, struct ras_common_if *ras_block) 746 { 747 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 748 struct ras_common_if **ras_if = NULL; 749 struct ras_ih_if ih_info = { 750 .cb = gmc_v9_0_process_ras_data_cb, 751 }; 752 int r; 753 754 if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) 755 ras_if = &adev->gmc.umc_ras_if; 756 else if (ras_block->block == AMDGPU_RAS_BLOCK__MMHUB) 757 ras_if = &adev->gmc.mmhub_ras_if; 758 else 759 BUG(); 760 761 if (!amdgpu_ras_is_supported(adev, ras_block->block)) { 762 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); 763 return 0; 764 } 765 766 /* handle resume path. */ 767 if (*ras_if) { 768 /* resend ras TA enable cmd during resume. 769 * prepare to handle failure. 770 */ 771 ih_info.head = **ras_if; 772 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 773 if (r) { 774 if (r == -EAGAIN) { 775 /* request a gpu reset. will run again. */ 776 amdgpu_ras_request_reset_on_boot(adev, 777 ras_block->block); 778 return 0; 779 } 780 /* fail to enable ras, cleanup all. */ 781 goto irq; 782 } 783 /* enable successfully. continue. */ 784 goto resume; 785 } 786 787 *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL); 788 if (!*ras_if) 789 return -ENOMEM; 790 791 **ras_if = *ras_block; 792 793 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 794 if (r) { 795 if (r == -EAGAIN) { 796 amdgpu_ras_request_reset_on_boot(adev, 797 ras_block->block); 798 r = 0; 799 } 800 goto feature; 801 } 802 803 ih_info.head = **ras_if; 804 fs_info->head = **ras_if; 805 806 if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) { 807 r = amdgpu_ras_interrupt_add_handler(adev, &ih_info); 808 if (r) 809 goto interrupt; 810 } 811 812 amdgpu_ras_debugfs_create(adev, fs_info); 813 814 r = amdgpu_ras_sysfs_create(adev, fs_info); 815 if (r) 816 goto sysfs; 817 resume: 818 if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) { 819 r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); 820 if (r) 821 goto irq; 822 } 823 824 return 0; 825 irq: 826 amdgpu_ras_sysfs_remove(adev, *ras_if); 827 sysfs: 828 amdgpu_ras_debugfs_remove(adev, *ras_if); 829 if (ras_block->block == AMDGPU_RAS_BLOCK__UMC) 830 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 831 interrupt: 832 amdgpu_ras_feature_enable(adev, *ras_if, 0); 833 feature: 834 kfree(*ras_if); 835 *ras_if = NULL; 836 return r; 837 } 838 839 static int gmc_v9_0_ecc_late_init(void *handle) 840 { 841 int r; 842 843 struct ras_fs_if umc_fs_info = { 844 .sysfs_name = "umc_err_count", 845 .debugfs_name = "umc_err_inject", 846 }; 847 struct ras_common_if umc_ras_block = { 848 .block = AMDGPU_RAS_BLOCK__UMC, 849 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 850 .sub_block_index = 0, 851 .name = "umc", 852 }; 853 struct ras_fs_if mmhub_fs_info = { 854 .sysfs_name = "mmhub_err_count", 855 .debugfs_name = "mmhub_err_inject", 856 }; 857 struct ras_common_if mmhub_ras_block = { 858 .block = AMDGPU_RAS_BLOCK__MMHUB, 859 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 860 .sub_block_index = 0, 861 .name = "mmhub", 862 }; 863 864 r = gmc_v9_0_ecc_ras_block_late_init(handle, 865 &umc_fs_info, &umc_ras_block); 866 if (r) 867 return r; 868 869 r = gmc_v9_0_ecc_ras_block_late_init(handle, 870 &mmhub_fs_info, &mmhub_ras_block); 871 return r; 872 } 873 874 static int gmc_v9_0_late_init(void *handle) 875 { 876 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 877 bool r; 878 879 if (!gmc_v9_0_keep_stolen_memory(adev)) 880 amdgpu_bo_late_init(adev); 881 882 r = gmc_v9_0_allocate_vm_inv_eng(adev); 883 if (r) 884 return r; 885 /* Check if ecc is available */ 886 if (!amdgpu_sriov_vf(adev)) { 887 switch (adev->asic_type) { 888 case CHIP_VEGA10: 889 case CHIP_VEGA20: 890 r = amdgpu_atomfirmware_mem_ecc_supported(adev); 891 if (!r) { 892 DRM_INFO("ECC is not present.\n"); 893 if (adev->df_funcs->enable_ecc_force_par_wr_rmw) 894 adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false); 895 } else { 896 DRM_INFO("ECC is active.\n"); 897 } 898 899 r = amdgpu_atomfirmware_sram_ecc_supported(adev); 900 if (!r) { 901 DRM_INFO("SRAM ECC is not present.\n"); 902 } else { 903 DRM_INFO("SRAM ECC is active.\n"); 904 } 905 break; 906 default: 907 break; 908 } 909 } 910 911 r = gmc_v9_0_ecc_late_init(handle); 912 if (r) 913 return r; 914 915 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 916 } 917 918 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 919 struct amdgpu_gmc *mc) 920 { 921 u64 base = 0; 922 if (!amdgpu_sriov_vf(adev)) { 923 if (adev->asic_type == CHIP_ARCTURUS) 924 base = mmhub_v9_4_get_fb_location(adev); 925 else 926 base = mmhub_v1_0_get_fb_location(adev); 927 } 928 /* add the xgmi offset of the physical node */ 929 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 930 amdgpu_gmc_vram_location(adev, mc, base); 931 amdgpu_gmc_gart_location(adev, mc); 932 if (!amdgpu_sriov_vf(adev)) 933 amdgpu_gmc_agp_location(adev, mc); 934 /* base offset of vram pages */ 935 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); 936 937 /* XXX: add the xgmi offset of the physical node? */ 938 adev->vm_manager.vram_base_offset += 939 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 940 } 941 942 /** 943 * gmc_v9_0_mc_init - initialize the memory controller driver params 944 * 945 * @adev: amdgpu_device pointer 946 * 947 * Look up the amount of vram, vram width, and decide how to place 948 * vram and gart within the GPU's physical address space. 949 * Returns 0 for success. 950 */ 951 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 952 { 953 int chansize, numchan; 954 int r; 955 956 if (amdgpu_sriov_vf(adev)) { 957 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 958 * and DF related registers is not readable, seems hardcord is the 959 * only way to set the correct vram_width 960 */ 961 adev->gmc.vram_width = 2048; 962 } else if (amdgpu_emu_mode != 1) { 963 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); 964 } 965 966 if (!adev->gmc.vram_width) { 967 /* hbm memory channel size */ 968 if (adev->flags & AMD_IS_APU) 969 chansize = 64; 970 else 971 chansize = 128; 972 973 numchan = adev->df_funcs->get_hbm_channel_number(adev); 974 adev->gmc.vram_width = numchan * chansize; 975 } 976 977 /* size in MB on si */ 978 adev->gmc.mc_vram_size = 979 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; 980 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 981 982 if (!(adev->flags & AMD_IS_APU)) { 983 r = amdgpu_device_resize_fb_bar(adev); 984 if (r) 985 return r; 986 } 987 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 988 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 989 990 #ifdef CONFIG_X86_64 991 if (adev->flags & AMD_IS_APU) { 992 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); 993 adev->gmc.aper_size = adev->gmc.real_vram_size; 994 } 995 #endif 996 /* In case the PCI BAR is larger than the actual amount of vram */ 997 adev->gmc.visible_vram_size = adev->gmc.aper_size; 998 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 999 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 1000 1001 /* set the gart size */ 1002 if (amdgpu_gart_size == -1) { 1003 switch (adev->asic_type) { 1004 case CHIP_VEGA10: /* all engines support GPUVM */ 1005 case CHIP_VEGA12: /* all engines support GPUVM */ 1006 case CHIP_VEGA20: 1007 case CHIP_ARCTURUS: 1008 default: 1009 adev->gmc.gart_size = 512ULL << 20; 1010 break; 1011 case CHIP_RAVEN: /* DCE SG support */ 1012 adev->gmc.gart_size = 1024ULL << 20; 1013 break; 1014 } 1015 } else { 1016 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1017 } 1018 1019 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1020 1021 return 0; 1022 } 1023 1024 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1025 { 1026 int r; 1027 1028 if (adev->gart.bo) { 1029 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1030 return 0; 1031 } 1032 /* Initialize common gart structure */ 1033 r = amdgpu_gart_init(adev); 1034 if (r) 1035 return r; 1036 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1037 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1038 AMDGPU_PTE_EXECUTABLE; 1039 return amdgpu_gart_table_vram_alloc(adev); 1040 } 1041 1042 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1043 { 1044 u32 d1vga_control; 1045 unsigned size; 1046 1047 /* 1048 * TODO Remove once GART corruption is resolved 1049 * Check related code in gmc_v9_0_sw_fini 1050 * */ 1051 if (gmc_v9_0_keep_stolen_memory(adev)) 1052 return 9 * 1024 * 1024; 1053 1054 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1055 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1056 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 1057 } else { 1058 u32 viewport; 1059 1060 switch (adev->asic_type) { 1061 case CHIP_RAVEN: 1062 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1063 size = (REG_GET_FIELD(viewport, 1064 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1065 REG_GET_FIELD(viewport, 1066 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1067 4); 1068 break; 1069 case CHIP_VEGA10: 1070 case CHIP_VEGA12: 1071 case CHIP_VEGA20: 1072 default: 1073 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1074 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1075 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1076 4); 1077 break; 1078 } 1079 } 1080 /* return 0 if the pre-OS buffer uses up most of vram */ 1081 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 1082 return 0; 1083 1084 return size; 1085 } 1086 1087 static int gmc_v9_0_sw_init(void *handle) 1088 { 1089 int r; 1090 int dma_bits; 1091 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1092 1093 gfxhub_v1_0_init(adev); 1094 if (adev->asic_type == CHIP_ARCTURUS) 1095 mmhub_v9_4_init(adev); 1096 else 1097 mmhub_v1_0_init(adev); 1098 1099 spin_lock_init(&adev->gmc.invalidate_lock); 1100 1101 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); 1102 switch (adev->asic_type) { 1103 case CHIP_RAVEN: 1104 adev->num_vmhubs = 2; 1105 1106 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1107 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1108 } else { 1109 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1110 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1111 adev->gmc.translate_further = 1112 adev->vm_manager.num_level > 1; 1113 } 1114 break; 1115 case CHIP_VEGA10: 1116 case CHIP_VEGA12: 1117 case CHIP_VEGA20: 1118 adev->num_vmhubs = 2; 1119 1120 /* 1121 * To fulfill 4-level page support, 1122 * vm size is 256TB (48bit), maximum size of Vega10, 1123 * block size 512 (9bit) 1124 */ 1125 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 1126 if (amdgpu_sriov_vf(adev)) 1127 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 1128 else 1129 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1130 break; 1131 case CHIP_ARCTURUS: 1132 adev->num_vmhubs = 3; 1133 1134 /* Keep the vm size same with Vega20 */ 1135 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1136 break; 1137 default: 1138 break; 1139 } 1140 1141 /* This interrupt is VMC page fault.*/ 1142 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1143 &adev->gmc.vm_fault); 1144 if (r) 1145 return r; 1146 1147 if (adev->asic_type == CHIP_ARCTURUS) { 1148 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1149 &adev->gmc.vm_fault); 1150 if (r) 1151 return r; 1152 } 1153 1154 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1155 &adev->gmc.vm_fault); 1156 1157 if (r) 1158 return r; 1159 1160 /* interrupt sent to DF. */ 1161 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1162 &adev->gmc.ecc_irq); 1163 if (r) 1164 return r; 1165 1166 /* Set the internal MC address mask 1167 * This is the max address of the GPU's 1168 * internal address space. 1169 */ 1170 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1171 1172 /* set DMA mask + need_dma32 flags. 1173 * PCIE - can handle 44-bits. 1174 * IGP - can handle 44-bits 1175 * PCI - dma32 for legacy pci gart, 44 bits on vega10 1176 */ 1177 adev->need_dma32 = false; 1178 dma_bits = adev->need_dma32 ? 32 : 44; 1179 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1180 if (r) { 1181 adev->need_dma32 = true; 1182 dma_bits = 32; 1183 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 1184 } 1185 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1186 if (r) { 1187 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 1188 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); 1189 } 1190 adev->need_swiotlb = drm_need_swiotlb(dma_bits); 1191 1192 if (adev->gmc.xgmi.supported) { 1193 r = gfxhub_v1_1_get_xgmi_info(adev); 1194 if (r) 1195 return r; 1196 } 1197 1198 r = gmc_v9_0_mc_init(adev); 1199 if (r) 1200 return r; 1201 1202 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev); 1203 1204 /* Memory manager */ 1205 r = amdgpu_bo_init(adev); 1206 if (r) 1207 return r; 1208 1209 r = gmc_v9_0_gart_init(adev); 1210 if (r) 1211 return r; 1212 1213 /* 1214 * number of VMs 1215 * VMID 0 is reserved for System 1216 * amdgpu graphics/compute will use VMIDs 1-7 1217 * amdkfd will use VMIDs 8-15 1218 */ 1219 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 1220 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 1221 adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS; 1222 1223 amdgpu_vm_manager_init(adev); 1224 1225 return 0; 1226 } 1227 1228 static int gmc_v9_0_sw_fini(void *handle) 1229 { 1230 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1231 1232 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) && 1233 adev->gmc.umc_ras_if) { 1234 struct ras_common_if *ras_if = adev->gmc.umc_ras_if; 1235 struct ras_ih_if ih_info = { 1236 .head = *ras_if, 1237 }; 1238 1239 /* remove fs first */ 1240 amdgpu_ras_debugfs_remove(adev, ras_if); 1241 amdgpu_ras_sysfs_remove(adev, ras_if); 1242 /* remove the IH */ 1243 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 1244 amdgpu_ras_feature_enable(adev, ras_if, 0); 1245 kfree(ras_if); 1246 } 1247 1248 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) && 1249 adev->gmc.mmhub_ras_if) { 1250 struct ras_common_if *ras_if = adev->gmc.mmhub_ras_if; 1251 1252 /* remove fs and disable ras feature */ 1253 amdgpu_ras_debugfs_remove(adev, ras_if); 1254 amdgpu_ras_sysfs_remove(adev, ras_if); 1255 amdgpu_ras_feature_enable(adev, ras_if, 0); 1256 kfree(ras_if); 1257 } 1258 1259 amdgpu_gem_force_release(adev); 1260 amdgpu_vm_manager_fini(adev); 1261 1262 if (gmc_v9_0_keep_stolen_memory(adev)) 1263 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL); 1264 1265 amdgpu_gart_table_vram_free(adev); 1266 amdgpu_bo_fini(adev); 1267 amdgpu_gart_fini(adev); 1268 1269 return 0; 1270 } 1271 1272 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 1273 { 1274 1275 switch (adev->asic_type) { 1276 case CHIP_VEGA10: 1277 if (amdgpu_sriov_vf(adev)) 1278 break; 1279 /* fall through */ 1280 case CHIP_VEGA20: 1281 soc15_program_register_sequence(adev, 1282 golden_settings_mmhub_1_0_0, 1283 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 1284 soc15_program_register_sequence(adev, 1285 golden_settings_athub_1_0_0, 1286 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1287 break; 1288 case CHIP_VEGA12: 1289 break; 1290 case CHIP_RAVEN: 1291 soc15_program_register_sequence(adev, 1292 golden_settings_athub_1_0_0, 1293 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1294 break; 1295 default: 1296 break; 1297 } 1298 } 1299 1300 /** 1301 * gmc_v9_0_gart_enable - gart enable 1302 * 1303 * @adev: amdgpu_device pointer 1304 */ 1305 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1306 { 1307 int r; 1308 bool value; 1309 u32 tmp; 1310 1311 amdgpu_device_program_register_sequence(adev, 1312 golden_settings_vega10_hdp, 1313 ARRAY_SIZE(golden_settings_vega10_hdp)); 1314 1315 if (adev->gart.bo == NULL) { 1316 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1317 return -EINVAL; 1318 } 1319 r = amdgpu_gart_table_vram_pin(adev); 1320 if (r) 1321 return r; 1322 1323 switch (adev->asic_type) { 1324 case CHIP_RAVEN: 1325 mmhub_v1_0_update_power_gating(adev, true); 1326 break; 1327 default: 1328 break; 1329 } 1330 1331 r = gfxhub_v1_0_gart_enable(adev); 1332 if (r) 1333 return r; 1334 1335 if (adev->asic_type == CHIP_ARCTURUS) 1336 r = mmhub_v9_4_gart_enable(adev); 1337 else 1338 r = mmhub_v1_0_gart_enable(adev); 1339 if (r) 1340 return r; 1341 1342 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); 1343 1344 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 1345 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 1346 1347 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 1348 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); 1349 1350 /* After HDP is initialized, flush HDP.*/ 1351 adev->nbio_funcs->hdp_flush(adev, NULL); 1352 1353 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1354 value = false; 1355 else 1356 value = true; 1357 1358 gfxhub_v1_0_set_fault_enable_default(adev, value); 1359 if (adev->asic_type == CHIP_ARCTURUS) 1360 mmhub_v9_4_set_fault_enable_default(adev, value); 1361 else 1362 mmhub_v1_0_set_fault_enable_default(adev, value); 1363 gmc_v9_0_flush_gpu_tlb(adev, 0, 0); 1364 1365 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1366 (unsigned)(adev->gmc.gart_size >> 20), 1367 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1368 adev->gart.ready = true; 1369 return 0; 1370 } 1371 1372 static int gmc_v9_0_hw_init(void *handle) 1373 { 1374 int r; 1375 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1376 1377 /* The sequence of these two function calls matters.*/ 1378 gmc_v9_0_init_golden_registers(adev); 1379 1380 if (adev->mode_info.num_crtc) { 1381 /* Lockout access through VGA aperture*/ 1382 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1383 1384 /* disable VGA render */ 1385 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1386 } 1387 1388 r = gmc_v9_0_gart_enable(adev); 1389 1390 return r; 1391 } 1392 1393 /** 1394 * gmc_v9_0_gart_disable - gart disable 1395 * 1396 * @adev: amdgpu_device pointer 1397 * 1398 * This disables all VM page table. 1399 */ 1400 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1401 { 1402 gfxhub_v1_0_gart_disable(adev); 1403 if (adev->asic_type == CHIP_ARCTURUS) 1404 mmhub_v9_4_gart_disable(adev); 1405 else 1406 mmhub_v1_0_gart_disable(adev); 1407 amdgpu_gart_table_vram_unpin(adev); 1408 } 1409 1410 static int gmc_v9_0_hw_fini(void *handle) 1411 { 1412 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1413 1414 if (amdgpu_sriov_vf(adev)) { 1415 /* full access mode, so don't touch any GMC register */ 1416 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1417 return 0; 1418 } 1419 1420 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1421 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1422 gmc_v9_0_gart_disable(adev); 1423 1424 return 0; 1425 } 1426 1427 static int gmc_v9_0_suspend(void *handle) 1428 { 1429 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1430 1431 return gmc_v9_0_hw_fini(adev); 1432 } 1433 1434 static int gmc_v9_0_resume(void *handle) 1435 { 1436 int r; 1437 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1438 1439 r = gmc_v9_0_hw_init(adev); 1440 if (r) 1441 return r; 1442 1443 amdgpu_vmid_reset_all(adev); 1444 1445 return 0; 1446 } 1447 1448 static bool gmc_v9_0_is_idle(void *handle) 1449 { 1450 /* MC is always ready in GMC v9.*/ 1451 return true; 1452 } 1453 1454 static int gmc_v9_0_wait_for_idle(void *handle) 1455 { 1456 /* There is no need to wait for MC idle in GMC v9.*/ 1457 return 0; 1458 } 1459 1460 static int gmc_v9_0_soft_reset(void *handle) 1461 { 1462 /* XXX for emulation.*/ 1463 return 0; 1464 } 1465 1466 static int gmc_v9_0_set_clockgating_state(void *handle, 1467 enum amd_clockgating_state state) 1468 { 1469 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1470 1471 if (adev->asic_type == CHIP_ARCTURUS) 1472 mmhub_v9_4_set_clockgating(adev, state); 1473 else 1474 mmhub_v1_0_set_clockgating(adev, state); 1475 1476 athub_v1_0_set_clockgating(adev, state); 1477 1478 return 0; 1479 } 1480 1481 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) 1482 { 1483 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1484 1485 if (adev->asic_type == CHIP_ARCTURUS) 1486 mmhub_v9_4_get_clockgating(adev, flags); 1487 else 1488 mmhub_v1_0_get_clockgating(adev, flags); 1489 1490 athub_v1_0_get_clockgating(adev, flags); 1491 } 1492 1493 static int gmc_v9_0_set_powergating_state(void *handle, 1494 enum amd_powergating_state state) 1495 { 1496 return 0; 1497 } 1498 1499 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 1500 .name = "gmc_v9_0", 1501 .early_init = gmc_v9_0_early_init, 1502 .late_init = gmc_v9_0_late_init, 1503 .sw_init = gmc_v9_0_sw_init, 1504 .sw_fini = gmc_v9_0_sw_fini, 1505 .hw_init = gmc_v9_0_hw_init, 1506 .hw_fini = gmc_v9_0_hw_fini, 1507 .suspend = gmc_v9_0_suspend, 1508 .resume = gmc_v9_0_resume, 1509 .is_idle = gmc_v9_0_is_idle, 1510 .wait_for_idle = gmc_v9_0_wait_for_idle, 1511 .soft_reset = gmc_v9_0_soft_reset, 1512 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 1513 .set_powergating_state = gmc_v9_0_set_powergating_state, 1514 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 1515 }; 1516 1517 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 1518 { 1519 .type = AMD_IP_BLOCK_TYPE_GMC, 1520 .major = 9, 1521 .minor = 0, 1522 .rev = 0, 1523 .funcs = &gmc_v9_0_ip_funcs, 1524 }; 1525