1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "mmhub_v9_4.h" 53 #include "mmhub_v1_7.h" 54 #include "umc_v6_1.h" 55 #include "umc_v6_0.h" 56 #include "umc_v6_7.h" 57 #include "hdp_v4_0.h" 58 #include "mca_v3_0.h" 59 60 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 61 62 #include "amdgpu_ras.h" 63 #include "amdgpu_xgmi.h" 64 65 /* add these here since we already include dce12 headers and these are for DCN */ 66 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 67 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 68 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 69 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 70 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 72 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 73 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 74 75 76 static const char *gfxhub_client_ids[] = { 77 "CB", 78 "DB", 79 "IA", 80 "WD", 81 "CPF", 82 "CPC", 83 "CPG", 84 "RLC", 85 "TCP", 86 "SQC (inst)", 87 "SQC (data)", 88 "SQG", 89 "PA", 90 }; 91 92 static const char *mmhub_client_ids_raven[][2] = { 93 [0][0] = "MP1", 94 [1][0] = "MP0", 95 [2][0] = "VCN", 96 [3][0] = "VCNU", 97 [4][0] = "HDP", 98 [5][0] = "DCE", 99 [13][0] = "UTCL2", 100 [19][0] = "TLS", 101 [26][0] = "OSS", 102 [27][0] = "SDMA0", 103 [0][1] = "MP1", 104 [1][1] = "MP0", 105 [2][1] = "VCN", 106 [3][1] = "VCNU", 107 [4][1] = "HDP", 108 [5][1] = "XDP", 109 [6][1] = "DBGU0", 110 [7][1] = "DCE", 111 [8][1] = "DCEDWB0", 112 [9][1] = "DCEDWB1", 113 [26][1] = "OSS", 114 [27][1] = "SDMA0", 115 }; 116 117 static const char *mmhub_client_ids_renoir[][2] = { 118 [0][0] = "MP1", 119 [1][0] = "MP0", 120 [2][0] = "HDP", 121 [4][0] = "DCEDMC", 122 [5][0] = "DCEVGA", 123 [13][0] = "UTCL2", 124 [19][0] = "TLS", 125 [26][0] = "OSS", 126 [27][0] = "SDMA0", 127 [28][0] = "VCN", 128 [29][0] = "VCNU", 129 [30][0] = "JPEG", 130 [0][1] = "MP1", 131 [1][1] = "MP0", 132 [2][1] = "HDP", 133 [3][1] = "XDP", 134 [6][1] = "DBGU0", 135 [7][1] = "DCEDMC", 136 [8][1] = "DCEVGA", 137 [9][1] = "DCEDWB", 138 [26][1] = "OSS", 139 [27][1] = "SDMA0", 140 [28][1] = "VCN", 141 [29][1] = "VCNU", 142 [30][1] = "JPEG", 143 }; 144 145 static const char *mmhub_client_ids_vega10[][2] = { 146 [0][0] = "MP0", 147 [1][0] = "UVD", 148 [2][0] = "UVDU", 149 [3][0] = "HDP", 150 [13][0] = "UTCL2", 151 [14][0] = "OSS", 152 [15][0] = "SDMA1", 153 [32+0][0] = "VCE0", 154 [32+1][0] = "VCE0U", 155 [32+2][0] = "XDMA", 156 [32+3][0] = "DCE", 157 [32+4][0] = "MP1", 158 [32+14][0] = "SDMA0", 159 [0][1] = "MP0", 160 [1][1] = "UVD", 161 [2][1] = "UVDU", 162 [3][1] = "DBGU0", 163 [4][1] = "HDP", 164 [5][1] = "XDP", 165 [14][1] = "OSS", 166 [15][1] = "SDMA0", 167 [32+0][1] = "VCE0", 168 [32+1][1] = "VCE0U", 169 [32+2][1] = "XDMA", 170 [32+3][1] = "DCE", 171 [32+4][1] = "DCEDWB", 172 [32+5][1] = "MP1", 173 [32+6][1] = "DBGU1", 174 [32+14][1] = "SDMA1", 175 }; 176 177 static const char *mmhub_client_ids_vega12[][2] = { 178 [0][0] = "MP0", 179 [1][0] = "VCE0", 180 [2][0] = "VCE0U", 181 [3][0] = "HDP", 182 [13][0] = "UTCL2", 183 [14][0] = "OSS", 184 [15][0] = "SDMA1", 185 [32+0][0] = "DCE", 186 [32+1][0] = "XDMA", 187 [32+2][0] = "UVD", 188 [32+3][0] = "UVDU", 189 [32+4][0] = "MP1", 190 [32+15][0] = "SDMA0", 191 [0][1] = "MP0", 192 [1][1] = "VCE0", 193 [2][1] = "VCE0U", 194 [3][1] = "DBGU0", 195 [4][1] = "HDP", 196 [5][1] = "XDP", 197 [14][1] = "OSS", 198 [15][1] = "SDMA0", 199 [32+0][1] = "DCE", 200 [32+1][1] = "DCEDWB", 201 [32+2][1] = "XDMA", 202 [32+3][1] = "UVD", 203 [32+4][1] = "UVDU", 204 [32+5][1] = "MP1", 205 [32+6][1] = "DBGU1", 206 [32+15][1] = "SDMA1", 207 }; 208 209 static const char *mmhub_client_ids_vega20[][2] = { 210 [0][0] = "XDMA", 211 [1][0] = "DCE", 212 [2][0] = "VCE0", 213 [3][0] = "VCE0U", 214 [4][0] = "UVD", 215 [5][0] = "UVD1U", 216 [13][0] = "OSS", 217 [14][0] = "HDP", 218 [15][0] = "SDMA0", 219 [32+0][0] = "UVD", 220 [32+1][0] = "UVDU", 221 [32+2][0] = "MP1", 222 [32+3][0] = "MP0", 223 [32+12][0] = "UTCL2", 224 [32+14][0] = "SDMA1", 225 [0][1] = "XDMA", 226 [1][1] = "DCE", 227 [2][1] = "DCEDWB", 228 [3][1] = "VCE0", 229 [4][1] = "VCE0U", 230 [5][1] = "UVD1", 231 [6][1] = "UVD1U", 232 [7][1] = "DBGU0", 233 [8][1] = "XDP", 234 [13][1] = "OSS", 235 [14][1] = "HDP", 236 [15][1] = "SDMA0", 237 [32+0][1] = "UVD", 238 [32+1][1] = "UVDU", 239 [32+2][1] = "DBGU1", 240 [32+3][1] = "MP1", 241 [32+4][1] = "MP0", 242 [32+14][1] = "SDMA1", 243 }; 244 245 static const char *mmhub_client_ids_arcturus[][2] = { 246 [0][0] = "DBGU1", 247 [1][0] = "XDP", 248 [2][0] = "MP1", 249 [14][0] = "HDP", 250 [171][0] = "JPEG", 251 [172][0] = "VCN", 252 [173][0] = "VCNU", 253 [203][0] = "JPEG1", 254 [204][0] = "VCN1", 255 [205][0] = "VCN1U", 256 [256][0] = "SDMA0", 257 [257][0] = "SDMA1", 258 [258][0] = "SDMA2", 259 [259][0] = "SDMA3", 260 [260][0] = "SDMA4", 261 [261][0] = "SDMA5", 262 [262][0] = "SDMA6", 263 [263][0] = "SDMA7", 264 [384][0] = "OSS", 265 [0][1] = "DBGU1", 266 [1][1] = "XDP", 267 [2][1] = "MP1", 268 [14][1] = "HDP", 269 [171][1] = "JPEG", 270 [172][1] = "VCN", 271 [173][1] = "VCNU", 272 [203][1] = "JPEG1", 273 [204][1] = "VCN1", 274 [205][1] = "VCN1U", 275 [256][1] = "SDMA0", 276 [257][1] = "SDMA1", 277 [258][1] = "SDMA2", 278 [259][1] = "SDMA3", 279 [260][1] = "SDMA4", 280 [261][1] = "SDMA5", 281 [262][1] = "SDMA6", 282 [263][1] = "SDMA7", 283 [384][1] = "OSS", 284 }; 285 286 static const char *mmhub_client_ids_aldebaran[][2] = { 287 [2][0] = "MP1", 288 [3][0] = "MP0", 289 [32+1][0] = "DBGU_IO0", 290 [32+2][0] = "DBGU_IO2", 291 [32+4][0] = "MPIO", 292 [96+11][0] = "JPEG0", 293 [96+12][0] = "VCN0", 294 [96+13][0] = "VCNU0", 295 [128+11][0] = "JPEG1", 296 [128+12][0] = "VCN1", 297 [128+13][0] = "VCNU1", 298 [160+1][0] = "XDP", 299 [160+14][0] = "HDP", 300 [256+0][0] = "SDMA0", 301 [256+1][0] = "SDMA1", 302 [256+2][0] = "SDMA2", 303 [256+3][0] = "SDMA3", 304 [256+4][0] = "SDMA4", 305 [384+0][0] = "OSS", 306 [2][1] = "MP1", 307 [3][1] = "MP0", 308 [32+1][1] = "DBGU_IO0", 309 [32+2][1] = "DBGU_IO2", 310 [32+4][1] = "MPIO", 311 [96+11][1] = "JPEG0", 312 [96+12][1] = "VCN0", 313 [96+13][1] = "VCNU0", 314 [128+11][1] = "JPEG1", 315 [128+12][1] = "VCN1", 316 [128+13][1] = "VCNU1", 317 [160+1][1] = "XDP", 318 [160+14][1] = "HDP", 319 [256+0][1] = "SDMA0", 320 [256+1][1] = "SDMA1", 321 [256+2][1] = "SDMA2", 322 [256+3][1] = "SDMA3", 323 [256+4][1] = "SDMA4", 324 [384+0][1] = "OSS", 325 }; 326 327 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 328 { 329 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 330 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 331 }; 332 333 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 334 { 335 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 336 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 337 }; 338 339 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 340 (0x000143c0 + 0x00000000), 341 (0x000143c0 + 0x00000800), 342 (0x000143c0 + 0x00001000), 343 (0x000143c0 + 0x00001800), 344 (0x000543c0 + 0x00000000), 345 (0x000543c0 + 0x00000800), 346 (0x000543c0 + 0x00001000), 347 (0x000543c0 + 0x00001800), 348 (0x000943c0 + 0x00000000), 349 (0x000943c0 + 0x00000800), 350 (0x000943c0 + 0x00001000), 351 (0x000943c0 + 0x00001800), 352 (0x000d43c0 + 0x00000000), 353 (0x000d43c0 + 0x00000800), 354 (0x000d43c0 + 0x00001000), 355 (0x000d43c0 + 0x00001800), 356 (0x001143c0 + 0x00000000), 357 (0x001143c0 + 0x00000800), 358 (0x001143c0 + 0x00001000), 359 (0x001143c0 + 0x00001800), 360 (0x001543c0 + 0x00000000), 361 (0x001543c0 + 0x00000800), 362 (0x001543c0 + 0x00001000), 363 (0x001543c0 + 0x00001800), 364 (0x001943c0 + 0x00000000), 365 (0x001943c0 + 0x00000800), 366 (0x001943c0 + 0x00001000), 367 (0x001943c0 + 0x00001800), 368 (0x001d43c0 + 0x00000000), 369 (0x001d43c0 + 0x00000800), 370 (0x001d43c0 + 0x00001000), 371 (0x001d43c0 + 0x00001800), 372 }; 373 374 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 375 (0x000143e0 + 0x00000000), 376 (0x000143e0 + 0x00000800), 377 (0x000143e0 + 0x00001000), 378 (0x000143e0 + 0x00001800), 379 (0x000543e0 + 0x00000000), 380 (0x000543e0 + 0x00000800), 381 (0x000543e0 + 0x00001000), 382 (0x000543e0 + 0x00001800), 383 (0x000943e0 + 0x00000000), 384 (0x000943e0 + 0x00000800), 385 (0x000943e0 + 0x00001000), 386 (0x000943e0 + 0x00001800), 387 (0x000d43e0 + 0x00000000), 388 (0x000d43e0 + 0x00000800), 389 (0x000d43e0 + 0x00001000), 390 (0x000d43e0 + 0x00001800), 391 (0x001143e0 + 0x00000000), 392 (0x001143e0 + 0x00000800), 393 (0x001143e0 + 0x00001000), 394 (0x001143e0 + 0x00001800), 395 (0x001543e0 + 0x00000000), 396 (0x001543e0 + 0x00000800), 397 (0x001543e0 + 0x00001000), 398 (0x001543e0 + 0x00001800), 399 (0x001943e0 + 0x00000000), 400 (0x001943e0 + 0x00000800), 401 (0x001943e0 + 0x00001000), 402 (0x001943e0 + 0x00001800), 403 (0x001d43e0 + 0x00000000), 404 (0x001d43e0 + 0x00000800), 405 (0x001d43e0 + 0x00001000), 406 (0x001d43e0 + 0x00001800), 407 }; 408 409 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 410 struct amdgpu_irq_src *src, 411 unsigned type, 412 enum amdgpu_interrupt_state state) 413 { 414 u32 bits, i, tmp, reg; 415 416 /* Devices newer then VEGA10/12 shall have these programming 417 sequences performed by PSP BL */ 418 if (adev->asic_type >= CHIP_VEGA20) 419 return 0; 420 421 bits = 0x7f; 422 423 switch (state) { 424 case AMDGPU_IRQ_STATE_DISABLE: 425 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 426 reg = ecc_umc_mcumc_ctrl_addrs[i]; 427 tmp = RREG32(reg); 428 tmp &= ~bits; 429 WREG32(reg, tmp); 430 } 431 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 432 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 433 tmp = RREG32(reg); 434 tmp &= ~bits; 435 WREG32(reg, tmp); 436 } 437 break; 438 case AMDGPU_IRQ_STATE_ENABLE: 439 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 440 reg = ecc_umc_mcumc_ctrl_addrs[i]; 441 tmp = RREG32(reg); 442 tmp |= bits; 443 WREG32(reg, tmp); 444 } 445 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 446 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 447 tmp = RREG32(reg); 448 tmp |= bits; 449 WREG32(reg, tmp); 450 } 451 break; 452 default: 453 break; 454 } 455 456 return 0; 457 } 458 459 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 460 struct amdgpu_irq_src *src, 461 unsigned type, 462 enum amdgpu_interrupt_state state) 463 { 464 struct amdgpu_vmhub *hub; 465 u32 tmp, reg, bits, i, j; 466 467 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 468 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 469 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 470 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 471 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 472 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 473 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 474 475 switch (state) { 476 case AMDGPU_IRQ_STATE_DISABLE: 477 for (j = 0; j < adev->num_vmhubs; j++) { 478 hub = &adev->vmhub[j]; 479 for (i = 0; i < 16; i++) { 480 reg = hub->vm_context0_cntl + i; 481 482 if (j == AMDGPU_GFXHUB_0) 483 tmp = RREG32_SOC15_IP(GC, reg); 484 else 485 tmp = RREG32_SOC15_IP(MMHUB, reg); 486 487 tmp &= ~bits; 488 489 if (j == AMDGPU_GFXHUB_0) 490 WREG32_SOC15_IP(GC, reg, tmp); 491 else 492 WREG32_SOC15_IP(MMHUB, reg, tmp); 493 } 494 } 495 break; 496 case AMDGPU_IRQ_STATE_ENABLE: 497 for (j = 0; j < adev->num_vmhubs; j++) { 498 hub = &adev->vmhub[j]; 499 for (i = 0; i < 16; i++) { 500 reg = hub->vm_context0_cntl + i; 501 502 if (j == AMDGPU_GFXHUB_0) 503 tmp = RREG32_SOC15_IP(GC, reg); 504 else 505 tmp = RREG32_SOC15_IP(MMHUB, reg); 506 507 tmp |= bits; 508 509 if (j == AMDGPU_GFXHUB_0) 510 WREG32_SOC15_IP(GC, reg, tmp); 511 else 512 WREG32_SOC15_IP(MMHUB, reg, tmp); 513 } 514 } 515 break; 516 default: 517 break; 518 } 519 520 return 0; 521 } 522 523 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 524 struct amdgpu_irq_src *source, 525 struct amdgpu_iv_entry *entry) 526 { 527 bool retry_fault = !!(entry->src_data[1] & 0x80); 528 bool write_fault = !!(entry->src_data[1] & 0x20); 529 uint32_t status = 0, cid = 0, rw = 0; 530 struct amdgpu_task_info task_info; 531 struct amdgpu_vmhub *hub; 532 const char *mmhub_cid; 533 const char *hub_name; 534 u64 addr; 535 536 addr = (u64)entry->src_data[0] << 12; 537 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 538 539 if (retry_fault) { 540 /* Returning 1 here also prevents sending the IV to the KFD */ 541 542 /* Process it onyl if it's the first fault for this address */ 543 if (entry->ih != &adev->irq.ih_soft && 544 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 545 entry->timestamp)) 546 return 1; 547 548 /* Delegate it to a different ring if the hardware hasn't 549 * already done it. 550 */ 551 if (entry->ih == &adev->irq.ih) { 552 amdgpu_irq_delegate(adev, entry, 8); 553 return 1; 554 } 555 556 /* Try to handle the recoverable page faults by filling page 557 * tables 558 */ 559 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault)) 560 return 1; 561 } 562 563 if (!printk_ratelimit()) 564 return 0; 565 566 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 567 hub_name = "mmhub0"; 568 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 569 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 570 hub_name = "mmhub1"; 571 hub = &adev->vmhub[AMDGPU_MMHUB_1]; 572 } else { 573 hub_name = "gfxhub0"; 574 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 575 } 576 577 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 578 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 579 580 dev_err(adev->dev, 581 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 582 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 583 hub_name, retry_fault ? "retry" : "no-retry", 584 entry->src_id, entry->ring_id, entry->vmid, 585 entry->pasid, task_info.process_name, task_info.tgid, 586 task_info.task_name, task_info.pid); 587 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 588 addr, entry->client_id, 589 soc15_ih_clientid_name[entry->client_id]); 590 591 if (amdgpu_sriov_vf(adev)) 592 return 0; 593 594 /* 595 * Issue a dummy read to wait for the status register to 596 * be updated to avoid reading an incorrect value due to 597 * the new fast GRBM interface. 598 */ 599 if ((entry->vmid_src == AMDGPU_GFXHUB_0) && 600 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 601 RREG32(hub->vm_l2_pro_fault_status); 602 603 status = RREG32(hub->vm_l2_pro_fault_status); 604 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 605 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 606 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 607 608 609 dev_err(adev->dev, 610 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 611 status); 612 if (hub == &adev->vmhub[AMDGPU_GFXHUB_0]) { 613 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 614 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 615 gfxhub_client_ids[cid], 616 cid); 617 } else { 618 switch (adev->ip_versions[MMHUB_HWIP][0]) { 619 case IP_VERSION(9, 0, 0): 620 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 621 break; 622 case IP_VERSION(9, 3, 0): 623 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 624 break; 625 case IP_VERSION(9, 4, 0): 626 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 627 break; 628 case IP_VERSION(9, 4, 1): 629 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 630 break; 631 case IP_VERSION(9, 1, 0): 632 case IP_VERSION(9, 2, 0): 633 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 634 break; 635 case IP_VERSION(1, 5, 0): 636 case IP_VERSION(2, 4, 0): 637 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 638 break; 639 case IP_VERSION(9, 4, 2): 640 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 641 break; 642 default: 643 mmhub_cid = NULL; 644 break; 645 } 646 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 647 mmhub_cid ? mmhub_cid : "unknown", cid); 648 } 649 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 650 REG_GET_FIELD(status, 651 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 652 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 653 REG_GET_FIELD(status, 654 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 655 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 656 REG_GET_FIELD(status, 657 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 658 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 659 REG_GET_FIELD(status, 660 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 661 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 662 return 0; 663 } 664 665 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 666 .set = gmc_v9_0_vm_fault_interrupt_state, 667 .process = gmc_v9_0_process_interrupt, 668 }; 669 670 671 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 672 .set = gmc_v9_0_ecc_interrupt_state, 673 .process = amdgpu_umc_process_ecc_irq, 674 }; 675 676 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 677 { 678 adev->gmc.vm_fault.num_types = 1; 679 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 680 681 if (!amdgpu_sriov_vf(adev) && 682 !adev->gmc.xgmi.connected_to_cpu) { 683 adev->gmc.ecc_irq.num_types = 1; 684 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 685 } 686 } 687 688 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 689 uint32_t flush_type) 690 { 691 u32 req = 0; 692 693 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 694 PER_VMID_INVALIDATE_REQ, 1 << vmid); 695 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 696 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 697 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 698 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 699 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 700 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 701 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 702 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 703 704 return req; 705 } 706 707 /** 708 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 709 * 710 * @adev: amdgpu_device pointer 711 * @vmhub: vmhub type 712 * 713 */ 714 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 715 uint32_t vmhub) 716 { 717 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 718 return false; 719 720 return ((vmhub == AMDGPU_MMHUB_0 || 721 vmhub == AMDGPU_MMHUB_1) && 722 (!amdgpu_sriov_vf(adev)) && 723 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 724 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 725 } 726 727 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 728 uint8_t vmid, uint16_t *p_pasid) 729 { 730 uint32_t value; 731 732 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 733 + vmid); 734 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 735 736 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 737 } 738 739 /* 740 * GART 741 * VMID 0 is the physical GPU addresses as used by the kernel. 742 * VMIDs 1-15 are used for userspace clients and are handled 743 * by the amdgpu vm/hsa code. 744 */ 745 746 /** 747 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 748 * 749 * @adev: amdgpu_device pointer 750 * @vmid: vm instance to flush 751 * @vmhub: which hub to flush 752 * @flush_type: the flush type 753 * 754 * Flush the TLB for the requested page table using certain type. 755 */ 756 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 757 uint32_t vmhub, uint32_t flush_type) 758 { 759 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 760 const unsigned eng = 17; 761 u32 j, inv_req, inv_req2, tmp; 762 struct amdgpu_vmhub *hub; 763 764 BUG_ON(vmhub >= adev->num_vmhubs); 765 766 hub = &adev->vmhub[vmhub]; 767 if (adev->gmc.xgmi.num_physical_nodes && 768 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) { 769 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 770 * heavy-weight TLB flush (type 2), which flushes 771 * both. Due to a race condition with concurrent 772 * memory accesses using the same TLB cache line, we 773 * still need a second TLB flush after this. 774 */ 775 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2); 776 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); 777 } else { 778 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 779 inv_req2 = 0; 780 } 781 782 /* This is necessary for a HW workaround under SRIOV as well 783 * as GFXOFF under bare metal 784 */ 785 if (adev->gfx.kiq.ring.sched.ready && 786 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 787 down_read_trylock(&adev->reset_sem)) { 788 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 789 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 790 791 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 792 1 << vmid); 793 up_read(&adev->reset_sem); 794 return; 795 } 796 797 spin_lock(&adev->gmc.invalidate_lock); 798 799 /* 800 * It may lose gpuvm invalidate acknowldege state across power-gating 801 * off cycle, add semaphore acquire before invalidation and semaphore 802 * release after invalidation to avoid entering power gated state 803 * to WA the Issue 804 */ 805 806 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 807 if (use_semaphore) { 808 for (j = 0; j < adev->usec_timeout; j++) { 809 /* a read return value of 1 means semaphore acquire */ 810 if (vmhub == AMDGPU_GFXHUB_0) 811 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 812 else 813 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 814 815 if (tmp & 0x1) 816 break; 817 udelay(1); 818 } 819 820 if (j >= adev->usec_timeout) 821 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 822 } 823 824 do { 825 if (vmhub == AMDGPU_GFXHUB_0) 826 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 827 else 828 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 829 830 /* 831 * Issue a dummy read to wait for the ACK register to 832 * be cleared to avoid a false ACK due to the new fast 833 * GRBM interface. 834 */ 835 if ((vmhub == AMDGPU_GFXHUB_0) && 836 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) 837 RREG32_NO_KIQ(hub->vm_inv_eng0_req + 838 hub->eng_distance * eng); 839 840 for (j = 0; j < adev->usec_timeout; j++) { 841 if (vmhub == AMDGPU_GFXHUB_0) 842 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 843 else 844 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 845 846 if (tmp & (1 << vmid)) 847 break; 848 udelay(1); 849 } 850 851 inv_req = inv_req2; 852 inv_req2 = 0; 853 } while (inv_req); 854 855 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 856 if (use_semaphore) { 857 /* 858 * add semaphore release after invalidation, 859 * write with 0 means semaphore release 860 */ 861 if (vmhub == AMDGPU_GFXHUB_0) 862 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 863 else 864 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 865 } 866 867 spin_unlock(&adev->gmc.invalidate_lock); 868 869 if (j < adev->usec_timeout) 870 return; 871 872 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 873 } 874 875 /** 876 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 877 * 878 * @adev: amdgpu_device pointer 879 * @pasid: pasid to be flush 880 * @flush_type: the flush type 881 * @all_hub: flush all hubs 882 * 883 * Flush the TLB for the requested pasid. 884 */ 885 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 886 uint16_t pasid, uint32_t flush_type, 887 bool all_hub) 888 { 889 int vmid, i; 890 signed long r; 891 uint32_t seq; 892 uint16_t queried_pasid; 893 bool ret; 894 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 895 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 896 897 if (amdgpu_in_reset(adev)) 898 return -EIO; 899 900 if (ring->sched.ready && down_read_trylock(&adev->reset_sem)) { 901 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 902 * heavy-weight TLB flush (type 2), which flushes 903 * both. Due to a race condition with concurrent 904 * memory accesses using the same TLB cache line, we 905 * still need a second TLB flush after this. 906 */ 907 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes && 908 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)); 909 /* 2 dwords flush + 8 dwords fence */ 910 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8; 911 912 if (vega20_xgmi_wa) 913 ndw += kiq->pmf->invalidate_tlbs_size; 914 915 spin_lock(&adev->gfx.kiq.ring_lock); 916 /* 2 dwords flush + 8 dwords fence */ 917 amdgpu_ring_alloc(ring, ndw); 918 if (vega20_xgmi_wa) 919 kiq->pmf->kiq_invalidate_tlbs(ring, 920 pasid, 2, all_hub); 921 kiq->pmf->kiq_invalidate_tlbs(ring, 922 pasid, flush_type, all_hub); 923 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 924 if (r) { 925 amdgpu_ring_undo(ring); 926 spin_unlock(&adev->gfx.kiq.ring_lock); 927 up_read(&adev->reset_sem); 928 return -ETIME; 929 } 930 931 amdgpu_ring_commit(ring); 932 spin_unlock(&adev->gfx.kiq.ring_lock); 933 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 934 if (r < 1) { 935 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 936 up_read(&adev->reset_sem); 937 return -ETIME; 938 } 939 up_read(&adev->reset_sem); 940 return 0; 941 } 942 943 for (vmid = 1; vmid < 16; vmid++) { 944 945 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 946 &queried_pasid); 947 if (ret && queried_pasid == pasid) { 948 if (all_hub) { 949 for (i = 0; i < adev->num_vmhubs; i++) 950 gmc_v9_0_flush_gpu_tlb(adev, vmid, 951 i, flush_type); 952 } else { 953 gmc_v9_0_flush_gpu_tlb(adev, vmid, 954 AMDGPU_GFXHUB_0, flush_type); 955 } 956 break; 957 } 958 } 959 960 return 0; 961 962 } 963 964 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 965 unsigned vmid, uint64_t pd_addr) 966 { 967 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 968 struct amdgpu_device *adev = ring->adev; 969 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 970 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 971 unsigned eng = ring->vm_inv_eng; 972 973 /* 974 * It may lose gpuvm invalidate acknowldege state across power-gating 975 * off cycle, add semaphore acquire before invalidation and semaphore 976 * release after invalidation to avoid entering power gated state 977 * to WA the Issue 978 */ 979 980 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 981 if (use_semaphore) 982 /* a read return value of 1 means semaphore acuqire */ 983 amdgpu_ring_emit_reg_wait(ring, 984 hub->vm_inv_eng0_sem + 985 hub->eng_distance * eng, 0x1, 0x1); 986 987 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 988 (hub->ctx_addr_distance * vmid), 989 lower_32_bits(pd_addr)); 990 991 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 992 (hub->ctx_addr_distance * vmid), 993 upper_32_bits(pd_addr)); 994 995 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 996 hub->eng_distance * eng, 997 hub->vm_inv_eng0_ack + 998 hub->eng_distance * eng, 999 req, 1 << vmid); 1000 1001 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1002 if (use_semaphore) 1003 /* 1004 * add semaphore release after invalidation, 1005 * write with 0 means semaphore release 1006 */ 1007 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1008 hub->eng_distance * eng, 0); 1009 1010 return pd_addr; 1011 } 1012 1013 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 1014 unsigned pasid) 1015 { 1016 struct amdgpu_device *adev = ring->adev; 1017 uint32_t reg; 1018 1019 /* Do nothing because there's no lut register for mmhub1. */ 1020 if (ring->funcs->vmhub == AMDGPU_MMHUB_1) 1021 return; 1022 1023 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 1024 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1025 else 1026 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1027 1028 amdgpu_ring_emit_wreg(ring, reg, pasid); 1029 } 1030 1031 /* 1032 * PTE format on VEGA 10: 1033 * 63:59 reserved 1034 * 58:57 mtype 1035 * 56 F 1036 * 55 L 1037 * 54 P 1038 * 53 SW 1039 * 52 T 1040 * 50:48 reserved 1041 * 47:12 4k physical page base address 1042 * 11:7 fragment 1043 * 6 write 1044 * 5 read 1045 * 4 exe 1046 * 3 Z 1047 * 2 snooped 1048 * 1 system 1049 * 0 valid 1050 * 1051 * PDE format on VEGA 10: 1052 * 63:59 block fragment size 1053 * 58:55 reserved 1054 * 54 P 1055 * 53:48 reserved 1056 * 47:6 physical base address of PD or PTE 1057 * 5:3 reserved 1058 * 2 C 1059 * 1 system 1060 * 0 valid 1061 */ 1062 1063 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1064 1065 { 1066 switch (flags) { 1067 case AMDGPU_VM_MTYPE_DEFAULT: 1068 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1069 case AMDGPU_VM_MTYPE_NC: 1070 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1071 case AMDGPU_VM_MTYPE_WC: 1072 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 1073 case AMDGPU_VM_MTYPE_RW: 1074 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 1075 case AMDGPU_VM_MTYPE_CC: 1076 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1077 case AMDGPU_VM_MTYPE_UC: 1078 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 1079 default: 1080 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1081 } 1082 } 1083 1084 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1085 uint64_t *addr, uint64_t *flags) 1086 { 1087 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1088 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1089 BUG_ON(*addr & 0xFFFF00000000003FULL); 1090 1091 if (!adev->gmc.translate_further) 1092 return; 1093 1094 if (level == AMDGPU_VM_PDB1) { 1095 /* Set the block fragment size */ 1096 if (!(*flags & AMDGPU_PDE_PTE)) 1097 *flags |= AMDGPU_PDE_BFS(0x9); 1098 1099 } else if (level == AMDGPU_VM_PDB0) { 1100 if (*flags & AMDGPU_PDE_PTE) 1101 *flags &= ~AMDGPU_PDE_PTE; 1102 else 1103 *flags |= AMDGPU_PTE_TF; 1104 } 1105 } 1106 1107 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1108 struct amdgpu_bo_va_mapping *mapping, 1109 uint64_t *flags) 1110 { 1111 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1112 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1113 1114 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1115 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1116 1117 if (mapping->flags & AMDGPU_PTE_PRT) { 1118 *flags |= AMDGPU_PTE_PRT; 1119 *flags &= ~AMDGPU_PTE_VALID; 1120 } 1121 1122 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1123 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) && 1124 !(*flags & AMDGPU_PTE_SYSTEM) && 1125 mapping->bo_va->is_xgmi) 1126 *flags |= AMDGPU_PTE_SNOOPED; 1127 1128 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) 1129 *flags |= mapping->flags & AMDGPU_PTE_SNOOPED; 1130 } 1131 1132 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1133 { 1134 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1135 unsigned size; 1136 1137 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1138 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1139 } else { 1140 u32 viewport; 1141 1142 switch (adev->ip_versions[DCE_HWIP][0]) { 1143 case IP_VERSION(1, 0, 0): 1144 case IP_VERSION(1, 0, 1): 1145 case IP_VERSION(2, 1, 0): 1146 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1147 size = (REG_GET_FIELD(viewport, 1148 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1149 REG_GET_FIELD(viewport, 1150 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1151 4); 1152 break; 1153 default: 1154 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1155 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1156 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1157 4); 1158 break; 1159 } 1160 } 1161 1162 return size; 1163 } 1164 1165 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1166 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1167 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1168 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1169 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1170 .map_mtype = gmc_v9_0_map_mtype, 1171 .get_vm_pde = gmc_v9_0_get_vm_pde, 1172 .get_vm_pte = gmc_v9_0_get_vm_pte, 1173 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1174 }; 1175 1176 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1177 { 1178 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1179 } 1180 1181 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1182 { 1183 switch (adev->ip_versions[UMC_HWIP][0]) { 1184 case IP_VERSION(6, 0, 0): 1185 adev->umc.funcs = &umc_v6_0_funcs; 1186 break; 1187 case IP_VERSION(6, 1, 1): 1188 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1189 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1190 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1191 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1192 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1193 adev->umc.ras_funcs = &umc_v6_1_ras_funcs; 1194 break; 1195 case IP_VERSION(6, 1, 2): 1196 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1197 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1198 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1199 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1200 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1201 adev->umc.ras_funcs = &umc_v6_1_ras_funcs; 1202 break; 1203 case IP_VERSION(6, 7, 0): 1204 adev->umc.max_ras_err_cnt_per_query = UMC_V6_7_TOTAL_CHANNEL_NUM; 1205 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1206 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1207 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1208 if (!adev->gmc.xgmi.connected_to_cpu) 1209 adev->umc.ras_funcs = &umc_v6_7_ras_funcs; 1210 if (1 & adev->smuio.funcs->get_die_id(adev)) 1211 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1212 else 1213 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1214 break; 1215 default: 1216 break; 1217 } 1218 } 1219 1220 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1221 { 1222 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1223 case IP_VERSION(9, 4, 1): 1224 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1225 break; 1226 case IP_VERSION(9, 4, 2): 1227 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1228 break; 1229 default: 1230 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1231 break; 1232 } 1233 } 1234 1235 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1236 { 1237 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1238 case IP_VERSION(9, 4, 0): 1239 adev->mmhub.ras_funcs = &mmhub_v1_0_ras_funcs; 1240 break; 1241 case IP_VERSION(9, 4, 1): 1242 adev->mmhub.ras_funcs = &mmhub_v9_4_ras_funcs; 1243 break; 1244 case IP_VERSION(9, 4, 2): 1245 adev->mmhub.ras_funcs = &mmhub_v1_7_ras_funcs; 1246 break; 1247 default: 1248 /* mmhub ras is not available */ 1249 break; 1250 } 1251 } 1252 1253 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1254 { 1255 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1256 } 1257 1258 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1259 { 1260 adev->hdp.ras_funcs = &hdp_v4_0_ras_funcs; 1261 } 1262 1263 static void gmc_v9_0_set_mca_funcs(struct amdgpu_device *adev) 1264 { 1265 /* is UMC the right IP to check for MCA? Maybe DF? */ 1266 switch (adev->ip_versions[UMC_HWIP][0]) { 1267 case IP_VERSION(6, 7, 0): 1268 if (!adev->gmc.xgmi.connected_to_cpu) 1269 adev->mca.funcs = &mca_v3_0_funcs; 1270 break; 1271 default: 1272 break; 1273 } 1274 } 1275 1276 static int gmc_v9_0_early_init(void *handle) 1277 { 1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1279 1280 /* ARCT and VEGA20 don't have XGMI defined in their IP discovery tables */ 1281 if (adev->asic_type == CHIP_VEGA20 || 1282 adev->asic_type == CHIP_ARCTURUS) 1283 adev->gmc.xgmi.supported = true; 1284 1285 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(6, 1, 0)) { 1286 adev->gmc.xgmi.supported = true; 1287 adev->gmc.xgmi.connected_to_cpu = 1288 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1289 } 1290 1291 gmc_v9_0_set_gmc_funcs(adev); 1292 gmc_v9_0_set_irq_funcs(adev); 1293 gmc_v9_0_set_umc_funcs(adev); 1294 gmc_v9_0_set_mmhub_funcs(adev); 1295 gmc_v9_0_set_mmhub_ras_funcs(adev); 1296 gmc_v9_0_set_gfxhub_funcs(adev); 1297 gmc_v9_0_set_hdp_ras_funcs(adev); 1298 gmc_v9_0_set_mca_funcs(adev); 1299 1300 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1301 adev->gmc.shared_aperture_end = 1302 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1303 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1304 adev->gmc.private_aperture_end = 1305 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1306 1307 return 0; 1308 } 1309 1310 static int gmc_v9_0_late_init(void *handle) 1311 { 1312 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1313 int r; 1314 1315 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1316 if (r) 1317 return r; 1318 1319 /* 1320 * Workaround performance drop issue with VBIOS enables partial 1321 * writes, while disables HBM ECC for vega10. 1322 */ 1323 if (!amdgpu_sriov_vf(adev) && 1324 (adev->ip_versions[UMC_HWIP][0] == IP_VERSION(6, 0, 0))) { 1325 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1326 if (adev->df.funcs && 1327 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1328 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1329 } 1330 } 1331 1332 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1333 if (adev->mmhub.ras_funcs && 1334 adev->mmhub.ras_funcs->reset_ras_error_count) 1335 adev->mmhub.ras_funcs->reset_ras_error_count(adev); 1336 1337 if (adev->hdp.ras_funcs && 1338 adev->hdp.ras_funcs->reset_ras_error_count) 1339 adev->hdp.ras_funcs->reset_ras_error_count(adev); 1340 } 1341 1342 r = amdgpu_gmc_ras_late_init(adev); 1343 if (r) 1344 return r; 1345 1346 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1347 } 1348 1349 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1350 struct amdgpu_gmc *mc) 1351 { 1352 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1353 1354 /* add the xgmi offset of the physical node */ 1355 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1356 if (adev->gmc.xgmi.connected_to_cpu) { 1357 amdgpu_gmc_sysvm_location(adev, mc); 1358 } else { 1359 amdgpu_gmc_vram_location(adev, mc, base); 1360 amdgpu_gmc_gart_location(adev, mc); 1361 amdgpu_gmc_agp_location(adev, mc); 1362 } 1363 /* base offset of vram pages */ 1364 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1365 1366 /* XXX: add the xgmi offset of the physical node? */ 1367 adev->vm_manager.vram_base_offset += 1368 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1369 } 1370 1371 /** 1372 * gmc_v9_0_mc_init - initialize the memory controller driver params 1373 * 1374 * @adev: amdgpu_device pointer 1375 * 1376 * Look up the amount of vram, vram width, and decide how to place 1377 * vram and gart within the GPU's physical address space. 1378 * Returns 0 for success. 1379 */ 1380 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1381 { 1382 int r; 1383 1384 /* size in MB on si */ 1385 adev->gmc.mc_vram_size = 1386 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1387 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1388 1389 if (!(adev->flags & AMD_IS_APU) && 1390 !adev->gmc.xgmi.connected_to_cpu) { 1391 r = amdgpu_device_resize_fb_bar(adev); 1392 if (r) 1393 return r; 1394 } 1395 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1396 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1397 1398 #ifdef CONFIG_X86_64 1399 /* 1400 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1401 * interface can use VRAM through here as it appears system reserved 1402 * memory in host address space. 1403 * 1404 * For APUs, VRAM is just the stolen system memory and can be accessed 1405 * directly. 1406 * 1407 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1408 */ 1409 1410 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1411 if ((adev->flags & AMD_IS_APU) || 1412 (adev->gmc.xgmi.supported && 1413 adev->gmc.xgmi.connected_to_cpu)) { 1414 adev->gmc.aper_base = 1415 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1416 adev->gmc.xgmi.physical_node_id * 1417 adev->gmc.xgmi.node_segment_size; 1418 adev->gmc.aper_size = adev->gmc.real_vram_size; 1419 } 1420 1421 #endif 1422 /* In case the PCI BAR is larger than the actual amount of vram */ 1423 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1424 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 1425 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 1426 1427 /* set the gart size */ 1428 if (amdgpu_gart_size == -1) { 1429 switch (adev->ip_versions[GC_HWIP][0]) { 1430 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1431 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1432 case IP_VERSION(9, 4, 0): 1433 case IP_VERSION(9, 4, 1): 1434 case IP_VERSION(9, 4, 2): 1435 default: 1436 adev->gmc.gart_size = 512ULL << 20; 1437 break; 1438 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1439 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1440 case IP_VERSION(9, 3, 0): 1441 adev->gmc.gart_size = 1024ULL << 20; 1442 break; 1443 } 1444 } else { 1445 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1446 } 1447 1448 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1449 1450 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1451 1452 return 0; 1453 } 1454 1455 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1456 { 1457 int r; 1458 1459 if (adev->gart.bo) { 1460 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1461 return 0; 1462 } 1463 1464 if (adev->gmc.xgmi.connected_to_cpu) { 1465 adev->gmc.vmid0_page_table_depth = 1; 1466 adev->gmc.vmid0_page_table_block_size = 12; 1467 } else { 1468 adev->gmc.vmid0_page_table_depth = 0; 1469 adev->gmc.vmid0_page_table_block_size = 0; 1470 } 1471 1472 /* Initialize common gart structure */ 1473 r = amdgpu_gart_init(adev); 1474 if (r) 1475 return r; 1476 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1477 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1478 AMDGPU_PTE_EXECUTABLE; 1479 1480 r = amdgpu_gart_table_vram_alloc(adev); 1481 if (r) 1482 return r; 1483 1484 if (adev->gmc.xgmi.connected_to_cpu) { 1485 r = amdgpu_gmc_pdb0_alloc(adev); 1486 } 1487 1488 return r; 1489 } 1490 1491 /** 1492 * gmc_v9_0_save_registers - saves regs 1493 * 1494 * @adev: amdgpu_device pointer 1495 * 1496 * This saves potential register values that should be 1497 * restored upon resume 1498 */ 1499 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1500 { 1501 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1502 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) 1503 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1504 } 1505 1506 static int gmc_v9_0_sw_init(void *handle) 1507 { 1508 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 1509 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1510 1511 adev->gfxhub.funcs->init(adev); 1512 1513 adev->mmhub.funcs->init(adev); 1514 if (adev->mca.funcs) 1515 adev->mca.funcs->init(adev); 1516 1517 spin_lock_init(&adev->gmc.invalidate_lock); 1518 1519 r = amdgpu_atomfirmware_get_vram_info(adev, 1520 &vram_width, &vram_type, &vram_vendor); 1521 if (amdgpu_sriov_vf(adev)) 1522 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1523 * and DF related registers is not readable, seems hardcord is the 1524 * only way to set the correct vram_width 1525 */ 1526 adev->gmc.vram_width = 2048; 1527 else if (amdgpu_emu_mode != 1) 1528 adev->gmc.vram_width = vram_width; 1529 1530 if (!adev->gmc.vram_width) { 1531 int chansize, numchan; 1532 1533 /* hbm memory channel size */ 1534 if (adev->flags & AMD_IS_APU) 1535 chansize = 64; 1536 else 1537 chansize = 128; 1538 if (adev->df.funcs && 1539 adev->df.funcs->get_hbm_channel_number) { 1540 numchan = adev->df.funcs->get_hbm_channel_number(adev); 1541 adev->gmc.vram_width = numchan * chansize; 1542 } 1543 } 1544 1545 adev->gmc.vram_type = vram_type; 1546 adev->gmc.vram_vendor = vram_vendor; 1547 switch (adev->ip_versions[GC_HWIP][0]) { 1548 case IP_VERSION(9, 1, 0): 1549 case IP_VERSION(9, 2, 2): 1550 adev->num_vmhubs = 2; 1551 1552 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1553 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1554 } else { 1555 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1556 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1557 adev->gmc.translate_further = 1558 adev->vm_manager.num_level > 1; 1559 } 1560 break; 1561 case IP_VERSION(9, 0, 1): 1562 case IP_VERSION(9, 2, 1): 1563 case IP_VERSION(9, 4, 0): 1564 case IP_VERSION(9, 3, 0): 1565 case IP_VERSION(9, 4, 2): 1566 adev->num_vmhubs = 2; 1567 1568 1569 /* 1570 * To fulfill 4-level page support, 1571 * vm size is 256TB (48bit), maximum size of Vega10, 1572 * block size 512 (9bit) 1573 */ 1574 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 1575 if (amdgpu_sriov_vf(adev)) 1576 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 1577 else 1578 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1579 break; 1580 case IP_VERSION(9, 4, 1): 1581 adev->num_vmhubs = 3; 1582 1583 /* Keep the vm size same with Vega20 */ 1584 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1585 break; 1586 default: 1587 break; 1588 } 1589 1590 /* This interrupt is VMC page fault.*/ 1591 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1592 &adev->gmc.vm_fault); 1593 if (r) 1594 return r; 1595 1596 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) { 1597 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1598 &adev->gmc.vm_fault); 1599 if (r) 1600 return r; 1601 } 1602 1603 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1604 &adev->gmc.vm_fault); 1605 1606 if (r) 1607 return r; 1608 1609 if (!amdgpu_sriov_vf(adev) && 1610 !adev->gmc.xgmi.connected_to_cpu) { 1611 /* interrupt sent to DF. */ 1612 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1613 &adev->gmc.ecc_irq); 1614 if (r) 1615 return r; 1616 } 1617 1618 /* Set the internal MC address mask 1619 * This is the max address of the GPU's 1620 * internal address space. 1621 */ 1622 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1623 1624 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 1625 if (r) { 1626 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 1627 return r; 1628 } 1629 adev->need_swiotlb = drm_need_swiotlb(44); 1630 1631 r = gmc_v9_0_mc_init(adev); 1632 if (r) 1633 return r; 1634 1635 amdgpu_gmc_get_vbios_allocations(adev); 1636 1637 /* Memory manager */ 1638 r = amdgpu_bo_init(adev); 1639 if (r) 1640 return r; 1641 1642 r = gmc_v9_0_gart_init(adev); 1643 if (r) 1644 return r; 1645 1646 /* 1647 * number of VMs 1648 * VMID 0 is reserved for System 1649 * amdgpu graphics/compute will use VMIDs 1..n-1 1650 * amdkfd will use VMIDs n..15 1651 * 1652 * The first KFD VMID is 8 for GPUs with graphics, 3 for 1653 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 1654 * for video processing. 1655 */ 1656 adev->vm_manager.first_kfd_vmid = 1657 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || 1658 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) ? 3 : 8; 1659 1660 amdgpu_vm_manager_init(adev); 1661 1662 gmc_v9_0_save_registers(adev); 1663 1664 return 0; 1665 } 1666 1667 static int gmc_v9_0_sw_fini(void *handle) 1668 { 1669 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1670 1671 amdgpu_gmc_ras_fini(adev); 1672 amdgpu_gem_force_release(adev); 1673 amdgpu_vm_manager_fini(adev); 1674 amdgpu_gart_table_vram_free(adev); 1675 amdgpu_bo_unref(&adev->gmc.pdb0_bo); 1676 amdgpu_bo_fini(adev); 1677 1678 return 0; 1679 } 1680 1681 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 1682 { 1683 1684 switch (adev->ip_versions[MMHUB_HWIP][0]) { 1685 case IP_VERSION(9, 0, 0): 1686 if (amdgpu_sriov_vf(adev)) 1687 break; 1688 fallthrough; 1689 case IP_VERSION(9, 4, 0): 1690 soc15_program_register_sequence(adev, 1691 golden_settings_mmhub_1_0_0, 1692 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 1693 soc15_program_register_sequence(adev, 1694 golden_settings_athub_1_0_0, 1695 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1696 break; 1697 case IP_VERSION(9, 1, 0): 1698 case IP_VERSION(9, 2, 0): 1699 /* TODO for renoir */ 1700 soc15_program_register_sequence(adev, 1701 golden_settings_athub_1_0_0, 1702 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1703 break; 1704 default: 1705 break; 1706 } 1707 } 1708 1709 /** 1710 * gmc_v9_0_restore_registers - restores regs 1711 * 1712 * @adev: amdgpu_device pointer 1713 * 1714 * This restores register values, saved at suspend. 1715 */ 1716 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 1717 { 1718 if ((adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 0)) || 1719 (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(1, 0, 1))) { 1720 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 1721 WARN_ON(adev->gmc.sdpif_register != 1722 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 1723 } 1724 } 1725 1726 /** 1727 * gmc_v9_0_gart_enable - gart enable 1728 * 1729 * @adev: amdgpu_device pointer 1730 */ 1731 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1732 { 1733 int r; 1734 1735 if (adev->gmc.xgmi.connected_to_cpu) 1736 amdgpu_gmc_init_pdb0(adev); 1737 1738 if (adev->gart.bo == NULL) { 1739 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1740 return -EINVAL; 1741 } 1742 1743 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 1744 goto skip_pin_bo; 1745 1746 r = amdgpu_gart_table_vram_pin(adev); 1747 if (r) 1748 return r; 1749 1750 skip_pin_bo: 1751 r = adev->gfxhub.funcs->gart_enable(adev); 1752 if (r) 1753 return r; 1754 1755 r = adev->mmhub.funcs->gart_enable(adev); 1756 if (r) 1757 return r; 1758 1759 DRM_INFO("PCIE GART of %uM enabled.\n", 1760 (unsigned)(adev->gmc.gart_size >> 20)); 1761 if (adev->gmc.pdb0_bo) 1762 DRM_INFO("PDB0 located at 0x%016llX\n", 1763 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 1764 DRM_INFO("PTB located at 0x%016llX\n", 1765 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1766 1767 adev->gart.ready = true; 1768 return 0; 1769 } 1770 1771 static int gmc_v9_0_hw_init(void *handle) 1772 { 1773 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1774 bool value; 1775 int i; 1776 1777 /* The sequence of these two function calls matters.*/ 1778 gmc_v9_0_init_golden_registers(adev); 1779 1780 if (adev->mode_info.num_crtc) { 1781 /* Lockout access through VGA aperture*/ 1782 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1783 /* disable VGA render */ 1784 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1785 } 1786 1787 if (adev->mmhub.funcs->update_power_gating) 1788 adev->mmhub.funcs->update_power_gating(adev, true); 1789 1790 adev->hdp.funcs->init_registers(adev); 1791 1792 /* After HDP is initialized, flush HDP.*/ 1793 adev->hdp.funcs->flush_hdp(adev, NULL); 1794 1795 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1796 value = false; 1797 else 1798 value = true; 1799 1800 if (!amdgpu_sriov_vf(adev)) { 1801 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 1802 adev->mmhub.funcs->set_fault_enable_default(adev, value); 1803 } 1804 for (i = 0; i < adev->num_vmhubs; ++i) 1805 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 1806 1807 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1808 adev->umc.funcs->init_registers(adev); 1809 1810 return gmc_v9_0_gart_enable(adev); 1811 } 1812 1813 /** 1814 * gmc_v9_0_gart_disable - gart disable 1815 * 1816 * @adev: amdgpu_device pointer 1817 * 1818 * This disables all VM page table. 1819 */ 1820 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1821 { 1822 adev->gfxhub.funcs->gart_disable(adev); 1823 adev->mmhub.funcs->gart_disable(adev); 1824 amdgpu_gart_table_vram_unpin(adev); 1825 } 1826 1827 static int gmc_v9_0_hw_fini(void *handle) 1828 { 1829 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1830 1831 gmc_v9_0_gart_disable(adev); 1832 1833 if (amdgpu_sriov_vf(adev)) { 1834 /* full access mode, so don't touch any GMC register */ 1835 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1836 return 0; 1837 } 1838 1839 /* 1840 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 1841 * a correct cached state for GMC. Otherwise, the "gate" again 1842 * operation on S3 resuming will fail due to wrong cached state. 1843 */ 1844 if (adev->mmhub.funcs->update_power_gating) 1845 adev->mmhub.funcs->update_power_gating(adev, false); 1846 1847 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1848 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1849 1850 return 0; 1851 } 1852 1853 static int gmc_v9_0_suspend(void *handle) 1854 { 1855 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1856 1857 return gmc_v9_0_hw_fini(adev); 1858 } 1859 1860 static int gmc_v9_0_resume(void *handle) 1861 { 1862 int r; 1863 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1864 1865 r = gmc_v9_0_hw_init(adev); 1866 if (r) 1867 return r; 1868 1869 amdgpu_vmid_reset_all(adev); 1870 1871 return 0; 1872 } 1873 1874 static bool gmc_v9_0_is_idle(void *handle) 1875 { 1876 /* MC is always ready in GMC v9.*/ 1877 return true; 1878 } 1879 1880 static int gmc_v9_0_wait_for_idle(void *handle) 1881 { 1882 /* There is no need to wait for MC idle in GMC v9.*/ 1883 return 0; 1884 } 1885 1886 static int gmc_v9_0_soft_reset(void *handle) 1887 { 1888 /* XXX for emulation.*/ 1889 return 0; 1890 } 1891 1892 static int gmc_v9_0_set_clockgating_state(void *handle, 1893 enum amd_clockgating_state state) 1894 { 1895 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1896 1897 adev->mmhub.funcs->set_clockgating(adev, state); 1898 1899 athub_v1_0_set_clockgating(adev, state); 1900 1901 return 0; 1902 } 1903 1904 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) 1905 { 1906 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1907 1908 adev->mmhub.funcs->get_clockgating(adev, flags); 1909 1910 athub_v1_0_get_clockgating(adev, flags); 1911 } 1912 1913 static int gmc_v9_0_set_powergating_state(void *handle, 1914 enum amd_powergating_state state) 1915 { 1916 return 0; 1917 } 1918 1919 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 1920 .name = "gmc_v9_0", 1921 .early_init = gmc_v9_0_early_init, 1922 .late_init = gmc_v9_0_late_init, 1923 .sw_init = gmc_v9_0_sw_init, 1924 .sw_fini = gmc_v9_0_sw_fini, 1925 .hw_init = gmc_v9_0_hw_init, 1926 .hw_fini = gmc_v9_0_hw_fini, 1927 .suspend = gmc_v9_0_suspend, 1928 .resume = gmc_v9_0_resume, 1929 .is_idle = gmc_v9_0_is_idle, 1930 .wait_for_idle = gmc_v9_0_wait_for_idle, 1931 .soft_reset = gmc_v9_0_soft_reset, 1932 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 1933 .set_powergating_state = gmc_v9_0_set_powergating_state, 1934 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 1935 }; 1936 1937 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 1938 { 1939 .type = AMD_IP_BLOCK_TYPE_GMC, 1940 .major = 9, 1941 .minor = 0, 1942 .rev = 0, 1943 .funcs = &gmc_v9_0_ip_funcs, 1944 }; 1945