1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "umc_v12_0.h" 60 #include "hdp_v4_0.h" 61 #include "mca_v3_0.h" 62 63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 64 65 #include "amdgpu_ras.h" 66 #include "amdgpu_xgmi.h" 67 68 /* add these here since we already include dce12 headers and these are for DCN */ 69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 77 78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 80 81 #define MAX_MEM_RANGES 8 82 83 static const char * const gfxhub_client_ids[] = { 84 "CB", 85 "DB", 86 "IA", 87 "WD", 88 "CPF", 89 "CPC", 90 "CPG", 91 "RLC", 92 "TCP", 93 "SQC (inst)", 94 "SQC (data)", 95 "SQG", 96 "PA", 97 }; 98 99 static const char *mmhub_client_ids_raven[][2] = { 100 [0][0] = "MP1", 101 [1][0] = "MP0", 102 [2][0] = "VCN", 103 [3][0] = "VCNU", 104 [4][0] = "HDP", 105 [5][0] = "DCE", 106 [13][0] = "UTCL2", 107 [19][0] = "TLS", 108 [26][0] = "OSS", 109 [27][0] = "SDMA0", 110 [0][1] = "MP1", 111 [1][1] = "MP0", 112 [2][1] = "VCN", 113 [3][1] = "VCNU", 114 [4][1] = "HDP", 115 [5][1] = "XDP", 116 [6][1] = "DBGU0", 117 [7][1] = "DCE", 118 [8][1] = "DCEDWB0", 119 [9][1] = "DCEDWB1", 120 [26][1] = "OSS", 121 [27][1] = "SDMA0", 122 }; 123 124 static const char *mmhub_client_ids_renoir[][2] = { 125 [0][0] = "MP1", 126 [1][0] = "MP0", 127 [2][0] = "HDP", 128 [4][0] = "DCEDMC", 129 [5][0] = "DCEVGA", 130 [13][0] = "UTCL2", 131 [19][0] = "TLS", 132 [26][0] = "OSS", 133 [27][0] = "SDMA0", 134 [28][0] = "VCN", 135 [29][0] = "VCNU", 136 [30][0] = "JPEG", 137 [0][1] = "MP1", 138 [1][1] = "MP0", 139 [2][1] = "HDP", 140 [3][1] = "XDP", 141 [6][1] = "DBGU0", 142 [7][1] = "DCEDMC", 143 [8][1] = "DCEVGA", 144 [9][1] = "DCEDWB", 145 [26][1] = "OSS", 146 [27][1] = "SDMA0", 147 [28][1] = "VCN", 148 [29][1] = "VCNU", 149 [30][1] = "JPEG", 150 }; 151 152 static const char *mmhub_client_ids_vega10[][2] = { 153 [0][0] = "MP0", 154 [1][0] = "UVD", 155 [2][0] = "UVDU", 156 [3][0] = "HDP", 157 [13][0] = "UTCL2", 158 [14][0] = "OSS", 159 [15][0] = "SDMA1", 160 [32+0][0] = "VCE0", 161 [32+1][0] = "VCE0U", 162 [32+2][0] = "XDMA", 163 [32+3][0] = "DCE", 164 [32+4][0] = "MP1", 165 [32+14][0] = "SDMA0", 166 [0][1] = "MP0", 167 [1][1] = "UVD", 168 [2][1] = "UVDU", 169 [3][1] = "DBGU0", 170 [4][1] = "HDP", 171 [5][1] = "XDP", 172 [14][1] = "OSS", 173 [15][1] = "SDMA0", 174 [32+0][1] = "VCE0", 175 [32+1][1] = "VCE0U", 176 [32+2][1] = "XDMA", 177 [32+3][1] = "DCE", 178 [32+4][1] = "DCEDWB", 179 [32+5][1] = "MP1", 180 [32+6][1] = "DBGU1", 181 [32+14][1] = "SDMA1", 182 }; 183 184 static const char *mmhub_client_ids_vega12[][2] = { 185 [0][0] = "MP0", 186 [1][0] = "VCE0", 187 [2][0] = "VCE0U", 188 [3][0] = "HDP", 189 [13][0] = "UTCL2", 190 [14][0] = "OSS", 191 [15][0] = "SDMA1", 192 [32+0][0] = "DCE", 193 [32+1][0] = "XDMA", 194 [32+2][0] = "UVD", 195 [32+3][0] = "UVDU", 196 [32+4][0] = "MP1", 197 [32+15][0] = "SDMA0", 198 [0][1] = "MP0", 199 [1][1] = "VCE0", 200 [2][1] = "VCE0U", 201 [3][1] = "DBGU0", 202 [4][1] = "HDP", 203 [5][1] = "XDP", 204 [14][1] = "OSS", 205 [15][1] = "SDMA0", 206 [32+0][1] = "DCE", 207 [32+1][1] = "DCEDWB", 208 [32+2][1] = "XDMA", 209 [32+3][1] = "UVD", 210 [32+4][1] = "UVDU", 211 [32+5][1] = "MP1", 212 [32+6][1] = "DBGU1", 213 [32+15][1] = "SDMA1", 214 }; 215 216 static const char *mmhub_client_ids_vega20[][2] = { 217 [0][0] = "XDMA", 218 [1][0] = "DCE", 219 [2][0] = "VCE0", 220 [3][0] = "VCE0U", 221 [4][0] = "UVD", 222 [5][0] = "UVD1U", 223 [13][0] = "OSS", 224 [14][0] = "HDP", 225 [15][0] = "SDMA0", 226 [32+0][0] = "UVD", 227 [32+1][0] = "UVDU", 228 [32+2][0] = "MP1", 229 [32+3][0] = "MP0", 230 [32+12][0] = "UTCL2", 231 [32+14][0] = "SDMA1", 232 [0][1] = "XDMA", 233 [1][1] = "DCE", 234 [2][1] = "DCEDWB", 235 [3][1] = "VCE0", 236 [4][1] = "VCE0U", 237 [5][1] = "UVD1", 238 [6][1] = "UVD1U", 239 [7][1] = "DBGU0", 240 [8][1] = "XDP", 241 [13][1] = "OSS", 242 [14][1] = "HDP", 243 [15][1] = "SDMA0", 244 [32+0][1] = "UVD", 245 [32+1][1] = "UVDU", 246 [32+2][1] = "DBGU1", 247 [32+3][1] = "MP1", 248 [32+4][1] = "MP0", 249 [32+14][1] = "SDMA1", 250 }; 251 252 static const char *mmhub_client_ids_arcturus[][2] = { 253 [0][0] = "DBGU1", 254 [1][0] = "XDP", 255 [2][0] = "MP1", 256 [14][0] = "HDP", 257 [171][0] = "JPEG", 258 [172][0] = "VCN", 259 [173][0] = "VCNU", 260 [203][0] = "JPEG1", 261 [204][0] = "VCN1", 262 [205][0] = "VCN1U", 263 [256][0] = "SDMA0", 264 [257][0] = "SDMA1", 265 [258][0] = "SDMA2", 266 [259][0] = "SDMA3", 267 [260][0] = "SDMA4", 268 [261][0] = "SDMA5", 269 [262][0] = "SDMA6", 270 [263][0] = "SDMA7", 271 [384][0] = "OSS", 272 [0][1] = "DBGU1", 273 [1][1] = "XDP", 274 [2][1] = "MP1", 275 [14][1] = "HDP", 276 [171][1] = "JPEG", 277 [172][1] = "VCN", 278 [173][1] = "VCNU", 279 [203][1] = "JPEG1", 280 [204][1] = "VCN1", 281 [205][1] = "VCN1U", 282 [256][1] = "SDMA0", 283 [257][1] = "SDMA1", 284 [258][1] = "SDMA2", 285 [259][1] = "SDMA3", 286 [260][1] = "SDMA4", 287 [261][1] = "SDMA5", 288 [262][1] = "SDMA6", 289 [263][1] = "SDMA7", 290 [384][1] = "OSS", 291 }; 292 293 static const char *mmhub_client_ids_aldebaran[][2] = { 294 [2][0] = "MP1", 295 [3][0] = "MP0", 296 [32+1][0] = "DBGU_IO0", 297 [32+2][0] = "DBGU_IO2", 298 [32+4][0] = "MPIO", 299 [96+11][0] = "JPEG0", 300 [96+12][0] = "VCN0", 301 [96+13][0] = "VCNU0", 302 [128+11][0] = "JPEG1", 303 [128+12][0] = "VCN1", 304 [128+13][0] = "VCNU1", 305 [160+1][0] = "XDP", 306 [160+14][0] = "HDP", 307 [256+0][0] = "SDMA0", 308 [256+1][0] = "SDMA1", 309 [256+2][0] = "SDMA2", 310 [256+3][0] = "SDMA3", 311 [256+4][0] = "SDMA4", 312 [384+0][0] = "OSS", 313 [2][1] = "MP1", 314 [3][1] = "MP0", 315 [32+1][1] = "DBGU_IO0", 316 [32+2][1] = "DBGU_IO2", 317 [32+4][1] = "MPIO", 318 [96+11][1] = "JPEG0", 319 [96+12][1] = "VCN0", 320 [96+13][1] = "VCNU0", 321 [128+11][1] = "JPEG1", 322 [128+12][1] = "VCN1", 323 [128+13][1] = "VCNU1", 324 [160+1][1] = "XDP", 325 [160+14][1] = "HDP", 326 [256+0][1] = "SDMA0", 327 [256+1][1] = "SDMA1", 328 [256+2][1] = "SDMA2", 329 [256+3][1] = "SDMA3", 330 [256+4][1] = "SDMA4", 331 [384+0][1] = "OSS", 332 }; 333 334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { 335 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 336 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 337 }; 338 339 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { 340 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 341 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 342 }; 343 344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 345 (0x000143c0 + 0x00000000), 346 (0x000143c0 + 0x00000800), 347 (0x000143c0 + 0x00001000), 348 (0x000143c0 + 0x00001800), 349 (0x000543c0 + 0x00000000), 350 (0x000543c0 + 0x00000800), 351 (0x000543c0 + 0x00001000), 352 (0x000543c0 + 0x00001800), 353 (0x000943c0 + 0x00000000), 354 (0x000943c0 + 0x00000800), 355 (0x000943c0 + 0x00001000), 356 (0x000943c0 + 0x00001800), 357 (0x000d43c0 + 0x00000000), 358 (0x000d43c0 + 0x00000800), 359 (0x000d43c0 + 0x00001000), 360 (0x000d43c0 + 0x00001800), 361 (0x001143c0 + 0x00000000), 362 (0x001143c0 + 0x00000800), 363 (0x001143c0 + 0x00001000), 364 (0x001143c0 + 0x00001800), 365 (0x001543c0 + 0x00000000), 366 (0x001543c0 + 0x00000800), 367 (0x001543c0 + 0x00001000), 368 (0x001543c0 + 0x00001800), 369 (0x001943c0 + 0x00000000), 370 (0x001943c0 + 0x00000800), 371 (0x001943c0 + 0x00001000), 372 (0x001943c0 + 0x00001800), 373 (0x001d43c0 + 0x00000000), 374 (0x001d43c0 + 0x00000800), 375 (0x001d43c0 + 0x00001000), 376 (0x001d43c0 + 0x00001800), 377 }; 378 379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 380 (0x000143e0 + 0x00000000), 381 (0x000143e0 + 0x00000800), 382 (0x000143e0 + 0x00001000), 383 (0x000143e0 + 0x00001800), 384 (0x000543e0 + 0x00000000), 385 (0x000543e0 + 0x00000800), 386 (0x000543e0 + 0x00001000), 387 (0x000543e0 + 0x00001800), 388 (0x000943e0 + 0x00000000), 389 (0x000943e0 + 0x00000800), 390 (0x000943e0 + 0x00001000), 391 (0x000943e0 + 0x00001800), 392 (0x000d43e0 + 0x00000000), 393 (0x000d43e0 + 0x00000800), 394 (0x000d43e0 + 0x00001000), 395 (0x000d43e0 + 0x00001800), 396 (0x001143e0 + 0x00000000), 397 (0x001143e0 + 0x00000800), 398 (0x001143e0 + 0x00001000), 399 (0x001143e0 + 0x00001800), 400 (0x001543e0 + 0x00000000), 401 (0x001543e0 + 0x00000800), 402 (0x001543e0 + 0x00001000), 403 (0x001543e0 + 0x00001800), 404 (0x001943e0 + 0x00000000), 405 (0x001943e0 + 0x00000800), 406 (0x001943e0 + 0x00001000), 407 (0x001943e0 + 0x00001800), 408 (0x001d43e0 + 0x00000000), 409 (0x001d43e0 + 0x00000800), 410 (0x001d43e0 + 0x00001000), 411 (0x001d43e0 + 0x00001800), 412 }; 413 414 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 415 struct amdgpu_irq_src *src, 416 unsigned int type, 417 enum amdgpu_interrupt_state state) 418 { 419 u32 bits, i, tmp, reg; 420 421 /* Devices newer then VEGA10/12 shall have these programming 422 * sequences performed by PSP BL 423 */ 424 if (adev->asic_type >= CHIP_VEGA20) 425 return 0; 426 427 bits = 0x7f; 428 429 switch (state) { 430 case AMDGPU_IRQ_STATE_DISABLE: 431 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 432 reg = ecc_umc_mcumc_ctrl_addrs[i]; 433 tmp = RREG32(reg); 434 tmp &= ~bits; 435 WREG32(reg, tmp); 436 } 437 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 438 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 439 tmp = RREG32(reg); 440 tmp &= ~bits; 441 WREG32(reg, tmp); 442 } 443 break; 444 case AMDGPU_IRQ_STATE_ENABLE: 445 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 446 reg = ecc_umc_mcumc_ctrl_addrs[i]; 447 tmp = RREG32(reg); 448 tmp |= bits; 449 WREG32(reg, tmp); 450 } 451 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 452 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 453 tmp = RREG32(reg); 454 tmp |= bits; 455 WREG32(reg, tmp); 456 } 457 break; 458 default: 459 break; 460 } 461 462 return 0; 463 } 464 465 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 466 struct amdgpu_irq_src *src, 467 unsigned int type, 468 enum amdgpu_interrupt_state state) 469 { 470 struct amdgpu_vmhub *hub; 471 u32 tmp, reg, bits, i, j; 472 473 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 479 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 480 481 switch (state) { 482 case AMDGPU_IRQ_STATE_DISABLE: 483 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 484 hub = &adev->vmhub[j]; 485 for (i = 0; i < 16; i++) { 486 reg = hub->vm_context0_cntl + i; 487 488 /* This works because this interrupt is only 489 * enabled at init/resume and disabled in 490 * fini/suspend, so the overall state doesn't 491 * change over the course of suspend/resume. 492 */ 493 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 494 continue; 495 496 if (j >= AMDGPU_MMHUB0(0)) 497 tmp = RREG32_SOC15_IP(MMHUB, reg); 498 else 499 tmp = RREG32_XCC(reg, j); 500 501 tmp &= ~bits; 502 503 if (j >= AMDGPU_MMHUB0(0)) 504 WREG32_SOC15_IP(MMHUB, reg, tmp); 505 else 506 WREG32_XCC(reg, tmp, j); 507 } 508 } 509 break; 510 case AMDGPU_IRQ_STATE_ENABLE: 511 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 512 hub = &adev->vmhub[j]; 513 for (i = 0; i < 16; i++) { 514 reg = hub->vm_context0_cntl + i; 515 516 /* This works because this interrupt is only 517 * enabled at init/resume and disabled in 518 * fini/suspend, so the overall state doesn't 519 * change over the course of suspend/resume. 520 */ 521 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 522 continue; 523 524 if (j >= AMDGPU_MMHUB0(0)) 525 tmp = RREG32_SOC15_IP(MMHUB, reg); 526 else 527 tmp = RREG32_XCC(reg, j); 528 529 tmp |= bits; 530 531 if (j >= AMDGPU_MMHUB0(0)) 532 WREG32_SOC15_IP(MMHUB, reg, tmp); 533 else 534 WREG32_XCC(reg, tmp, j); 535 } 536 } 537 break; 538 default: 539 break; 540 } 541 542 return 0; 543 } 544 545 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 546 struct amdgpu_irq_src *source, 547 struct amdgpu_iv_entry *entry) 548 { 549 bool retry_fault = !!(entry->src_data[1] & 0x80); 550 bool write_fault = !!(entry->src_data[1] & 0x20); 551 uint32_t status = 0, cid = 0, rw = 0, fed = 0; 552 struct amdgpu_task_info *task_info; 553 struct amdgpu_vmhub *hub; 554 const char *mmhub_cid; 555 const char *hub_name; 556 unsigned int vmhub; 557 u64 addr; 558 uint32_t cam_index = 0; 559 int ret, xcc_id = 0; 560 uint32_t node_id; 561 562 node_id = entry->node_id; 563 564 addr = (u64)entry->src_data[0] << 12; 565 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 566 567 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 568 hub_name = "mmhub0"; 569 vmhub = AMDGPU_MMHUB0(node_id / 4); 570 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 571 hub_name = "mmhub1"; 572 vmhub = AMDGPU_MMHUB1(0); 573 } else { 574 hub_name = "gfxhub0"; 575 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 577 node_id); 578 if (xcc_id < 0) 579 xcc_id = 0; 580 } 581 vmhub = xcc_id; 582 } 583 hub = &adev->vmhub[vmhub]; 584 585 if (retry_fault) { 586 if (adev->irq.retry_cam_enabled) { 587 /* Delegate it to a different ring if the hardware hasn't 588 * already done it. 589 */ 590 if (entry->ih == &adev->irq.ih) { 591 amdgpu_irq_delegate(adev, entry, 8); 592 return 1; 593 } 594 595 cam_index = entry->src_data[2] & 0x3ff; 596 597 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 598 addr, entry->timestamp, write_fault); 599 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 600 if (ret) 601 return 1; 602 } else { 603 /* Process it onyl if it's the first fault for this address */ 604 if (entry->ih != &adev->irq.ih_soft && 605 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 606 entry->timestamp)) 607 return 1; 608 609 /* Delegate it to a different ring if the hardware hasn't 610 * already done it. 611 */ 612 if (entry->ih == &adev->irq.ih) { 613 amdgpu_irq_delegate(adev, entry, 8); 614 return 1; 615 } 616 617 /* Try to handle the recoverable page faults by filling page 618 * tables 619 */ 620 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 621 addr, entry->timestamp, write_fault)) 622 return 1; 623 } 624 } 625 626 if (!printk_ratelimit()) 627 return 0; 628 629 dev_err(adev->dev, 630 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name, 631 retry_fault ? "retry" : "no-retry", 632 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 633 634 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 635 if (task_info) { 636 dev_err(adev->dev, 637 " for process %s pid %d thread %s pid %d)\n", 638 task_info->process_name, task_info->tgid, 639 task_info->task_name, task_info->pid); 640 amdgpu_vm_put_task_info(task_info); 641 } 642 643 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 644 addr, entry->client_id, 645 soc15_ih_clientid_name[entry->client_id]); 646 647 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 648 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 649 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 650 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 651 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 652 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 653 654 if (amdgpu_sriov_vf(adev)) 655 return 0; 656 657 /* 658 * Issue a dummy read to wait for the status register to 659 * be updated to avoid reading an incorrect value due to 660 * the new fast GRBM interface. 661 */ 662 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 663 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 664 RREG32(hub->vm_l2_pro_fault_status); 665 666 status = RREG32(hub->vm_l2_pro_fault_status); 667 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 668 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 669 fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED); 670 671 /* for fed error, kfd will handle it, return directly */ 672 if (fed && amdgpu_ras_is_poison_mode_supported(adev) && 673 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2))) 674 return 0; 675 676 /* Only print L2 fault status if the status register could be read and 677 * contains useful information 678 */ 679 if (!status) 680 return 0; 681 682 if (!amdgpu_sriov_vf(adev)) 683 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 684 685 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub); 686 687 dev_err(adev->dev, 688 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 689 status); 690 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 691 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 692 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 693 gfxhub_client_ids[cid], 694 cid); 695 } else { 696 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 697 case IP_VERSION(9, 0, 0): 698 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 699 break; 700 case IP_VERSION(9, 3, 0): 701 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 702 break; 703 case IP_VERSION(9, 4, 0): 704 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 705 break; 706 case IP_VERSION(9, 4, 1): 707 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 708 break; 709 case IP_VERSION(9, 1, 0): 710 case IP_VERSION(9, 2, 0): 711 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 712 break; 713 case IP_VERSION(1, 5, 0): 714 case IP_VERSION(2, 4, 0): 715 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 716 break; 717 case IP_VERSION(1, 8, 0): 718 case IP_VERSION(9, 4, 2): 719 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 720 break; 721 default: 722 mmhub_cid = NULL; 723 break; 724 } 725 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 726 mmhub_cid ? mmhub_cid : "unknown", cid); 727 } 728 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 729 REG_GET_FIELD(status, 730 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 731 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 732 REG_GET_FIELD(status, 733 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 734 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 735 REG_GET_FIELD(status, 736 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 737 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 738 REG_GET_FIELD(status, 739 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 740 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 741 return 0; 742 } 743 744 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 745 .set = gmc_v9_0_vm_fault_interrupt_state, 746 .process = gmc_v9_0_process_interrupt, 747 }; 748 749 750 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 751 .set = gmc_v9_0_ecc_interrupt_state, 752 .process = amdgpu_umc_process_ecc_irq, 753 }; 754 755 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 756 { 757 adev->gmc.vm_fault.num_types = 1; 758 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 759 760 if (!amdgpu_sriov_vf(adev) && 761 !adev->gmc.xgmi.connected_to_cpu && 762 !adev->gmc.is_app_apu) { 763 adev->gmc.ecc_irq.num_types = 1; 764 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 765 } 766 } 767 768 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 769 uint32_t flush_type) 770 { 771 u32 req = 0; 772 773 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 774 PER_VMID_INVALIDATE_REQ, 1 << vmid); 775 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 776 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 777 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 778 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 779 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 780 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 781 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 782 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 783 784 return req; 785 } 786 787 /** 788 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 789 * 790 * @adev: amdgpu_device pointer 791 * @vmhub: vmhub type 792 * 793 */ 794 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 795 uint32_t vmhub) 796 { 797 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 798 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 799 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 800 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 801 return false; 802 803 return ((vmhub == AMDGPU_MMHUB0(0) || 804 vmhub == AMDGPU_MMHUB1(0)) && 805 (!amdgpu_sriov_vf(adev)) && 806 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 807 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 808 } 809 810 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 811 uint8_t vmid, uint16_t *p_pasid) 812 { 813 uint32_t value; 814 815 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 816 + vmid); 817 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 818 819 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 820 } 821 822 /* 823 * GART 824 * VMID 0 is the physical GPU addresses as used by the kernel. 825 * VMIDs 1-15 are used for userspace clients and are handled 826 * by the amdgpu vm/hsa code. 827 */ 828 829 /** 830 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 831 * 832 * @adev: amdgpu_device pointer 833 * @vmid: vm instance to flush 834 * @vmhub: which hub to flush 835 * @flush_type: the flush type 836 * 837 * Flush the TLB for the requested page table using certain type. 838 */ 839 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 840 uint32_t vmhub, uint32_t flush_type) 841 { 842 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 843 u32 j, inv_req, tmp, sem, req, ack, inst; 844 const unsigned int eng = 17; 845 struct amdgpu_vmhub *hub; 846 847 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 848 849 hub = &adev->vmhub[vmhub]; 850 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 851 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 852 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 853 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 854 855 if (vmhub >= AMDGPU_MMHUB0(0)) 856 inst = 0; 857 else 858 inst = vmhub; 859 860 /* This is necessary for SRIOV as well as for GFXOFF to function 861 * properly under bare metal 862 */ 863 if (adev->gfx.kiq[inst].ring.sched.ready && 864 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 865 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 866 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 867 868 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 869 1 << vmid, inst); 870 return; 871 } 872 873 /* This path is needed before KIQ/MES/GFXOFF are set up */ 874 spin_lock(&adev->gmc.invalidate_lock); 875 876 /* 877 * It may lose gpuvm invalidate acknowldege state across power-gating 878 * off cycle, add semaphore acquire before invalidation and semaphore 879 * release after invalidation to avoid entering power gated state 880 * to WA the Issue 881 */ 882 883 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 884 if (use_semaphore) { 885 for (j = 0; j < adev->usec_timeout; j++) { 886 /* a read return value of 1 means semaphore acquire */ 887 if (vmhub >= AMDGPU_MMHUB0(0)) 888 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst)); 889 else 890 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst)); 891 if (tmp & 0x1) 892 break; 893 udelay(1); 894 } 895 896 if (j >= adev->usec_timeout) 897 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 898 } 899 900 if (vmhub >= AMDGPU_MMHUB0(0)) 901 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst)); 902 else 903 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst)); 904 905 /* 906 * Issue a dummy read to wait for the ACK register to 907 * be cleared to avoid a false ACK due to the new fast 908 * GRBM interface. 909 */ 910 if ((vmhub == AMDGPU_GFXHUB(0)) && 911 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 912 RREG32_NO_KIQ(req); 913 914 for (j = 0; j < adev->usec_timeout; j++) { 915 if (vmhub >= AMDGPU_MMHUB0(0)) 916 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst)); 917 else 918 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst)); 919 if (tmp & (1 << vmid)) 920 break; 921 udelay(1); 922 } 923 924 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 925 if (use_semaphore) { 926 /* 927 * add semaphore release after invalidation, 928 * write with 0 means semaphore release 929 */ 930 if (vmhub >= AMDGPU_MMHUB0(0)) 931 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst)); 932 else 933 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst)); 934 } 935 936 spin_unlock(&adev->gmc.invalidate_lock); 937 938 if (j < adev->usec_timeout) 939 return; 940 941 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 942 } 943 944 /** 945 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 946 * 947 * @adev: amdgpu_device pointer 948 * @pasid: pasid to be flush 949 * @flush_type: the flush type 950 * @all_hub: flush all hubs 951 * @inst: is used to select which instance of KIQ to use for the invalidation 952 * 953 * Flush the TLB for the requested pasid. 954 */ 955 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 956 uint16_t pasid, uint32_t flush_type, 957 bool all_hub, uint32_t inst) 958 { 959 uint16_t queried; 960 int i, vmid; 961 962 for (vmid = 1; vmid < 16; vmid++) { 963 bool valid; 964 965 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 966 &queried); 967 if (!valid || queried != pasid) 968 continue; 969 970 if (all_hub) { 971 for_each_set_bit(i, adev->vmhubs_mask, 972 AMDGPU_MAX_VMHUBS) 973 gmc_v9_0_flush_gpu_tlb(adev, vmid, i, 974 flush_type); 975 } else { 976 gmc_v9_0_flush_gpu_tlb(adev, vmid, 977 AMDGPU_GFXHUB(0), 978 flush_type); 979 } 980 } 981 } 982 983 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 984 unsigned int vmid, uint64_t pd_addr) 985 { 986 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 987 struct amdgpu_device *adev = ring->adev; 988 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 989 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 990 unsigned int eng = ring->vm_inv_eng; 991 992 /* 993 * It may lose gpuvm invalidate acknowldege state across power-gating 994 * off cycle, add semaphore acquire before invalidation and semaphore 995 * release after invalidation to avoid entering power gated state 996 * to WA the Issue 997 */ 998 999 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1000 if (use_semaphore) 1001 /* a read return value of 1 means semaphore acuqire */ 1002 amdgpu_ring_emit_reg_wait(ring, 1003 hub->vm_inv_eng0_sem + 1004 hub->eng_distance * eng, 0x1, 0x1); 1005 1006 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1007 (hub->ctx_addr_distance * vmid), 1008 lower_32_bits(pd_addr)); 1009 1010 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1011 (hub->ctx_addr_distance * vmid), 1012 upper_32_bits(pd_addr)); 1013 1014 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 1015 hub->eng_distance * eng, 1016 hub->vm_inv_eng0_ack + 1017 hub->eng_distance * eng, 1018 req, 1 << vmid); 1019 1020 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1021 if (use_semaphore) 1022 /* 1023 * add semaphore release after invalidation, 1024 * write with 0 means semaphore release 1025 */ 1026 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1027 hub->eng_distance * eng, 0); 1028 1029 return pd_addr; 1030 } 1031 1032 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 1033 unsigned int pasid) 1034 { 1035 struct amdgpu_device *adev = ring->adev; 1036 uint32_t reg; 1037 1038 /* Do nothing because there's no lut register for mmhub1. */ 1039 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 1040 return; 1041 1042 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 1043 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1044 else 1045 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1046 1047 amdgpu_ring_emit_wreg(ring, reg, pasid); 1048 } 1049 1050 /* 1051 * PTE format on VEGA 10: 1052 * 63:59 reserved 1053 * 58:57 mtype 1054 * 56 F 1055 * 55 L 1056 * 54 P 1057 * 53 SW 1058 * 52 T 1059 * 50:48 reserved 1060 * 47:12 4k physical page base address 1061 * 11:7 fragment 1062 * 6 write 1063 * 5 read 1064 * 4 exe 1065 * 3 Z 1066 * 2 snooped 1067 * 1 system 1068 * 0 valid 1069 * 1070 * PDE format on VEGA 10: 1071 * 63:59 block fragment size 1072 * 58:55 reserved 1073 * 54 P 1074 * 53:48 reserved 1075 * 47:6 physical base address of PD or PTE 1076 * 5:3 reserved 1077 * 2 C 1078 * 1 system 1079 * 0 valid 1080 */ 1081 1082 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1083 1084 { 1085 switch (flags) { 1086 case AMDGPU_VM_MTYPE_DEFAULT: 1087 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1088 case AMDGPU_VM_MTYPE_NC: 1089 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1090 case AMDGPU_VM_MTYPE_WC: 1091 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_WC); 1092 case AMDGPU_VM_MTYPE_RW: 1093 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_RW); 1094 case AMDGPU_VM_MTYPE_CC: 1095 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_CC); 1096 case AMDGPU_VM_MTYPE_UC: 1097 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC); 1098 default: 1099 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1100 } 1101 } 1102 1103 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1104 uint64_t *addr, uint64_t *flags) 1105 { 1106 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1107 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1108 BUG_ON(*addr & 0xFFFF00000000003FULL); 1109 1110 if (!adev->gmc.translate_further) 1111 return; 1112 1113 if (level == AMDGPU_VM_PDB1) { 1114 /* Set the block fragment size */ 1115 if (!(*flags & AMDGPU_PDE_PTE)) 1116 *flags |= AMDGPU_PDE_BFS(0x9); 1117 1118 } else if (level == AMDGPU_VM_PDB0) { 1119 if (*flags & AMDGPU_PDE_PTE) { 1120 *flags &= ~AMDGPU_PDE_PTE; 1121 if (!(*flags & AMDGPU_PTE_VALID)) 1122 *addr |= 1 << PAGE_SHIFT; 1123 } else { 1124 *flags |= AMDGPU_PTE_TF; 1125 } 1126 } 1127 } 1128 1129 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1130 struct amdgpu_bo *bo, 1131 struct amdgpu_bo_va_mapping *mapping, 1132 uint64_t *flags) 1133 { 1134 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1135 bool is_vram = bo->tbo.resource && 1136 bo->tbo.resource->mem_type == TTM_PL_VRAM; 1137 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 1138 AMDGPU_GEM_CREATE_EXT_COHERENT); 1139 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; 1140 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1141 struct amdgpu_vm *vm = mapping->bo_va->base.vm; 1142 unsigned int mtype_local, mtype; 1143 uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); 1144 bool snoop = false; 1145 bool is_local; 1146 1147 dma_resv_assert_held(bo->tbo.base.resv); 1148 1149 switch (gc_ip_version) { 1150 case IP_VERSION(9, 4, 1): 1151 case IP_VERSION(9, 4, 2): 1152 if (is_vram) { 1153 if (bo_adev == adev) { 1154 if (uncached) 1155 mtype = MTYPE_UC; 1156 else if (coherent) 1157 mtype = MTYPE_CC; 1158 else 1159 mtype = MTYPE_RW; 1160 /* FIXME: is this still needed? Or does 1161 * amdgpu_ttm_tt_pde_flags already handle this? 1162 */ 1163 if (gc_ip_version == IP_VERSION(9, 4, 2) && 1164 adev->gmc.xgmi.connected_to_cpu) 1165 snoop = true; 1166 } else { 1167 if (uncached || coherent) 1168 mtype = MTYPE_UC; 1169 else 1170 mtype = MTYPE_NC; 1171 if (mapping->bo_va->is_xgmi) 1172 snoop = true; 1173 } 1174 } else { 1175 if (uncached || coherent) 1176 mtype = MTYPE_UC; 1177 else 1178 mtype = MTYPE_NC; 1179 /* FIXME: is this still needed? Or does 1180 * amdgpu_ttm_tt_pde_flags already handle this? 1181 */ 1182 snoop = true; 1183 } 1184 break; 1185 case IP_VERSION(9, 4, 3): 1186 case IP_VERSION(9, 4, 4): 1187 case IP_VERSION(9, 5, 0): 1188 /* Only local VRAM BOs or system memory on non-NUMA APUs 1189 * can be assumed to be local in their entirety. Choose 1190 * MTYPE_NC as safe fallback for all system memory BOs on 1191 * NUMA systems. Their MTYPE can be overridden per-page in 1192 * gmc_v9_0_override_vm_pte_flags. 1193 */ 1194 mtype_local = MTYPE_RW; 1195 if (amdgpu_mtype_local == 1) { 1196 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); 1197 mtype_local = MTYPE_NC; 1198 } else if (amdgpu_mtype_local == 2) { 1199 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n"); 1200 mtype_local = MTYPE_CC; 1201 } else { 1202 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); 1203 } 1204 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1205 num_possible_nodes() <= 1) || 1206 (is_vram && adev == bo_adev && 1207 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id); 1208 snoop = true; 1209 if (uncached) { 1210 mtype = MTYPE_UC; 1211 } else if (ext_coherent) { 1212 if (gc_ip_version == IP_VERSION(9, 5, 0) || adev->rev_id) 1213 mtype = is_local ? MTYPE_CC : MTYPE_UC; 1214 else 1215 mtype = MTYPE_UC; 1216 } else if (adev->flags & AMD_IS_APU) { 1217 mtype = is_local ? mtype_local : MTYPE_NC; 1218 } else { 1219 /* dGPU */ 1220 if (is_local) 1221 mtype = mtype_local; 1222 else if (gc_ip_version < IP_VERSION(9, 5, 0) && !is_vram) 1223 mtype = MTYPE_UC; 1224 else 1225 mtype = MTYPE_NC; 1226 } 1227 1228 break; 1229 default: 1230 if (uncached || coherent) 1231 mtype = MTYPE_UC; 1232 else 1233 mtype = MTYPE_NC; 1234 1235 /* FIXME: is this still needed? Or does 1236 * amdgpu_ttm_tt_pde_flags already handle this? 1237 */ 1238 if (!is_vram) 1239 snoop = true; 1240 } 1241 1242 if (mtype != MTYPE_NC) 1243 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype); 1244 1245 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1246 } 1247 1248 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1249 struct amdgpu_bo_va_mapping *mapping, 1250 uint64_t *flags) 1251 { 1252 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1253 1254 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1255 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1256 1257 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1258 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1259 1260 if (mapping->flags & AMDGPU_PTE_PRT) { 1261 *flags |= AMDGPU_PTE_PRT; 1262 *flags &= ~AMDGPU_PTE_VALID; 1263 } 1264 1265 if ((*flags & AMDGPU_PTE_VALID) && bo) 1266 gmc_v9_0_get_coherence_flags(adev, bo, mapping, flags); 1267 } 1268 1269 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1270 struct amdgpu_vm *vm, 1271 uint64_t addr, uint64_t *flags) 1272 { 1273 int local_node, nid; 1274 1275 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system 1276 * memory can use more efficient MTYPEs. 1277 */ 1278 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3) && 1279 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) && 1280 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 5, 0)) 1281 return; 1282 1283 /* Only direct-mapped memory allows us to determine the NUMA node from 1284 * the DMA address. 1285 */ 1286 if (!adev->ram_is_direct_mapped) { 1287 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n"); 1288 return; 1289 } 1290 1291 /* MTYPE_NC is the same default and can be overridden. 1292 * MTYPE_UC will be present if the memory is extended-coherent 1293 * and can also be overridden. 1294 */ 1295 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1296 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC) && 1297 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1298 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC)) { 1299 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n"); 1300 return; 1301 } 1302 1303 /* FIXME: Only supported on native mode for now. For carve-out, the 1304 * NUMA affinity of the GPU/VM needs to come from the PCI info because 1305 * memory partitions are not associated with different NUMA nodes. 1306 */ 1307 if (adev->gmc.is_app_apu && vm->mem_id >= 0) { 1308 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1309 } else { 1310 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n"); 1311 return; 1312 } 1313 1314 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1315 * page or NUMA nodes. 1316 */ 1317 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1318 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n"); 1319 return; 1320 } 1321 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1322 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1323 vm->mem_id, local_node, nid); 1324 if (nid == local_node) { 1325 uint64_t old_flags = *flags; 1326 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) == 1327 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC)) { 1328 unsigned int mtype_local = MTYPE_RW; 1329 1330 if (amdgpu_mtype_local == 1) 1331 mtype_local = MTYPE_NC; 1332 else if (amdgpu_mtype_local == 2) 1333 mtype_local = MTYPE_CC; 1334 1335 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype_local); 1336 } else if (adev->rev_id) { 1337 /* MTYPE_UC case */ 1338 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC); 1339 } 1340 1341 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n", 1342 old_flags, *flags); 1343 } 1344 } 1345 1346 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1347 { 1348 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1349 unsigned int size; 1350 1351 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1352 1353 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1354 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1355 } else { 1356 u32 viewport; 1357 1358 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1359 case IP_VERSION(1, 0, 0): 1360 case IP_VERSION(1, 0, 1): 1361 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1362 size = (REG_GET_FIELD(viewport, 1363 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1364 REG_GET_FIELD(viewport, 1365 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1366 4); 1367 break; 1368 case IP_VERSION(2, 1, 0): 1369 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1370 size = (REG_GET_FIELD(viewport, 1371 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1372 REG_GET_FIELD(viewport, 1373 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1374 4); 1375 break; 1376 default: 1377 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1378 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1379 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1380 4); 1381 break; 1382 } 1383 } 1384 1385 return size; 1386 } 1387 1388 static enum amdgpu_memory_partition 1389 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes) 1390 { 1391 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE; 1392 1393 if (adev->nbio.funcs->get_memory_partition_mode) 1394 mode = adev->nbio.funcs->get_memory_partition_mode(adev, 1395 supp_modes); 1396 1397 return mode; 1398 } 1399 1400 static enum amdgpu_memory_partition 1401 gmc_v9_0_query_vf_memory_partition(struct amdgpu_device *adev) 1402 { 1403 switch (adev->gmc.num_mem_partitions) { 1404 case 0: 1405 return UNKNOWN_MEMORY_PARTITION_MODE; 1406 case 1: 1407 return AMDGPU_NPS1_PARTITION_MODE; 1408 case 2: 1409 return AMDGPU_NPS2_PARTITION_MODE; 1410 case 4: 1411 return AMDGPU_NPS4_PARTITION_MODE; 1412 default: 1413 return AMDGPU_NPS1_PARTITION_MODE; 1414 } 1415 1416 return AMDGPU_NPS1_PARTITION_MODE; 1417 } 1418 1419 static enum amdgpu_memory_partition 1420 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev) 1421 { 1422 if (amdgpu_sriov_vf(adev)) 1423 return gmc_v9_0_query_vf_memory_partition(adev); 1424 1425 return gmc_v9_0_get_memory_partition(adev, NULL); 1426 } 1427 1428 static bool gmc_v9_0_need_reset_on_init(struct amdgpu_device *adev) 1429 { 1430 if (adev->nbio.funcs && adev->nbio.funcs->is_nps_switch_requested && 1431 adev->nbio.funcs->is_nps_switch_requested(adev)) { 1432 adev->gmc.reset_flags |= AMDGPU_GMC_INIT_RESET_NPS; 1433 return true; 1434 } 1435 1436 return false; 1437 } 1438 1439 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1440 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1441 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1442 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1443 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1444 .map_mtype = gmc_v9_0_map_mtype, 1445 .get_vm_pde = gmc_v9_0_get_vm_pde, 1446 .get_vm_pte = gmc_v9_0_get_vm_pte, 1447 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1448 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1449 .query_mem_partition_mode = &gmc_v9_0_query_memory_partition, 1450 .request_mem_partition_mode = &amdgpu_gmc_request_memory_partition, 1451 .need_reset_on_init = &gmc_v9_0_need_reset_on_init, 1452 }; 1453 1454 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1455 { 1456 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1457 } 1458 1459 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1460 { 1461 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1462 case IP_VERSION(6, 0, 0): 1463 adev->umc.funcs = &umc_v6_0_funcs; 1464 break; 1465 case IP_VERSION(6, 1, 1): 1466 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1467 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1468 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1469 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1470 adev->umc.retire_unit = 1; 1471 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1472 adev->umc.ras = &umc_v6_1_ras; 1473 break; 1474 case IP_VERSION(6, 1, 2): 1475 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1476 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1477 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1478 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1479 adev->umc.retire_unit = 1; 1480 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1481 adev->umc.ras = &umc_v6_1_ras; 1482 break; 1483 case IP_VERSION(6, 7, 0): 1484 adev->umc.max_ras_err_cnt_per_query = 1485 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1486 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1487 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1488 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1489 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1490 if (!adev->gmc.xgmi.connected_to_cpu) 1491 adev->umc.ras = &umc_v6_7_ras; 1492 if (1 & adev->smuio.funcs->get_die_id(adev)) 1493 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1494 else 1495 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1496 break; 1497 case IP_VERSION(12, 0, 0): 1498 adev->umc.max_ras_err_cnt_per_query = 1499 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1500 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM; 1501 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM; 1502 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM; 1503 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET; 1504 adev->umc.active_mask = adev->aid_mask; 1505 adev->umc.retire_unit = UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1506 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1507 adev->umc.ras = &umc_v12_0_ras; 1508 break; 1509 default: 1510 break; 1511 } 1512 } 1513 1514 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1515 { 1516 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1517 case IP_VERSION(9, 4, 1): 1518 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1519 break; 1520 case IP_VERSION(9, 4, 2): 1521 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1522 break; 1523 case IP_VERSION(1, 8, 0): 1524 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1525 break; 1526 default: 1527 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1528 break; 1529 } 1530 } 1531 1532 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1533 { 1534 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1535 case IP_VERSION(9, 4, 0): 1536 adev->mmhub.ras = &mmhub_v1_0_ras; 1537 break; 1538 case IP_VERSION(9, 4, 1): 1539 adev->mmhub.ras = &mmhub_v9_4_ras; 1540 break; 1541 case IP_VERSION(9, 4, 2): 1542 adev->mmhub.ras = &mmhub_v1_7_ras; 1543 break; 1544 case IP_VERSION(1, 8, 0): 1545 case IP_VERSION(1, 8, 1): 1546 adev->mmhub.ras = &mmhub_v1_8_ras; 1547 break; 1548 default: 1549 /* mmhub ras is not available */ 1550 break; 1551 } 1552 } 1553 1554 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1555 { 1556 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1557 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 1558 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 1559 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1560 else 1561 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1562 } 1563 1564 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1565 { 1566 adev->hdp.ras = &hdp_v4_0_ras; 1567 } 1568 1569 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1570 { 1571 struct amdgpu_mca *mca = &adev->mca; 1572 1573 /* is UMC the right IP to check for MCA? Maybe DF? */ 1574 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1575 case IP_VERSION(6, 7, 0): 1576 if (!adev->gmc.xgmi.connected_to_cpu) { 1577 mca->mp0.ras = &mca_v3_0_mp0_ras; 1578 mca->mp1.ras = &mca_v3_0_mp1_ras; 1579 mca->mpio.ras = &mca_v3_0_mpio_ras; 1580 } 1581 break; 1582 default: 1583 break; 1584 } 1585 } 1586 1587 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1588 { 1589 if (!adev->gmc.xgmi.connected_to_cpu) 1590 adev->gmc.xgmi.ras = &xgmi_ras; 1591 } 1592 1593 static void gmc_v9_0_init_nps_details(struct amdgpu_device *adev) 1594 { 1595 adev->gmc.supported_nps_modes = 0; 1596 1597 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 1598 return; 1599 1600 /*TODO: Check PSP version also which supports NPS switch. Otherwise keep 1601 * supported modes as 0. 1602 */ 1603 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1604 case IP_VERSION(9, 4, 3): 1605 case IP_VERSION(9, 4, 4): 1606 adev->gmc.supported_nps_modes = 1607 BIT(AMDGPU_NPS1_PARTITION_MODE) | 1608 BIT(AMDGPU_NPS4_PARTITION_MODE); 1609 break; 1610 default: 1611 break; 1612 } 1613 } 1614 1615 static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block) 1616 { 1617 struct amdgpu_device *adev = ip_block->adev; 1618 1619 /* 1620 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1621 * in their IP discovery tables 1622 */ 1623 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) || 1624 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 1625 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1626 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 1627 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 1628 adev->gmc.xgmi.supported = true; 1629 1630 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) { 1631 adev->gmc.xgmi.supported = true; 1632 adev->gmc.xgmi.connected_to_cpu = 1633 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1634 } 1635 1636 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1637 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { 1638 enum amdgpu_pkg_type pkg_type = 1639 adev->smuio.funcs->get_pkg_type(adev); 1640 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1641 * and the APU, can be in used two possible modes: 1642 * - carveout mode 1643 * - native APU mode 1644 * "is_app_apu" can be used to identify the APU in the native 1645 * mode. 1646 */ 1647 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1648 !pci_resource_len(adev->pdev, 0)); 1649 } 1650 1651 gmc_v9_0_set_gmc_funcs(adev); 1652 gmc_v9_0_set_irq_funcs(adev); 1653 gmc_v9_0_set_umc_funcs(adev); 1654 gmc_v9_0_set_mmhub_funcs(adev); 1655 gmc_v9_0_set_mmhub_ras_funcs(adev); 1656 gmc_v9_0_set_gfxhub_funcs(adev); 1657 gmc_v9_0_set_hdp_ras_funcs(adev); 1658 gmc_v9_0_set_mca_ras_funcs(adev); 1659 gmc_v9_0_set_xgmi_ras_funcs(adev); 1660 1661 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1662 adev->gmc.shared_aperture_end = 1663 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1664 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1665 adev->gmc.private_aperture_end = 1666 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1667 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1668 1669 return 0; 1670 } 1671 1672 static int gmc_v9_0_late_init(struct amdgpu_ip_block *ip_block) 1673 { 1674 struct amdgpu_device *adev = ip_block->adev; 1675 int r; 1676 1677 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1678 if (r) 1679 return r; 1680 1681 /* 1682 * Workaround performance drop issue with VBIOS enables partial 1683 * writes, while disables HBM ECC for vega10. 1684 */ 1685 if (!amdgpu_sriov_vf(adev) && 1686 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) { 1687 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1688 if (adev->df.funcs && 1689 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1690 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1691 } 1692 } 1693 1694 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1695 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB); 1696 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP); 1697 } 1698 1699 r = amdgpu_gmc_ras_late_init(adev); 1700 if (r) 1701 return r; 1702 1703 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1704 } 1705 1706 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1707 struct amdgpu_gmc *mc) 1708 { 1709 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1710 1711 amdgpu_gmc_set_agp_default(adev, mc); 1712 1713 /* add the xgmi offset of the physical node */ 1714 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1715 if (adev->gmc.xgmi.connected_to_cpu) { 1716 amdgpu_gmc_sysvm_location(adev, mc); 1717 } else { 1718 amdgpu_gmc_vram_location(adev, mc, base); 1719 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 1720 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 1721 amdgpu_gmc_agp_location(adev, mc); 1722 } 1723 /* base offset of vram pages */ 1724 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1725 1726 /* XXX: add the xgmi offset of the physical node? */ 1727 adev->vm_manager.vram_base_offset += 1728 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1729 } 1730 1731 /** 1732 * gmc_v9_0_mc_init - initialize the memory controller driver params 1733 * 1734 * @adev: amdgpu_device pointer 1735 * 1736 * Look up the amount of vram, vram width, and decide how to place 1737 * vram and gart within the GPU's physical address space. 1738 * Returns 0 for success. 1739 */ 1740 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1741 { 1742 int r; 1743 1744 /* size in MB on si */ 1745 if (!adev->gmc.is_app_apu) { 1746 adev->gmc.mc_vram_size = 1747 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1748 } else { 1749 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1750 adev->gmc.mc_vram_size = 0; 1751 } 1752 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1753 1754 if (!(adev->flags & AMD_IS_APU) && 1755 !adev->gmc.xgmi.connected_to_cpu) { 1756 r = amdgpu_device_resize_fb_bar(adev); 1757 if (r) 1758 return r; 1759 } 1760 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1761 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1762 1763 #ifdef CONFIG_X86_64 1764 /* 1765 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1766 * interface can use VRAM through here as it appears system reserved 1767 * memory in host address space. 1768 * 1769 * For APUs, VRAM is just the stolen system memory and can be accessed 1770 * directly. 1771 * 1772 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1773 */ 1774 1775 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1776 if ((!amdgpu_sriov_vf(adev) && 1777 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1778 (adev->gmc.xgmi.supported && 1779 adev->gmc.xgmi.connected_to_cpu)) { 1780 adev->gmc.aper_base = 1781 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1782 adev->gmc.xgmi.physical_node_id * 1783 adev->gmc.xgmi.node_segment_size; 1784 adev->gmc.aper_size = adev->gmc.real_vram_size; 1785 } 1786 1787 #endif 1788 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1789 1790 /* set the gart size */ 1791 if (amdgpu_gart_size == -1) { 1792 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1793 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1794 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1795 case IP_VERSION(9, 4, 0): 1796 case IP_VERSION(9, 4, 1): 1797 case IP_VERSION(9, 4, 2): 1798 case IP_VERSION(9, 4, 3): 1799 case IP_VERSION(9, 4, 4): 1800 case IP_VERSION(9, 5, 0): 1801 default: 1802 adev->gmc.gart_size = 512ULL << 20; 1803 break; 1804 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1805 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1806 case IP_VERSION(9, 3, 0): 1807 adev->gmc.gart_size = 1024ULL << 20; 1808 break; 1809 } 1810 } else { 1811 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1812 } 1813 1814 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1815 1816 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1817 1818 return 0; 1819 } 1820 1821 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1822 { 1823 int r; 1824 1825 if (adev->gart.bo) { 1826 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1827 return 0; 1828 } 1829 1830 if (adev->gmc.xgmi.connected_to_cpu) { 1831 adev->gmc.vmid0_page_table_depth = 1; 1832 adev->gmc.vmid0_page_table_block_size = 12; 1833 } else { 1834 adev->gmc.vmid0_page_table_depth = 0; 1835 adev->gmc.vmid0_page_table_block_size = 0; 1836 } 1837 1838 /* Initialize common gart structure */ 1839 r = amdgpu_gart_init(adev); 1840 if (r) 1841 return r; 1842 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1843 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC) | 1844 AMDGPU_PTE_EXECUTABLE; 1845 1846 if (!adev->gmc.real_vram_size) { 1847 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1848 r = amdgpu_gart_table_ram_alloc(adev); 1849 if (r) 1850 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1851 } else { 1852 r = amdgpu_gart_table_vram_alloc(adev); 1853 if (r) 1854 return r; 1855 1856 if (adev->gmc.xgmi.connected_to_cpu) 1857 r = amdgpu_gmc_pdb0_alloc(adev); 1858 } 1859 1860 return r; 1861 } 1862 1863 /** 1864 * gmc_v9_0_save_registers - saves regs 1865 * 1866 * @adev: amdgpu_device pointer 1867 * 1868 * This saves potential register values that should be 1869 * restored upon resume 1870 */ 1871 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1872 { 1873 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1874 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) 1875 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1876 } 1877 1878 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev) 1879 { 1880 enum amdgpu_memory_partition mode; 1881 u32 supp_modes; 1882 bool valid; 1883 1884 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes); 1885 1886 /* Mode detected by hardware not present in supported modes */ 1887 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && 1888 !(BIT(mode - 1) & supp_modes)) 1889 return false; 1890 1891 switch (mode) { 1892 case UNKNOWN_MEMORY_PARTITION_MODE: 1893 case AMDGPU_NPS1_PARTITION_MODE: 1894 valid = (adev->gmc.num_mem_partitions == 1); 1895 break; 1896 case AMDGPU_NPS2_PARTITION_MODE: 1897 valid = (adev->gmc.num_mem_partitions == 2); 1898 break; 1899 case AMDGPU_NPS4_PARTITION_MODE: 1900 valid = (adev->gmc.num_mem_partitions == 3 || 1901 adev->gmc.num_mem_partitions == 4); 1902 break; 1903 default: 1904 valid = false; 1905 } 1906 1907 return valid; 1908 } 1909 1910 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid) 1911 { 1912 int i; 1913 1914 /* Check if node with id 'nid' is present in 'node_ids' array */ 1915 for (i = 0; i < num_ids; ++i) 1916 if (node_ids[i] == nid) 1917 return true; 1918 1919 return false; 1920 } 1921 1922 static void 1923 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev, 1924 struct amdgpu_mem_partition_info *mem_ranges) 1925 { 1926 struct amdgpu_numa_info numa_info; 1927 int node_ids[MAX_MEM_RANGES]; 1928 int num_ranges = 0, ret; 1929 int num_xcc, xcc_id; 1930 uint32_t xcc_mask; 1931 1932 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1933 xcc_mask = (1U << num_xcc) - 1; 1934 1935 for_each_inst(xcc_id, xcc_mask) { 1936 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 1937 if (ret) 1938 continue; 1939 1940 if (numa_info.nid == NUMA_NO_NODE) { 1941 mem_ranges[0].size = numa_info.size; 1942 mem_ranges[0].numa.node = numa_info.nid; 1943 num_ranges = 1; 1944 break; 1945 } 1946 1947 if (gmc_v9_0_is_node_present(node_ids, num_ranges, 1948 numa_info.nid)) 1949 continue; 1950 1951 node_ids[num_ranges] = numa_info.nid; 1952 mem_ranges[num_ranges].numa.node = numa_info.nid; 1953 mem_ranges[num_ranges].size = numa_info.size; 1954 ++num_ranges; 1955 } 1956 1957 adev->gmc.num_mem_partitions = num_ranges; 1958 } 1959 1960 static void 1961 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, 1962 struct amdgpu_mem_partition_info *mem_ranges) 1963 { 1964 enum amdgpu_memory_partition mode; 1965 u32 start_addr = 0, size; 1966 int i, r, l; 1967 1968 mode = gmc_v9_0_query_memory_partition(adev); 1969 1970 switch (mode) { 1971 case UNKNOWN_MEMORY_PARTITION_MODE: 1972 adev->gmc.num_mem_partitions = 0; 1973 break; 1974 case AMDGPU_NPS1_PARTITION_MODE: 1975 adev->gmc.num_mem_partitions = 1; 1976 break; 1977 case AMDGPU_NPS2_PARTITION_MODE: 1978 adev->gmc.num_mem_partitions = 2; 1979 break; 1980 case AMDGPU_NPS4_PARTITION_MODE: 1981 if (adev->flags & AMD_IS_APU) 1982 adev->gmc.num_mem_partitions = 3; 1983 else 1984 adev->gmc.num_mem_partitions = 4; 1985 break; 1986 default: 1987 adev->gmc.num_mem_partitions = 1; 1988 break; 1989 } 1990 1991 /* Use NPS range info, if populated */ 1992 r = amdgpu_gmc_get_nps_memranges(adev, mem_ranges, 1993 &adev->gmc.num_mem_partitions); 1994 if (!r) { 1995 l = 0; 1996 for (i = 1; i < adev->gmc.num_mem_partitions; ++i) { 1997 if (mem_ranges[i].range.lpfn > 1998 mem_ranges[i - 1].range.lpfn) 1999 l = i; 2000 } 2001 2002 } else { 2003 if (!adev->gmc.num_mem_partitions) { 2004 dev_err(adev->dev, 2005 "Not able to detect NPS mode, fall back to NPS1"); 2006 adev->gmc.num_mem_partitions = 1; 2007 } 2008 /* Fallback to sw based calculation */ 2009 size = (adev->gmc.real_vram_size + SZ_16M) >> AMDGPU_GPU_PAGE_SHIFT; 2010 size /= adev->gmc.num_mem_partitions; 2011 2012 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 2013 mem_ranges[i].range.fpfn = start_addr; 2014 mem_ranges[i].size = 2015 ((u64)size << AMDGPU_GPU_PAGE_SHIFT); 2016 mem_ranges[i].range.lpfn = start_addr + size - 1; 2017 start_addr += size; 2018 } 2019 2020 l = adev->gmc.num_mem_partitions - 1; 2021 } 2022 2023 /* Adjust the last one */ 2024 mem_ranges[l].range.lpfn = 2025 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; 2026 mem_ranges[l].size = 2027 adev->gmc.real_vram_size - 2028 ((u64)mem_ranges[l].range.fpfn << AMDGPU_GPU_PAGE_SHIFT); 2029 } 2030 2031 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev) 2032 { 2033 bool valid; 2034 2035 adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES, 2036 sizeof(struct amdgpu_mem_partition_info), 2037 GFP_KERNEL); 2038 if (!adev->gmc.mem_partitions) 2039 return -ENOMEM; 2040 2041 /* TODO : Get the range from PSP/Discovery for dGPU */ 2042 if (adev->gmc.is_app_apu) 2043 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); 2044 else 2045 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 2046 2047 if (amdgpu_sriov_vf(adev)) 2048 valid = true; 2049 else 2050 valid = gmc_v9_0_validate_partition_info(adev); 2051 if (!valid) { 2052 /* TODO: handle invalid case */ 2053 dev_WARN(adev->dev, 2054 "Mem ranges not matching with hardware config"); 2055 } 2056 2057 return 0; 2058 } 2059 2060 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 2061 { 2062 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 2063 adev->gmc.vram_width = 128 * 64; 2064 } 2065 2066 static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) 2067 { 2068 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 2069 struct amdgpu_device *adev = ip_block->adev; 2070 unsigned long inst_mask = adev->aid_mask; 2071 2072 adev->gfxhub.funcs->init(adev); 2073 2074 adev->mmhub.funcs->init(adev); 2075 2076 spin_lock_init(&adev->gmc.invalidate_lock); 2077 2078 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2079 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 2080 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) { 2081 gmc_v9_4_3_init_vram_info(adev); 2082 } else if (!adev->bios) { 2083 if (adev->flags & AMD_IS_APU) { 2084 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 2085 adev->gmc.vram_width = 64 * 64; 2086 } else { 2087 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 2088 adev->gmc.vram_width = 128 * 64; 2089 } 2090 } else { 2091 r = amdgpu_atomfirmware_get_vram_info(adev, 2092 &vram_width, &vram_type, &vram_vendor); 2093 if (amdgpu_sriov_vf(adev)) 2094 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 2095 * and DF related registers is not readable, seems hardcord is the 2096 * only way to set the correct vram_width 2097 */ 2098 adev->gmc.vram_width = 2048; 2099 else if (amdgpu_emu_mode != 1) 2100 adev->gmc.vram_width = vram_width; 2101 2102 if (!adev->gmc.vram_width) { 2103 int chansize, numchan; 2104 2105 /* hbm memory channel size */ 2106 if (adev->flags & AMD_IS_APU) 2107 chansize = 64; 2108 else 2109 chansize = 128; 2110 if (adev->df.funcs && 2111 adev->df.funcs->get_hbm_channel_number) { 2112 numchan = adev->df.funcs->get_hbm_channel_number(adev); 2113 adev->gmc.vram_width = numchan * chansize; 2114 } 2115 } 2116 2117 adev->gmc.vram_type = vram_type; 2118 adev->gmc.vram_vendor = vram_vendor; 2119 } 2120 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2121 case IP_VERSION(9, 1, 0): 2122 case IP_VERSION(9, 2, 2): 2123 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2124 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2125 2126 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 2127 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2128 } else { 2129 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 2130 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 2131 adev->gmc.translate_further = 2132 adev->vm_manager.num_level > 1; 2133 } 2134 break; 2135 case IP_VERSION(9, 0, 1): 2136 case IP_VERSION(9, 2, 1): 2137 case IP_VERSION(9, 4, 0): 2138 case IP_VERSION(9, 3, 0): 2139 case IP_VERSION(9, 4, 2): 2140 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2141 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2142 2143 /* 2144 * To fulfill 4-level page support, 2145 * vm size is 256TB (48bit), maximum size of Vega10, 2146 * block size 512 (9bit) 2147 */ 2148 2149 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2150 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 2151 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2152 break; 2153 case IP_VERSION(9, 4, 1): 2154 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2155 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2156 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 2157 2158 /* Keep the vm size same with Vega20 */ 2159 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2160 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2161 break; 2162 case IP_VERSION(9, 4, 3): 2163 case IP_VERSION(9, 4, 4): 2164 case IP_VERSION(9, 5, 0): 2165 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 2166 NUM_XCC(adev->gfx.xcc_mask)); 2167 2168 inst_mask <<= AMDGPU_MMHUB0(0); 2169 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 2170 2171 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2172 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2173 break; 2174 default: 2175 break; 2176 } 2177 2178 /* This interrupt is VMC page fault.*/ 2179 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 2180 &adev->gmc.vm_fault); 2181 if (r) 2182 return r; 2183 2184 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) { 2185 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 2186 &adev->gmc.vm_fault); 2187 if (r) 2188 return r; 2189 } 2190 2191 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 2192 &adev->gmc.vm_fault); 2193 2194 if (r) 2195 return r; 2196 2197 if (!amdgpu_sriov_vf(adev) && 2198 !adev->gmc.xgmi.connected_to_cpu && 2199 !adev->gmc.is_app_apu) { 2200 /* interrupt sent to DF. */ 2201 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 2202 &adev->gmc.ecc_irq); 2203 if (r) 2204 return r; 2205 } 2206 2207 /* Set the internal MC address mask 2208 * This is the max address of the GPU's 2209 * internal address space. 2210 */ 2211 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 2212 2213 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= 2214 IP_VERSION(9, 4, 2) ? 2215 48 : 2216 44; 2217 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 2218 if (r) { 2219 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 2220 return r; 2221 } 2222 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 2223 2224 r = gmc_v9_0_mc_init(adev); 2225 if (r) 2226 return r; 2227 2228 amdgpu_gmc_get_vbios_allocations(adev); 2229 2230 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2231 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 2232 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) { 2233 r = gmc_v9_0_init_mem_ranges(adev); 2234 if (r) 2235 return r; 2236 } 2237 2238 /* Memory manager */ 2239 r = amdgpu_bo_init(adev); 2240 if (r) 2241 return r; 2242 2243 r = gmc_v9_0_gart_init(adev); 2244 if (r) 2245 return r; 2246 2247 gmc_v9_0_init_nps_details(adev); 2248 /* 2249 * number of VMs 2250 * VMID 0 is reserved for System 2251 * amdgpu graphics/compute will use VMIDs 1..n-1 2252 * amdkfd will use VMIDs n..15 2253 * 2254 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2255 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2256 * for video processing. 2257 */ 2258 adev->vm_manager.first_kfd_vmid = 2259 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 2260 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 2261 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2262 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 2263 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) ? 2264 3 : 2265 8; 2266 2267 amdgpu_vm_manager_init(adev); 2268 2269 gmc_v9_0_save_registers(adev); 2270 2271 r = amdgpu_gmc_ras_sw_init(adev); 2272 if (r) 2273 return r; 2274 2275 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2276 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 2277 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 2278 amdgpu_gmc_sysfs_init(adev); 2279 2280 return 0; 2281 } 2282 2283 static int gmc_v9_0_sw_fini(struct amdgpu_ip_block *ip_block) 2284 { 2285 struct amdgpu_device *adev = ip_block->adev; 2286 2287 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2288 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || 2289 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 2290 amdgpu_gmc_sysfs_fini(adev); 2291 2292 amdgpu_gmc_ras_fini(adev); 2293 amdgpu_gem_force_release(adev); 2294 amdgpu_vm_manager_fini(adev); 2295 if (!adev->gmc.real_vram_size) { 2296 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2297 amdgpu_gart_table_ram_free(adev); 2298 } else { 2299 amdgpu_gart_table_vram_free(adev); 2300 } 2301 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2302 amdgpu_bo_fini(adev); 2303 2304 adev->gmc.num_mem_partitions = 0; 2305 kfree(adev->gmc.mem_partitions); 2306 2307 return 0; 2308 } 2309 2310 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2311 { 2312 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 2313 case IP_VERSION(9, 0, 0): 2314 if (amdgpu_sriov_vf(adev)) 2315 break; 2316 fallthrough; 2317 case IP_VERSION(9, 4, 0): 2318 soc15_program_register_sequence(adev, 2319 golden_settings_mmhub_1_0_0, 2320 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2321 soc15_program_register_sequence(adev, 2322 golden_settings_athub_1_0_0, 2323 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2324 break; 2325 case IP_VERSION(9, 1, 0): 2326 case IP_VERSION(9, 2, 0): 2327 /* TODO for renoir */ 2328 soc15_program_register_sequence(adev, 2329 golden_settings_athub_1_0_0, 2330 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2331 break; 2332 default: 2333 break; 2334 } 2335 } 2336 2337 /** 2338 * gmc_v9_0_restore_registers - restores regs 2339 * 2340 * @adev: amdgpu_device pointer 2341 * 2342 * This restores register values, saved at suspend. 2343 */ 2344 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2345 { 2346 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 2347 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) { 2348 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2349 WARN_ON(adev->gmc.sdpif_register != 2350 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2351 } 2352 } 2353 2354 /** 2355 * gmc_v9_0_gart_enable - gart enable 2356 * 2357 * @adev: amdgpu_device pointer 2358 */ 2359 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2360 { 2361 int r; 2362 2363 if (adev->gmc.xgmi.connected_to_cpu) 2364 amdgpu_gmc_init_pdb0(adev); 2365 2366 if (adev->gart.bo == NULL) { 2367 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2368 return -EINVAL; 2369 } 2370 2371 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2372 2373 if (!adev->in_s0ix) { 2374 r = adev->gfxhub.funcs->gart_enable(adev); 2375 if (r) 2376 return r; 2377 } 2378 2379 r = adev->mmhub.funcs->gart_enable(adev); 2380 if (r) 2381 return r; 2382 2383 DRM_INFO("PCIE GART of %uM enabled.\n", 2384 (unsigned int)(adev->gmc.gart_size >> 20)); 2385 if (adev->gmc.pdb0_bo) 2386 DRM_INFO("PDB0 located at 0x%016llX\n", 2387 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2388 DRM_INFO("PTB located at 0x%016llX\n", 2389 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2390 2391 return 0; 2392 } 2393 2394 static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block) 2395 { 2396 struct amdgpu_device *adev = ip_block->adev; 2397 bool value; 2398 int i, r; 2399 2400 adev->gmc.flush_pasid_uses_kiq = true; 2401 2402 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush 2403 * (type 2), which flushes both. Due to a race condition with 2404 * concurrent memory accesses using the same TLB cache line, we still 2405 * need a second TLB flush after this. 2406 */ 2407 adev->gmc.flush_tlb_needs_extra_type_2 = 2408 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) && 2409 adev->gmc.xgmi.num_physical_nodes; 2410 /* 2411 * TODO: This workaround is badly documented and had a buggy 2412 * implementation. We should probably verify what we do here. 2413 */ 2414 adev->gmc.flush_tlb_needs_extra_type_0 = 2415 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 2416 adev->rev_id == 0; 2417 2418 /* The sequence of these two function calls matters.*/ 2419 gmc_v9_0_init_golden_registers(adev); 2420 2421 if (adev->mode_info.num_crtc) { 2422 /* Lockout access through VGA aperture*/ 2423 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2424 /* disable VGA render */ 2425 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2426 } 2427 2428 if (adev->mmhub.funcs->update_power_gating) 2429 adev->mmhub.funcs->update_power_gating(adev, true); 2430 2431 adev->hdp.funcs->init_registers(adev); 2432 2433 /* After HDP is initialized, flush HDP.*/ 2434 adev->hdp.funcs->flush_hdp(adev, NULL); 2435 2436 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2437 value = false; 2438 else 2439 value = true; 2440 2441 if (!amdgpu_sriov_vf(adev)) { 2442 if (!adev->in_s0ix) 2443 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2444 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2445 } 2446 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2447 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2448 continue; 2449 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2450 } 2451 2452 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2453 adev->umc.funcs->init_registers(adev); 2454 2455 r = gmc_v9_0_gart_enable(adev); 2456 if (r) 2457 return r; 2458 2459 if (amdgpu_emu_mode == 1) 2460 return amdgpu_gmc_vram_checking(adev); 2461 2462 return 0; 2463 } 2464 2465 /** 2466 * gmc_v9_0_gart_disable - gart disable 2467 * 2468 * @adev: amdgpu_device pointer 2469 * 2470 * This disables all VM page table. 2471 */ 2472 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2473 { 2474 if (!adev->in_s0ix) 2475 adev->gfxhub.funcs->gart_disable(adev); 2476 adev->mmhub.funcs->gart_disable(adev); 2477 } 2478 2479 static int gmc_v9_0_hw_fini(struct amdgpu_ip_block *ip_block) 2480 { 2481 struct amdgpu_device *adev = ip_block->adev; 2482 2483 gmc_v9_0_gart_disable(adev); 2484 2485 if (amdgpu_sriov_vf(adev)) { 2486 /* full access mode, so don't touch any GMC register */ 2487 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2488 return 0; 2489 } 2490 2491 /* 2492 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2493 * a correct cached state for GMC. Otherwise, the "gate" again 2494 * operation on S3 resuming will fail due to wrong cached state. 2495 */ 2496 if (adev->mmhub.funcs->update_power_gating) 2497 adev->mmhub.funcs->update_power_gating(adev, false); 2498 2499 /* 2500 * For minimal init, late_init is not called, hence VM fault/RAS irqs 2501 * are not enabled. 2502 */ 2503 if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { 2504 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2505 2506 if (adev->gmc.ecc_irq.funcs && 2507 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2508 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 2509 } 2510 2511 return 0; 2512 } 2513 2514 static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block) 2515 { 2516 return gmc_v9_0_hw_fini(ip_block); 2517 } 2518 2519 static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block) 2520 { 2521 struct amdgpu_device *adev = ip_block->adev; 2522 int r; 2523 2524 /* If a reset is done for NPS mode switch, read the memory range 2525 * information again. 2526 */ 2527 if (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS) { 2528 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 2529 adev->gmc.reset_flags &= ~AMDGPU_GMC_INIT_RESET_NPS; 2530 } 2531 2532 r = gmc_v9_0_hw_init(ip_block); 2533 if (r) 2534 return r; 2535 2536 amdgpu_vmid_reset_all(ip_block->adev); 2537 2538 return 0; 2539 } 2540 2541 static bool gmc_v9_0_is_idle(void *handle) 2542 { 2543 /* MC is always ready in GMC v9.*/ 2544 return true; 2545 } 2546 2547 static int gmc_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 2548 { 2549 /* There is no need to wait for MC idle in GMC v9.*/ 2550 return 0; 2551 } 2552 2553 static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block) 2554 { 2555 /* XXX for emulation.*/ 2556 return 0; 2557 } 2558 2559 static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2560 enum amd_clockgating_state state) 2561 { 2562 struct amdgpu_device *adev = ip_block->adev; 2563 2564 adev->mmhub.funcs->set_clockgating(adev, state); 2565 2566 athub_v1_0_set_clockgating(adev, state); 2567 2568 return 0; 2569 } 2570 2571 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 2572 { 2573 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2574 2575 adev->mmhub.funcs->get_clockgating(adev, flags); 2576 2577 athub_v1_0_get_clockgating(adev, flags); 2578 } 2579 2580 static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 2581 enum amd_powergating_state state) 2582 { 2583 return 0; 2584 } 2585 2586 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2587 .name = "gmc_v9_0", 2588 .early_init = gmc_v9_0_early_init, 2589 .late_init = gmc_v9_0_late_init, 2590 .sw_init = gmc_v9_0_sw_init, 2591 .sw_fini = gmc_v9_0_sw_fini, 2592 .hw_init = gmc_v9_0_hw_init, 2593 .hw_fini = gmc_v9_0_hw_fini, 2594 .suspend = gmc_v9_0_suspend, 2595 .resume = gmc_v9_0_resume, 2596 .is_idle = gmc_v9_0_is_idle, 2597 .wait_for_idle = gmc_v9_0_wait_for_idle, 2598 .soft_reset = gmc_v9_0_soft_reset, 2599 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2600 .set_powergating_state = gmc_v9_0_set_powergating_state, 2601 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2602 }; 2603 2604 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = { 2605 .type = AMD_IP_BLOCK_TYPE_GMC, 2606 .major = 9, 2607 .minor = 0, 2608 .rev = 0, 2609 .funcs = &gmc_v9_0_ip_funcs, 2610 }; 2611