1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "gmc_v9_0.h" 26 27 #include "vega10/soc15ip.h" 28 #include "vega10/HDP/hdp_4_0_offset.h" 29 #include "vega10/HDP/hdp_4_0_sh_mask.h" 30 #include "vega10/GC/gc_9_0_sh_mask.h" 31 #include "vega10/vega10_enum.h" 32 33 #include "soc15_common.h" 34 35 #include "nbio_v6_1.h" 36 #include "gfxhub_v1_0.h" 37 #include "mmhub_v1_0.h" 38 39 #define mmDF_CS_AON0_DramBaseAddress0 0x0044 40 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0 41 //DF_CS_AON0_DramBaseAddress0 42 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 43 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 44 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4 45 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8 46 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc 47 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L 48 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L 49 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L 50 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L 51 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L 52 53 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ 54 #define AMDGPU_NUM_OF_VMIDS 8 55 56 static const u32 golden_settings_vega10_hdp[] = 57 { 58 0xf64, 0x0fffffff, 0x00000000, 59 0xf65, 0x0fffffff, 0x00000000, 60 0xf66, 0x0fffffff, 0x00000000, 61 0xf67, 0x0fffffff, 0x00000000, 62 0xf68, 0x0fffffff, 0x00000000, 63 0xf6a, 0x0fffffff, 0x00000000, 64 0xf6b, 0x0fffffff, 0x00000000, 65 0xf6c, 0x0fffffff, 0x00000000, 66 0xf6d, 0x0fffffff, 0x00000000, 67 0xf6e, 0x0fffffff, 0x00000000, 68 }; 69 70 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 71 struct amdgpu_irq_src *src, 72 unsigned type, 73 enum amdgpu_interrupt_state state) 74 { 75 struct amdgpu_vmhub *hub; 76 u32 tmp, reg, bits, i; 77 78 switch (state) { 79 case AMDGPU_IRQ_STATE_DISABLE: 80 /* MM HUB */ 81 hub = &adev->vmhub[AMDGPU_MMHUB]; 82 bits = hub->get_vm_protection_bits(); 83 for (i = 0; i< 16; i++) { 84 reg = hub->vm_context0_cntl + i; 85 tmp = RREG32(reg); 86 tmp &= ~bits; 87 WREG32(reg, tmp); 88 } 89 90 /* GFX HUB */ 91 hub = &adev->vmhub[AMDGPU_GFXHUB]; 92 bits = hub->get_vm_protection_bits(); 93 for (i = 0; i < 16; i++) { 94 reg = hub->vm_context0_cntl + i; 95 tmp = RREG32(reg); 96 tmp &= ~bits; 97 WREG32(reg, tmp); 98 } 99 break; 100 case AMDGPU_IRQ_STATE_ENABLE: 101 /* MM HUB */ 102 hub = &adev->vmhub[AMDGPU_MMHUB]; 103 bits = hub->get_vm_protection_bits(); 104 for (i = 0; i< 16; i++) { 105 reg = hub->vm_context0_cntl + i; 106 tmp = RREG32(reg); 107 tmp |= bits; 108 WREG32(reg, tmp); 109 } 110 111 /* GFX HUB */ 112 hub = &adev->vmhub[AMDGPU_GFXHUB]; 113 bits = hub->get_vm_protection_bits(); 114 for (i = 0; i < 16; i++) { 115 reg = hub->vm_context0_cntl + i; 116 tmp = RREG32(reg); 117 tmp |= bits; 118 WREG32(reg, tmp); 119 } 120 break; 121 default: 122 break; 123 } 124 125 return 0; 126 } 127 128 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 129 struct amdgpu_irq_src *source, 130 struct amdgpu_iv_entry *entry) 131 { 132 struct amdgpu_vmhub *gfxhub = &adev->vmhub[AMDGPU_GFXHUB]; 133 struct amdgpu_vmhub *mmhub = &adev->vmhub[AMDGPU_MMHUB]; 134 uint32_t status = 0; 135 u64 addr; 136 137 addr = (u64)entry->src_data[0] << 12; 138 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 139 140 if (!amdgpu_sriov_vf(adev)) { 141 if (entry->vm_id_src) { 142 status = RREG32(mmhub->vm_l2_pro_fault_status); 143 WREG32_P(mmhub->vm_l2_pro_fault_cntl, 1, ~1); 144 } else { 145 status = RREG32(gfxhub->vm_l2_pro_fault_status); 146 WREG32_P(gfxhub->vm_l2_pro_fault_cntl, 1, ~1); 147 } 148 } 149 150 if (printk_ratelimit()) { 151 dev_err(adev->dev, 152 "[%s] VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u)\n", 153 entry->vm_id_src ? "mmhub" : "gfxhub", 154 entry->src_id, entry->ring_id, entry->vm_id, 155 entry->pas_id); 156 dev_err(adev->dev, " at page 0x%016llx from %d\n", 157 addr, entry->client_id); 158 if (!amdgpu_sriov_vf(adev)) 159 dev_err(adev->dev, 160 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 161 status); 162 } 163 164 return 0; 165 } 166 167 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 168 .set = gmc_v9_0_vm_fault_interrupt_state, 169 .process = gmc_v9_0_process_interrupt, 170 }; 171 172 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 173 { 174 adev->mc.vm_fault.num_types = 1; 175 adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 176 } 177 178 /* 179 * GART 180 * VMID 0 is the physical GPU addresses as used by the kernel. 181 * VMIDs 1-15 are used for userspace clients and are handled 182 * by the amdgpu vm/hsa code. 183 */ 184 185 /** 186 * gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback 187 * 188 * @adev: amdgpu_device pointer 189 * @vmid: vm instance to flush 190 * 191 * Flush the TLB for the requested page table. 192 */ 193 static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 194 uint32_t vmid) 195 { 196 /* Use register 17 for GART */ 197 const unsigned eng = 17; 198 unsigned i, j; 199 200 /* flush hdp cache */ 201 nbio_v6_1_hdp_flush(adev); 202 203 spin_lock(&adev->mc.invalidate_lock); 204 205 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { 206 struct amdgpu_vmhub *hub = &adev->vmhub[i]; 207 u32 tmp = hub->get_invalidate_req(vmid); 208 209 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); 210 211 /* Busy wait for ACK.*/ 212 for (j = 0; j < 100; j++) { 213 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 214 tmp &= 1 << vmid; 215 if (tmp) 216 break; 217 cpu_relax(); 218 } 219 if (j < 100) 220 continue; 221 222 /* Wait for ACK with a delay.*/ 223 for (j = 0; j < adev->usec_timeout; j++) { 224 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 225 tmp &= 1 << vmid; 226 if (tmp) 227 break; 228 udelay(1); 229 } 230 if (j < adev->usec_timeout) 231 continue; 232 233 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 234 } 235 236 spin_unlock(&adev->mc.invalidate_lock); 237 } 238 239 /** 240 * gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO 241 * 242 * @adev: amdgpu_device pointer 243 * @cpu_pt_addr: cpu address of the page table 244 * @gpu_page_idx: entry in the page table to update 245 * @addr: dst addr to write into pte/pde 246 * @flags: access flags 247 * 248 * Update the page tables using the CPU. 249 */ 250 static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev, 251 void *cpu_pt_addr, 252 uint32_t gpu_page_idx, 253 uint64_t addr, 254 uint64_t flags) 255 { 256 void __iomem *ptr = (void *)cpu_pt_addr; 257 uint64_t value; 258 259 /* 260 * PTE format on VEGA 10: 261 * 63:59 reserved 262 * 58:57 mtype 263 * 56 F 264 * 55 L 265 * 54 P 266 * 53 SW 267 * 52 T 268 * 50:48 reserved 269 * 47:12 4k physical page base address 270 * 11:7 fragment 271 * 6 write 272 * 5 read 273 * 4 exe 274 * 3 Z 275 * 2 snooped 276 * 1 system 277 * 0 valid 278 * 279 * PDE format on VEGA 10: 280 * 63:59 block fragment size 281 * 58:55 reserved 282 * 54 P 283 * 53:48 reserved 284 * 47:6 physical base address of PD or PTE 285 * 5:3 reserved 286 * 2 C 287 * 1 system 288 * 0 valid 289 */ 290 291 /* 292 * The following is for PTE only. GART does not have PDEs. 293 */ 294 value = addr & 0x0000FFFFFFFFF000ULL; 295 value |= flags; 296 writeq(value, ptr + (gpu_page_idx * 8)); 297 return 0; 298 } 299 300 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, 301 uint32_t flags) 302 303 { 304 uint64_t pte_flag = 0; 305 306 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 307 pte_flag |= AMDGPU_PTE_EXECUTABLE; 308 if (flags & AMDGPU_VM_PAGE_READABLE) 309 pte_flag |= AMDGPU_PTE_READABLE; 310 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 311 pte_flag |= AMDGPU_PTE_WRITEABLE; 312 313 switch (flags & AMDGPU_VM_MTYPE_MASK) { 314 case AMDGPU_VM_MTYPE_DEFAULT: 315 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 316 break; 317 case AMDGPU_VM_MTYPE_NC: 318 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 319 break; 320 case AMDGPU_VM_MTYPE_WC: 321 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC); 322 break; 323 case AMDGPU_VM_MTYPE_CC: 324 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC); 325 break; 326 case AMDGPU_VM_MTYPE_UC: 327 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC); 328 break; 329 default: 330 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 331 break; 332 } 333 334 if (flags & AMDGPU_VM_PAGE_PRT) 335 pte_flag |= AMDGPU_PTE_PRT; 336 337 return pte_flag; 338 } 339 340 static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = { 341 .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb, 342 .set_pte_pde = gmc_v9_0_gart_set_pte_pde, 343 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags 344 }; 345 346 static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev) 347 { 348 if (adev->gart.gart_funcs == NULL) 349 adev->gart.gart_funcs = &gmc_v9_0_gart_funcs; 350 } 351 352 static u64 gmc_v9_0_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr) 353 { 354 return adev->vm_manager.vram_base_offset + mc_addr - adev->mc.vram_start; 355 } 356 357 static const struct amdgpu_mc_funcs gmc_v9_0_mc_funcs = { 358 .adjust_mc_addr = gmc_v9_0_adjust_mc_addr, 359 }; 360 361 static void gmc_v9_0_set_mc_funcs(struct amdgpu_device *adev) 362 { 363 adev->mc.mc_funcs = &gmc_v9_0_mc_funcs; 364 } 365 366 static int gmc_v9_0_early_init(void *handle) 367 { 368 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 369 370 gmc_v9_0_set_gart_funcs(adev); 371 gmc_v9_0_set_mc_funcs(adev); 372 gmc_v9_0_set_irq_funcs(adev); 373 374 return 0; 375 } 376 377 static int gmc_v9_0_late_init(void *handle) 378 { 379 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 380 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 381 } 382 383 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 384 struct amdgpu_mc *mc) 385 { 386 u64 base = 0; 387 if (!amdgpu_sriov_vf(adev)) 388 base = mmhub_v1_0_get_fb_location(adev); 389 amdgpu_vram_location(adev, &adev->mc, base); 390 adev->mc.gtt_base_align = 0; 391 amdgpu_gtt_location(adev, mc); 392 } 393 394 /** 395 * gmc_v9_0_mc_init - initialize the memory controller driver params 396 * 397 * @adev: amdgpu_device pointer 398 * 399 * Look up the amount of vram, vram width, and decide how to place 400 * vram and gart within the GPU's physical address space. 401 * Returns 0 for success. 402 */ 403 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 404 { 405 u32 tmp; 406 int chansize, numchan; 407 408 /* hbm memory channel size */ 409 chansize = 128; 410 411 tmp = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_CS_AON0_DramBaseAddress0)); 412 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK; 413 tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; 414 switch (tmp) { 415 case 0: 416 default: 417 numchan = 1; 418 break; 419 case 1: 420 numchan = 2; 421 break; 422 case 2: 423 numchan = 0; 424 break; 425 case 3: 426 numchan = 4; 427 break; 428 case 4: 429 numchan = 0; 430 break; 431 case 5: 432 numchan = 8; 433 break; 434 case 6: 435 numchan = 0; 436 break; 437 case 7: 438 numchan = 16; 439 break; 440 case 8: 441 numchan = 2; 442 break; 443 } 444 adev->mc.vram_width = numchan * chansize; 445 446 /* Could aper size report 0 ? */ 447 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 448 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 449 /* size in MB on si */ 450 adev->mc.mc_vram_size = 451 nbio_v6_1_get_memsize(adev) * 1024ULL * 1024ULL; 452 adev->mc.real_vram_size = adev->mc.mc_vram_size; 453 adev->mc.visible_vram_size = adev->mc.aper_size; 454 455 /* In case the PCI BAR is larger than the actual amount of vram */ 456 if (adev->mc.visible_vram_size > adev->mc.real_vram_size) 457 adev->mc.visible_vram_size = adev->mc.real_vram_size; 458 459 /* unless the user had overridden it, set the gart 460 * size equal to the 1024 or vram, whichever is larger. 461 */ 462 if (amdgpu_gart_size == -1) 463 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); 464 else 465 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; 466 467 gmc_v9_0_vram_gtt_location(adev, &adev->mc); 468 469 return 0; 470 } 471 472 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 473 { 474 int r; 475 476 if (adev->gart.robj) { 477 WARN(1, "VEGA10 PCIE GART already initialized\n"); 478 return 0; 479 } 480 /* Initialize common gart structure */ 481 r = amdgpu_gart_init(adev); 482 if (r) 483 return r; 484 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 485 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) | 486 AMDGPU_PTE_EXECUTABLE; 487 return amdgpu_gart_table_vram_alloc(adev); 488 } 489 490 /* 491 * vm 492 * VMID 0 is the physical GPU addresses as used by the kernel. 493 * VMIDs 1-15 are used for userspace clients and are handled 494 * by the amdgpu vm/hsa code. 495 */ 496 /** 497 * gmc_v9_0_vm_init - vm init callback 498 * 499 * @adev: amdgpu_device pointer 500 * 501 * Inits vega10 specific vm parameters (number of VMs, base of vram for 502 * VMIDs 1-15) (vega10). 503 * Returns 0 for success. 504 */ 505 static int gmc_v9_0_vm_init(struct amdgpu_device *adev) 506 { 507 /* 508 * number of VMs 509 * VMID 0 is reserved for System 510 * amdgpu graphics/compute will use VMIDs 1-7 511 * amdkfd will use VMIDs 8-15 512 */ 513 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS; 514 adev->vm_manager.num_level = 3; 515 amdgpu_vm_manager_init(adev); 516 517 /* base offset of vram pages */ 518 /*XXX This value is not zero for APU*/ 519 adev->vm_manager.vram_base_offset = 0; 520 521 return 0; 522 } 523 524 /** 525 * gmc_v9_0_vm_fini - vm fini callback 526 * 527 * @adev: amdgpu_device pointer 528 * 529 * Tear down any asic specific VM setup. 530 */ 531 static void gmc_v9_0_vm_fini(struct amdgpu_device *adev) 532 { 533 return; 534 } 535 536 static int gmc_v9_0_sw_init(void *handle) 537 { 538 int r; 539 int dma_bits; 540 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 541 542 spin_lock_init(&adev->mc.invalidate_lock); 543 544 if (adev->flags & AMD_IS_APU) { 545 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 546 } else { 547 /* XXX Don't know how to get VRAM type yet. */ 548 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; 549 } 550 551 /* This interrupt is VMC page fault.*/ 552 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, 553 &adev->mc.vm_fault); 554 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0, 555 &adev->mc.vm_fault); 556 557 if (r) 558 return r; 559 560 /* Because of four level VMPTs, vm size is at least 512GB. 561 * The maximum size is 256TB (48bit). 562 */ 563 if (amdgpu_vm_size < 512) { 564 DRM_WARN("VM size is at least 512GB!\n"); 565 amdgpu_vm_size = 512; 566 } 567 adev->vm_manager.max_pfn = (uint64_t)amdgpu_vm_size << 18; 568 569 /* Set the internal MC address mask 570 * This is the max address of the GPU's 571 * internal address space. 572 */ 573 adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 574 575 /* set DMA mask + need_dma32 flags. 576 * PCIE - can handle 44-bits. 577 * IGP - can handle 44-bits 578 * PCI - dma32 for legacy pci gart, 44 bits on vega10 579 */ 580 adev->need_dma32 = false; 581 dma_bits = adev->need_dma32 ? 32 : 44; 582 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 583 if (r) { 584 adev->need_dma32 = true; 585 dma_bits = 32; 586 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 587 } 588 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 589 if (r) { 590 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 591 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); 592 } 593 594 r = gmc_v9_0_mc_init(adev); 595 if (r) 596 return r; 597 598 /* Memory manager */ 599 r = amdgpu_bo_init(adev); 600 if (r) 601 return r; 602 603 r = gmc_v9_0_gart_init(adev); 604 if (r) 605 return r; 606 607 if (!adev->vm_manager.enabled) { 608 r = gmc_v9_0_vm_init(adev); 609 if (r) { 610 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 611 return r; 612 } 613 adev->vm_manager.enabled = true; 614 } 615 return r; 616 } 617 618 /** 619 * gmc_v8_0_gart_fini - vm fini callback 620 * 621 * @adev: amdgpu_device pointer 622 * 623 * Tears down the driver GART/VM setup (CIK). 624 */ 625 static void gmc_v9_0_gart_fini(struct amdgpu_device *adev) 626 { 627 amdgpu_gart_table_vram_free(adev); 628 amdgpu_gart_fini(adev); 629 } 630 631 static int gmc_v9_0_sw_fini(void *handle) 632 { 633 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 634 635 if (adev->vm_manager.enabled) { 636 amdgpu_vm_manager_fini(adev); 637 gmc_v9_0_vm_fini(adev); 638 adev->vm_manager.enabled = false; 639 } 640 gmc_v9_0_gart_fini(adev); 641 amdgpu_gem_force_release(adev); 642 amdgpu_bo_fini(adev); 643 644 return 0; 645 } 646 647 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 648 { 649 switch (adev->asic_type) { 650 case CHIP_VEGA10: 651 break; 652 default: 653 break; 654 } 655 } 656 657 /** 658 * gmc_v9_0_gart_enable - gart enable 659 * 660 * @adev: amdgpu_device pointer 661 */ 662 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 663 { 664 int r; 665 bool value; 666 u32 tmp; 667 668 amdgpu_program_register_sequence(adev, 669 golden_settings_vega10_hdp, 670 (const u32)ARRAY_SIZE(golden_settings_vega10_hdp)); 671 672 if (adev->gart.robj == NULL) { 673 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 674 return -EINVAL; 675 } 676 r = amdgpu_gart_table_vram_pin(adev); 677 if (r) 678 return r; 679 680 /* After HDP is initialized, flush HDP.*/ 681 nbio_v6_1_hdp_flush(adev); 682 683 r = gfxhub_v1_0_gart_enable(adev); 684 if (r) 685 return r; 686 687 r = mmhub_v1_0_gart_enable(adev); 688 if (r) 689 return r; 690 691 tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL)); 692 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; 693 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL), tmp); 694 695 tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL)); 696 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL), tmp); 697 698 699 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 700 value = false; 701 else 702 value = true; 703 704 gfxhub_v1_0_set_fault_enable_default(adev, value); 705 mmhub_v1_0_set_fault_enable_default(adev, value); 706 707 gmc_v9_0_gart_flush_gpu_tlb(adev, 0); 708 709 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 710 (unsigned)(adev->mc.gtt_size >> 20), 711 (unsigned long long)adev->gart.table_addr); 712 adev->gart.ready = true; 713 return 0; 714 } 715 716 static int gmc_v9_0_hw_init(void *handle) 717 { 718 int r; 719 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 720 721 /* The sequence of these two function calls matters.*/ 722 gmc_v9_0_init_golden_registers(adev); 723 724 r = gmc_v9_0_gart_enable(adev); 725 726 return r; 727 } 728 729 /** 730 * gmc_v9_0_gart_disable - gart disable 731 * 732 * @adev: amdgpu_device pointer 733 * 734 * This disables all VM page table. 735 */ 736 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 737 { 738 gfxhub_v1_0_gart_disable(adev); 739 mmhub_v1_0_gart_disable(adev); 740 amdgpu_gart_table_vram_unpin(adev); 741 } 742 743 static int gmc_v9_0_hw_fini(void *handle) 744 { 745 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 746 747 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 748 gmc_v9_0_gart_disable(adev); 749 750 return 0; 751 } 752 753 static int gmc_v9_0_suspend(void *handle) 754 { 755 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 756 757 if (adev->vm_manager.enabled) { 758 gmc_v9_0_vm_fini(adev); 759 adev->vm_manager.enabled = false; 760 } 761 gmc_v9_0_hw_fini(adev); 762 763 return 0; 764 } 765 766 static int gmc_v9_0_resume(void *handle) 767 { 768 int r; 769 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 770 771 r = gmc_v9_0_hw_init(adev); 772 if (r) 773 return r; 774 775 if (!adev->vm_manager.enabled) { 776 r = gmc_v9_0_vm_init(adev); 777 if (r) { 778 dev_err(adev->dev, 779 "vm manager initialization failed (%d).\n", r); 780 return r; 781 } 782 adev->vm_manager.enabled = true; 783 } 784 785 return r; 786 } 787 788 static bool gmc_v9_0_is_idle(void *handle) 789 { 790 /* MC is always ready in GMC v9.*/ 791 return true; 792 } 793 794 static int gmc_v9_0_wait_for_idle(void *handle) 795 { 796 /* There is no need to wait for MC idle in GMC v9.*/ 797 return 0; 798 } 799 800 static int gmc_v9_0_soft_reset(void *handle) 801 { 802 /* XXX for emulation.*/ 803 return 0; 804 } 805 806 static int gmc_v9_0_set_clockgating_state(void *handle, 807 enum amd_clockgating_state state) 808 { 809 return 0; 810 } 811 812 static int gmc_v9_0_set_powergating_state(void *handle, 813 enum amd_powergating_state state) 814 { 815 return 0; 816 } 817 818 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 819 .name = "gmc_v9_0", 820 .early_init = gmc_v9_0_early_init, 821 .late_init = gmc_v9_0_late_init, 822 .sw_init = gmc_v9_0_sw_init, 823 .sw_fini = gmc_v9_0_sw_fini, 824 .hw_init = gmc_v9_0_hw_init, 825 .hw_fini = gmc_v9_0_hw_fini, 826 .suspend = gmc_v9_0_suspend, 827 .resume = gmc_v9_0_resume, 828 .is_idle = gmc_v9_0_is_idle, 829 .wait_for_idle = gmc_v9_0_wait_for_idle, 830 .soft_reset = gmc_v9_0_soft_reset, 831 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 832 .set_powergating_state = gmc_v9_0_set_powergating_state, 833 }; 834 835 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 836 { 837 .type = AMD_IP_BLOCK_TYPE_GMC, 838 .major = 9, 839 .minor = 0, 840 .rev = 0, 841 .funcs = &gmc_v9_0_ip_funcs, 842 }; 843