1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "umc_v12_0.h" 60 #include "hdp_v4_0.h" 61 #include "mca_v3_0.h" 62 63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 64 65 #include "amdgpu_ras.h" 66 #include "amdgpu_xgmi.h" 67 68 /* add these here since we already include dce12 headers and these are for DCN */ 69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 77 78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 80 81 static const char * const gfxhub_client_ids[] = { 82 "CB", 83 "DB", 84 "IA", 85 "WD", 86 "CPF", 87 "CPC", 88 "CPG", 89 "RLC", 90 "TCP", 91 "SQC (inst)", 92 "SQC (data)", 93 "SQG", 94 "PA", 95 }; 96 97 static const char *mmhub_client_ids_raven[][2] = { 98 [0][0] = "MP1", 99 [1][0] = "MP0", 100 [2][0] = "VCN", 101 [3][0] = "VCNU", 102 [4][0] = "HDP", 103 [5][0] = "DCE", 104 [13][0] = "UTCL2", 105 [19][0] = "TLS", 106 [26][0] = "OSS", 107 [27][0] = "SDMA0", 108 [0][1] = "MP1", 109 [1][1] = "MP0", 110 [2][1] = "VCN", 111 [3][1] = "VCNU", 112 [4][1] = "HDP", 113 [5][1] = "XDP", 114 [6][1] = "DBGU0", 115 [7][1] = "DCE", 116 [8][1] = "DCEDWB0", 117 [9][1] = "DCEDWB1", 118 [26][1] = "OSS", 119 [27][1] = "SDMA0", 120 }; 121 122 static const char *mmhub_client_ids_renoir[][2] = { 123 [0][0] = "MP1", 124 [1][0] = "MP0", 125 [2][0] = "HDP", 126 [4][0] = "DCEDMC", 127 [5][0] = "DCEVGA", 128 [13][0] = "UTCL2", 129 [19][0] = "TLS", 130 [26][0] = "OSS", 131 [27][0] = "SDMA0", 132 [28][0] = "VCN", 133 [29][0] = "VCNU", 134 [30][0] = "JPEG", 135 [0][1] = "MP1", 136 [1][1] = "MP0", 137 [2][1] = "HDP", 138 [3][1] = "XDP", 139 [6][1] = "DBGU0", 140 [7][1] = "DCEDMC", 141 [8][1] = "DCEVGA", 142 [9][1] = "DCEDWB", 143 [26][1] = "OSS", 144 [27][1] = "SDMA0", 145 [28][1] = "VCN", 146 [29][1] = "VCNU", 147 [30][1] = "JPEG", 148 }; 149 150 static const char *mmhub_client_ids_vega10[][2] = { 151 [0][0] = "MP0", 152 [1][0] = "UVD", 153 [2][0] = "UVDU", 154 [3][0] = "HDP", 155 [13][0] = "UTCL2", 156 [14][0] = "OSS", 157 [15][0] = "SDMA1", 158 [32+0][0] = "VCE0", 159 [32+1][0] = "VCE0U", 160 [32+2][0] = "XDMA", 161 [32+3][0] = "DCE", 162 [32+4][0] = "MP1", 163 [32+14][0] = "SDMA0", 164 [0][1] = "MP0", 165 [1][1] = "UVD", 166 [2][1] = "UVDU", 167 [3][1] = "DBGU0", 168 [4][1] = "HDP", 169 [5][1] = "XDP", 170 [14][1] = "OSS", 171 [15][1] = "SDMA0", 172 [32+0][1] = "VCE0", 173 [32+1][1] = "VCE0U", 174 [32+2][1] = "XDMA", 175 [32+3][1] = "DCE", 176 [32+4][1] = "DCEDWB", 177 [32+5][1] = "MP1", 178 [32+6][1] = "DBGU1", 179 [32+14][1] = "SDMA1", 180 }; 181 182 static const char *mmhub_client_ids_vega12[][2] = { 183 [0][0] = "MP0", 184 [1][0] = "VCE0", 185 [2][0] = "VCE0U", 186 [3][0] = "HDP", 187 [13][0] = "UTCL2", 188 [14][0] = "OSS", 189 [15][0] = "SDMA1", 190 [32+0][0] = "DCE", 191 [32+1][0] = "XDMA", 192 [32+2][0] = "UVD", 193 [32+3][0] = "UVDU", 194 [32+4][0] = "MP1", 195 [32+15][0] = "SDMA0", 196 [0][1] = "MP0", 197 [1][1] = "VCE0", 198 [2][1] = "VCE0U", 199 [3][1] = "DBGU0", 200 [4][1] = "HDP", 201 [5][1] = "XDP", 202 [14][1] = "OSS", 203 [15][1] = "SDMA0", 204 [32+0][1] = "DCE", 205 [32+1][1] = "DCEDWB", 206 [32+2][1] = "XDMA", 207 [32+3][1] = "UVD", 208 [32+4][1] = "UVDU", 209 [32+5][1] = "MP1", 210 [32+6][1] = "DBGU1", 211 [32+15][1] = "SDMA1", 212 }; 213 214 static const char *mmhub_client_ids_vega20[][2] = { 215 [0][0] = "XDMA", 216 [1][0] = "DCE", 217 [2][0] = "VCE0", 218 [3][0] = "VCE0U", 219 [4][0] = "UVD", 220 [5][0] = "UVD1U", 221 [13][0] = "OSS", 222 [14][0] = "HDP", 223 [15][0] = "SDMA0", 224 [32+0][0] = "UVD", 225 [32+1][0] = "UVDU", 226 [32+2][0] = "MP1", 227 [32+3][0] = "MP0", 228 [32+12][0] = "UTCL2", 229 [32+14][0] = "SDMA1", 230 [0][1] = "XDMA", 231 [1][1] = "DCE", 232 [2][1] = "DCEDWB", 233 [3][1] = "VCE0", 234 [4][1] = "VCE0U", 235 [5][1] = "UVD1", 236 [6][1] = "UVD1U", 237 [7][1] = "DBGU0", 238 [8][1] = "XDP", 239 [13][1] = "OSS", 240 [14][1] = "HDP", 241 [15][1] = "SDMA0", 242 [32+0][1] = "UVD", 243 [32+1][1] = "UVDU", 244 [32+2][1] = "DBGU1", 245 [32+3][1] = "MP1", 246 [32+4][1] = "MP0", 247 [32+14][1] = "SDMA1", 248 }; 249 250 static const char *mmhub_client_ids_arcturus[][2] = { 251 [0][0] = "DBGU1", 252 [1][0] = "XDP", 253 [2][0] = "MP1", 254 [14][0] = "HDP", 255 [171][0] = "JPEG", 256 [172][0] = "VCN", 257 [173][0] = "VCNU", 258 [203][0] = "JPEG1", 259 [204][0] = "VCN1", 260 [205][0] = "VCN1U", 261 [256][0] = "SDMA0", 262 [257][0] = "SDMA1", 263 [258][0] = "SDMA2", 264 [259][0] = "SDMA3", 265 [260][0] = "SDMA4", 266 [261][0] = "SDMA5", 267 [262][0] = "SDMA6", 268 [263][0] = "SDMA7", 269 [384][0] = "OSS", 270 [0][1] = "DBGU1", 271 [1][1] = "XDP", 272 [2][1] = "MP1", 273 [14][1] = "HDP", 274 [171][1] = "JPEG", 275 [172][1] = "VCN", 276 [173][1] = "VCNU", 277 [203][1] = "JPEG1", 278 [204][1] = "VCN1", 279 [205][1] = "VCN1U", 280 [256][1] = "SDMA0", 281 [257][1] = "SDMA1", 282 [258][1] = "SDMA2", 283 [259][1] = "SDMA3", 284 [260][1] = "SDMA4", 285 [261][1] = "SDMA5", 286 [262][1] = "SDMA6", 287 [263][1] = "SDMA7", 288 [384][1] = "OSS", 289 }; 290 291 static const char *mmhub_client_ids_aldebaran[][2] = { 292 [2][0] = "MP1", 293 [3][0] = "MP0", 294 [32+1][0] = "DBGU_IO0", 295 [32+2][0] = "DBGU_IO2", 296 [32+4][0] = "MPIO", 297 [96+11][0] = "JPEG0", 298 [96+12][0] = "VCN0", 299 [96+13][0] = "VCNU0", 300 [128+11][0] = "JPEG1", 301 [128+12][0] = "VCN1", 302 [128+13][0] = "VCNU1", 303 [160+1][0] = "XDP", 304 [160+14][0] = "HDP", 305 [256+0][0] = "SDMA0", 306 [256+1][0] = "SDMA1", 307 [256+2][0] = "SDMA2", 308 [256+3][0] = "SDMA3", 309 [256+4][0] = "SDMA4", 310 [384+0][0] = "OSS", 311 [2][1] = "MP1", 312 [3][1] = "MP0", 313 [32+1][1] = "DBGU_IO0", 314 [32+2][1] = "DBGU_IO2", 315 [32+4][1] = "MPIO", 316 [96+11][1] = "JPEG0", 317 [96+12][1] = "VCN0", 318 [96+13][1] = "VCNU0", 319 [128+11][1] = "JPEG1", 320 [128+12][1] = "VCN1", 321 [128+13][1] = "VCNU1", 322 [160+1][1] = "XDP", 323 [160+14][1] = "HDP", 324 [256+0][1] = "SDMA0", 325 [256+1][1] = "SDMA1", 326 [256+2][1] = "SDMA2", 327 [256+3][1] = "SDMA3", 328 [256+4][1] = "SDMA4", 329 [384+0][1] = "OSS", 330 }; 331 332 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { 333 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 334 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 335 }; 336 337 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { 338 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 339 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 340 }; 341 342 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 343 (0x000143c0 + 0x00000000), 344 (0x000143c0 + 0x00000800), 345 (0x000143c0 + 0x00001000), 346 (0x000143c0 + 0x00001800), 347 (0x000543c0 + 0x00000000), 348 (0x000543c0 + 0x00000800), 349 (0x000543c0 + 0x00001000), 350 (0x000543c0 + 0x00001800), 351 (0x000943c0 + 0x00000000), 352 (0x000943c0 + 0x00000800), 353 (0x000943c0 + 0x00001000), 354 (0x000943c0 + 0x00001800), 355 (0x000d43c0 + 0x00000000), 356 (0x000d43c0 + 0x00000800), 357 (0x000d43c0 + 0x00001000), 358 (0x000d43c0 + 0x00001800), 359 (0x001143c0 + 0x00000000), 360 (0x001143c0 + 0x00000800), 361 (0x001143c0 + 0x00001000), 362 (0x001143c0 + 0x00001800), 363 (0x001543c0 + 0x00000000), 364 (0x001543c0 + 0x00000800), 365 (0x001543c0 + 0x00001000), 366 (0x001543c0 + 0x00001800), 367 (0x001943c0 + 0x00000000), 368 (0x001943c0 + 0x00000800), 369 (0x001943c0 + 0x00001000), 370 (0x001943c0 + 0x00001800), 371 (0x001d43c0 + 0x00000000), 372 (0x001d43c0 + 0x00000800), 373 (0x001d43c0 + 0x00001000), 374 (0x001d43c0 + 0x00001800), 375 }; 376 377 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 378 (0x000143e0 + 0x00000000), 379 (0x000143e0 + 0x00000800), 380 (0x000143e0 + 0x00001000), 381 (0x000143e0 + 0x00001800), 382 (0x000543e0 + 0x00000000), 383 (0x000543e0 + 0x00000800), 384 (0x000543e0 + 0x00001000), 385 (0x000543e0 + 0x00001800), 386 (0x000943e0 + 0x00000000), 387 (0x000943e0 + 0x00000800), 388 (0x000943e0 + 0x00001000), 389 (0x000943e0 + 0x00001800), 390 (0x000d43e0 + 0x00000000), 391 (0x000d43e0 + 0x00000800), 392 (0x000d43e0 + 0x00001000), 393 (0x000d43e0 + 0x00001800), 394 (0x001143e0 + 0x00000000), 395 (0x001143e0 + 0x00000800), 396 (0x001143e0 + 0x00001000), 397 (0x001143e0 + 0x00001800), 398 (0x001543e0 + 0x00000000), 399 (0x001543e0 + 0x00000800), 400 (0x001543e0 + 0x00001000), 401 (0x001543e0 + 0x00001800), 402 (0x001943e0 + 0x00000000), 403 (0x001943e0 + 0x00000800), 404 (0x001943e0 + 0x00001000), 405 (0x001943e0 + 0x00001800), 406 (0x001d43e0 + 0x00000000), 407 (0x001d43e0 + 0x00000800), 408 (0x001d43e0 + 0x00001000), 409 (0x001d43e0 + 0x00001800), 410 }; 411 412 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 413 struct amdgpu_irq_src *src, 414 unsigned int type, 415 enum amdgpu_interrupt_state state) 416 { 417 u32 bits, i, tmp, reg; 418 419 /* Devices newer then VEGA10/12 shall have these programming 420 * sequences performed by PSP BL 421 */ 422 if (adev->asic_type >= CHIP_VEGA20) 423 return 0; 424 425 bits = 0x7f; 426 427 switch (state) { 428 case AMDGPU_IRQ_STATE_DISABLE: 429 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 430 reg = ecc_umc_mcumc_ctrl_addrs[i]; 431 tmp = RREG32(reg); 432 tmp &= ~bits; 433 WREG32(reg, tmp); 434 } 435 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 436 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 437 tmp = RREG32(reg); 438 tmp &= ~bits; 439 WREG32(reg, tmp); 440 } 441 break; 442 case AMDGPU_IRQ_STATE_ENABLE: 443 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 444 reg = ecc_umc_mcumc_ctrl_addrs[i]; 445 tmp = RREG32(reg); 446 tmp |= bits; 447 WREG32(reg, tmp); 448 } 449 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 450 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 451 tmp = RREG32(reg); 452 tmp |= bits; 453 WREG32(reg, tmp); 454 } 455 break; 456 default: 457 break; 458 } 459 460 return 0; 461 } 462 463 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 464 struct amdgpu_irq_src *src, 465 unsigned int type, 466 enum amdgpu_interrupt_state state) 467 { 468 struct amdgpu_vmhub *hub; 469 u32 tmp, reg, bits, i, j; 470 471 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 472 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 473 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 478 479 switch (state) { 480 case AMDGPU_IRQ_STATE_DISABLE: 481 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 482 hub = &adev->vmhub[j]; 483 for (i = 0; i < 16; i++) { 484 reg = hub->vm_context0_cntl + i; 485 486 /* This works because this interrupt is only 487 * enabled at init/resume and disabled in 488 * fini/suspend, so the overall state doesn't 489 * change over the course of suspend/resume. 490 */ 491 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 492 continue; 493 494 if (j >= AMDGPU_MMHUB0(0)) 495 tmp = RREG32_SOC15_IP(MMHUB, reg); 496 else 497 tmp = RREG32_XCC(reg, j); 498 499 tmp &= ~bits; 500 501 if (j >= AMDGPU_MMHUB0(0)) 502 WREG32_SOC15_IP(MMHUB, reg, tmp); 503 else 504 WREG32_XCC(reg, tmp, j); 505 } 506 } 507 break; 508 case AMDGPU_IRQ_STATE_ENABLE: 509 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 510 hub = &adev->vmhub[j]; 511 for (i = 0; i < 16; i++) { 512 reg = hub->vm_context0_cntl + i; 513 514 /* This works because this interrupt is only 515 * enabled at init/resume and disabled in 516 * fini/suspend, so the overall state doesn't 517 * change over the course of suspend/resume. 518 */ 519 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 520 continue; 521 522 if (j >= AMDGPU_MMHUB0(0)) 523 tmp = RREG32_SOC15_IP(MMHUB, reg); 524 else 525 tmp = RREG32_XCC(reg, j); 526 527 tmp |= bits; 528 529 if (j >= AMDGPU_MMHUB0(0)) 530 WREG32_SOC15_IP(MMHUB, reg, tmp); 531 else 532 WREG32_XCC(reg, tmp, j); 533 } 534 } 535 break; 536 default: 537 break; 538 } 539 540 return 0; 541 } 542 543 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 544 struct amdgpu_irq_src *source, 545 struct amdgpu_iv_entry *entry) 546 { 547 bool retry_fault = !!(entry->src_data[1] & 548 AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY); 549 bool write_fault = !!(entry->src_data[1] & 550 AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE); 551 uint32_t status = 0, cid = 0, rw = 0, fed = 0; 552 struct amdgpu_task_info *task_info; 553 struct amdgpu_vmhub *hub; 554 const char *mmhub_cid; 555 const char *hub_name; 556 unsigned int vmhub; 557 u64 addr; 558 uint32_t cam_index = 0; 559 int ret, xcc_id = 0; 560 uint32_t node_id; 561 562 node_id = entry->node_id; 563 564 addr = (u64)entry->src_data[0] << 12; 565 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 566 567 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 568 hub_name = "mmhub0"; 569 vmhub = AMDGPU_MMHUB0(node_id / 4); 570 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 571 hub_name = "mmhub1"; 572 vmhub = AMDGPU_MMHUB1(0); 573 } else { 574 hub_name = "gfxhub0"; 575 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 577 node_id); 578 if (xcc_id < 0) 579 xcc_id = 0; 580 } 581 vmhub = xcc_id; 582 } 583 hub = &adev->vmhub[vmhub]; 584 585 if (retry_fault) { 586 cam_index = entry->src_data[2] & 0x3ff; 587 588 ret = amdgpu_gmc_handle_retry_fault(adev, entry, addr, cam_index, node_id, 589 write_fault); 590 /* Returning 1 here also prevents sending the IV to the KFD */ 591 if (ret == 1) 592 return 1; 593 } 594 595 if (kgd2kfd_vmfault_fast_path(adev, entry, retry_fault)) 596 return 1; 597 598 if (!printk_ratelimit()) 599 return 0; 600 601 dev_err(adev->dev, 602 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name, 603 retry_fault ? "retry" : "no-retry", 604 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 605 606 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 607 if (task_info) { 608 amdgpu_vm_print_task_info(adev, task_info); 609 amdgpu_vm_put_task_info(task_info); 610 } 611 612 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 613 addr, entry->client_id, 614 soc15_ih_clientid_name[entry->client_id]); 615 616 if (amdgpu_is_multi_aid(adev)) 617 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 618 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 619 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 620 621 if (amdgpu_sriov_vf(adev)) 622 return 0; 623 624 /* 625 * Issue a dummy read to wait for the status register to 626 * be updated to avoid reading an incorrect value due to 627 * the new fast GRBM interface. 628 */ 629 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 630 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 631 RREG32(hub->vm_l2_pro_fault_status); 632 633 status = RREG32(hub->vm_l2_pro_fault_status); 634 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 635 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 636 fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED); 637 638 /* for fed error, kfd will handle it, return directly */ 639 if (fed && amdgpu_ras_is_poison_mode_supported(adev) && 640 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2))) 641 return 0; 642 643 /* Only print L2 fault status if the status register could be read and 644 * contains useful information 645 */ 646 if (!status) 647 return 0; 648 649 if (!amdgpu_sriov_vf(adev)) 650 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 651 652 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub); 653 654 dev_err(adev->dev, 655 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 656 status); 657 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 658 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 659 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 660 gfxhub_client_ids[cid], 661 cid); 662 } else { 663 mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); 664 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 665 mmhub_cid ? mmhub_cid : "unknown", cid); 666 } 667 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 668 REG_GET_FIELD(status, 669 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 670 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 671 REG_GET_FIELD(status, 672 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 673 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 674 REG_GET_FIELD(status, 675 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 676 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 677 REG_GET_FIELD(status, 678 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 679 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 680 return 0; 681 } 682 683 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 684 .set = gmc_v9_0_vm_fault_interrupt_state, 685 .process = gmc_v9_0_process_interrupt, 686 }; 687 688 689 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 690 .set = gmc_v9_0_ecc_interrupt_state, 691 .process = amdgpu_umc_process_ecc_irq, 692 }; 693 694 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 695 { 696 adev->gmc.vm_fault.num_types = 1; 697 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 698 699 if (!amdgpu_sriov_vf(adev) && 700 !adev->gmc.xgmi.connected_to_cpu && 701 !adev->gmc.is_app_apu) { 702 adev->gmc.ecc_irq.num_types = 1; 703 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 704 } 705 } 706 707 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 708 uint32_t flush_type) 709 { 710 u32 req = 0; 711 712 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 713 PER_VMID_INVALIDATE_REQ, 1 << vmid); 714 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 715 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 716 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 717 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 718 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 719 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 720 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 721 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 722 723 return req; 724 } 725 726 /** 727 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 728 * 729 * @adev: amdgpu_device pointer 730 * @vmhub: vmhub type 731 * 732 */ 733 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 734 uint32_t vmhub) 735 { 736 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 737 amdgpu_is_multi_aid(adev)) 738 return false; 739 740 return ((vmhub == AMDGPU_MMHUB0(0) || 741 vmhub == AMDGPU_MMHUB1(0)) && 742 (!amdgpu_sriov_vf(adev)) && 743 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 744 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 745 } 746 747 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 748 uint8_t vmid, uint16_t *p_pasid) 749 { 750 uint32_t value; 751 752 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 753 + vmid); 754 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 755 756 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 757 } 758 759 /* 760 * GART 761 * VMID 0 is the physical GPU addresses as used by the kernel. 762 * VMIDs 1-15 are used for userspace clients and are handled 763 * by the amdgpu vm/hsa code. 764 */ 765 766 /** 767 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 768 * 769 * @adev: amdgpu_device pointer 770 * @vmid: vm instance to flush 771 * @vmhub: which hub to flush 772 * @flush_type: the flush type 773 * 774 * Flush the TLB for the requested page table using certain type. 775 */ 776 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 777 uint32_t vmhub, uint32_t flush_type) 778 { 779 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 780 u32 j, inv_req, tmp, sem, req, ack, inst; 781 const unsigned int eng = 17; 782 struct amdgpu_vmhub *hub; 783 784 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 785 786 hub = &adev->vmhub[vmhub]; 787 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 788 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 789 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 790 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 791 792 if (vmhub >= AMDGPU_MMHUB0(0)) 793 inst = 0; 794 else 795 inst = vmhub; 796 797 /* This is necessary for SRIOV as well as for GFXOFF to function 798 * properly under bare metal 799 */ 800 if (adev->gfx.kiq[inst].ring.sched.ready && 801 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 802 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 803 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 804 805 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 806 1 << vmid, inst); 807 return; 808 } 809 810 /* This path is needed before KIQ/MES/GFXOFF are set up */ 811 spin_lock(&adev->gmc.invalidate_lock); 812 813 /* 814 * It may lose gpuvm invalidate acknowldege state across power-gating 815 * off cycle, add semaphore acquire before invalidation and semaphore 816 * release after invalidation to avoid entering power gated state 817 * to WA the Issue 818 */ 819 820 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 821 if (use_semaphore) { 822 for (j = 0; j < adev->usec_timeout; j++) { 823 /* a read return value of 1 means semaphore acquire */ 824 if (vmhub >= AMDGPU_MMHUB0(0)) 825 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst)); 826 else 827 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst)); 828 if (tmp & 0x1) 829 break; 830 udelay(1); 831 } 832 833 if (j >= adev->usec_timeout) 834 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 835 } 836 837 if (vmhub >= AMDGPU_MMHUB0(0)) 838 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst)); 839 else 840 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst)); 841 842 /* 843 * Issue a dummy read to wait for the ACK register to 844 * be cleared to avoid a false ACK due to the new fast 845 * GRBM interface. 846 */ 847 if ((vmhub == AMDGPU_GFXHUB(0)) && 848 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 849 RREG32_NO_KIQ(req); 850 851 for (j = 0; j < adev->usec_timeout; j++) { 852 if (vmhub >= AMDGPU_MMHUB0(0)) 853 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst)); 854 else 855 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst)); 856 if (tmp & (1 << vmid)) 857 break; 858 udelay(1); 859 } 860 861 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 862 if (use_semaphore) { 863 /* 864 * add semaphore release after invalidation, 865 * write with 0 means semaphore release 866 */ 867 if (vmhub >= AMDGPU_MMHUB0(0)) 868 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst)); 869 else 870 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst)); 871 } 872 873 spin_unlock(&adev->gmc.invalidate_lock); 874 875 if (j < adev->usec_timeout) 876 return; 877 878 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 879 } 880 881 /** 882 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 883 * 884 * @adev: amdgpu_device pointer 885 * @pasid: pasid to be flush 886 * @flush_type: the flush type 887 * @all_hub: flush all hubs 888 * @inst: is used to select which instance of KIQ to use for the invalidation 889 * 890 * Flush the TLB for the requested pasid. 891 */ 892 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 893 uint16_t pasid, uint32_t flush_type, 894 bool all_hub, uint32_t inst) 895 { 896 uint16_t queried; 897 int i, vmid; 898 899 for (vmid = 1; vmid < 16; vmid++) { 900 bool valid; 901 902 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 903 &queried); 904 if (!valid || queried != pasid) 905 continue; 906 907 if (all_hub) { 908 for_each_set_bit(i, adev->vmhubs_mask, 909 AMDGPU_MAX_VMHUBS) 910 gmc_v9_0_flush_gpu_tlb(adev, vmid, i, 911 flush_type); 912 } else { 913 gmc_v9_0_flush_gpu_tlb(adev, vmid, 914 AMDGPU_GFXHUB(0), 915 flush_type); 916 } 917 } 918 } 919 920 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 921 unsigned int vmid, uint64_t pd_addr) 922 { 923 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 924 struct amdgpu_device *adev = ring->adev; 925 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 926 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 927 unsigned int eng = ring->vm_inv_eng; 928 929 /* 930 * It may lose gpuvm invalidate acknowldege state across power-gating 931 * off cycle, add semaphore acquire before invalidation and semaphore 932 * release after invalidation to avoid entering power gated state 933 * to WA the Issue 934 */ 935 936 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 937 if (use_semaphore) 938 /* a read return value of 1 means semaphore acuqire */ 939 amdgpu_ring_emit_reg_wait(ring, 940 hub->vm_inv_eng0_sem + 941 hub->eng_distance * eng, 0x1, 0x1); 942 943 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 944 (hub->ctx_addr_distance * vmid), 945 lower_32_bits(pd_addr)); 946 947 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 948 (hub->ctx_addr_distance * vmid), 949 upper_32_bits(pd_addr)); 950 951 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 952 hub->eng_distance * eng, 953 hub->vm_inv_eng0_ack + 954 hub->eng_distance * eng, 955 req, 1 << vmid); 956 957 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 958 if (use_semaphore) 959 /* 960 * add semaphore release after invalidation, 961 * write with 0 means semaphore release 962 */ 963 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 964 hub->eng_distance * eng, 0); 965 966 return pd_addr; 967 } 968 969 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 970 unsigned int pasid) 971 { 972 struct amdgpu_device *adev = ring->adev; 973 uint32_t reg; 974 975 /* Do nothing because there's no lut register for mmhub1. */ 976 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 977 return; 978 979 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 980 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 981 else 982 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 983 984 amdgpu_ring_emit_wreg(ring, reg, pasid); 985 } 986 987 /* 988 * PTE format on VEGA 10: 989 * 63:59 reserved 990 * 58:57 mtype 991 * 56 F 992 * 55 L 993 * 54 P 994 * 53 SW 995 * 52 T 996 * 50:48 reserved 997 * 47:12 4k physical page base address 998 * 11:7 fragment 999 * 6 write 1000 * 5 read 1001 * 4 exe 1002 * 3 Z 1003 * 2 snooped 1004 * 1 system 1005 * 0 valid 1006 * 1007 * PDE format on VEGA 10: 1008 * 63:59 block fragment size 1009 * 58:55 reserved 1010 * 54 P 1011 * 53:48 reserved 1012 * 47:6 physical base address of PD or PTE 1013 * 5:3 reserved 1014 * 2 C 1015 * 1 system 1016 * 0 valid 1017 */ 1018 1019 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1020 uint64_t *addr, uint64_t *flags) 1021 { 1022 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1023 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1024 BUG_ON(*addr & 0xFFFF00000000003FULL); 1025 1026 if (!adev->gmc.translate_further) 1027 return; 1028 1029 if (level == AMDGPU_VM_PDB1) { 1030 /* Set the block fragment size */ 1031 if (!(*flags & AMDGPU_PDE_PTE)) 1032 *flags |= AMDGPU_PDE_BFS(0x9); 1033 1034 } else if (level == AMDGPU_VM_PDB0) { 1035 if (*flags & AMDGPU_PDE_PTE) { 1036 *flags &= ~AMDGPU_PDE_PTE; 1037 if (!(*flags & AMDGPU_PTE_VALID)) 1038 *addr |= 1 << PAGE_SHIFT; 1039 } else { 1040 *flags |= AMDGPU_PTE_TF; 1041 } 1042 } 1043 } 1044 1045 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1046 struct amdgpu_vm *vm, 1047 struct amdgpu_bo *bo, 1048 uint32_t vm_flags, 1049 uint64_t *flags) 1050 { 1051 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1052 bool is_vram = bo->tbo.resource && 1053 bo->tbo.resource->mem_type == TTM_PL_VRAM; 1054 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 1055 AMDGPU_GEM_CREATE_EXT_COHERENT); 1056 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; 1057 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1058 unsigned int mtype_local, mtype; 1059 uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); 1060 bool snoop = false; 1061 bool is_local; 1062 1063 dma_resv_assert_held(bo->tbo.base.resv); 1064 1065 switch (gc_ip_version) { 1066 case IP_VERSION(9, 4, 1): 1067 case IP_VERSION(9, 4, 2): 1068 if (is_vram) { 1069 if (bo_adev == adev) { 1070 if (uncached) 1071 mtype = MTYPE_UC; 1072 else if (coherent) 1073 mtype = MTYPE_CC; 1074 else 1075 mtype = MTYPE_RW; 1076 /* FIXME: is this still needed? Or does 1077 * amdgpu_ttm_tt_pde_flags already handle this? 1078 */ 1079 if (gc_ip_version == IP_VERSION(9, 4, 2) && 1080 adev->gmc.xgmi.connected_to_cpu) 1081 snoop = true; 1082 } else { 1083 if (uncached || coherent) 1084 mtype = MTYPE_UC; 1085 else 1086 mtype = MTYPE_NC; 1087 if (amdgpu_xgmi_same_hive(adev, bo_adev)) 1088 snoop = true; 1089 } 1090 } else { 1091 if (uncached || coherent) 1092 mtype = MTYPE_UC; 1093 else 1094 mtype = MTYPE_NC; 1095 /* FIXME: is this still needed? Or does 1096 * amdgpu_ttm_tt_pde_flags already handle this? 1097 */ 1098 snoop = true; 1099 } 1100 break; 1101 case IP_VERSION(9, 4, 3): 1102 case IP_VERSION(9, 4, 4): 1103 case IP_VERSION(9, 5, 0): 1104 /* Only local VRAM BOs or system memory on non-NUMA APUs 1105 * can be assumed to be local in their entirety. Choose 1106 * MTYPE_NC as safe fallback for all system memory BOs on 1107 * NUMA systems. Their MTYPE can be overridden per-page in 1108 * gmc_v9_0_override_vm_pte_flags. 1109 */ 1110 mtype_local = MTYPE_RW; 1111 if (amdgpu_mtype_local == 1) { 1112 drm_info_once(adev_to_drm(adev), "Using MTYPE_NC for local memory\n"); 1113 mtype_local = MTYPE_NC; 1114 } else if (amdgpu_mtype_local == 2) { 1115 drm_info_once(adev_to_drm(adev), "Using MTYPE_CC for local memory\n"); 1116 mtype_local = MTYPE_CC; 1117 } else { 1118 drm_info_once(adev_to_drm(adev), "Using MTYPE_RW for local memory\n"); 1119 } 1120 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1121 num_possible_nodes() <= 1) || 1122 (is_vram && adev == bo_adev && 1123 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id); 1124 snoop = true; 1125 if (uncached) { 1126 mtype = MTYPE_UC; 1127 } else if (ext_coherent) { 1128 mtype = is_local ? MTYPE_CC : MTYPE_UC; 1129 } else if (adev->flags & AMD_IS_APU) { 1130 mtype = is_local ? mtype_local : MTYPE_NC; 1131 } else { 1132 /* dGPU */ 1133 if (is_local) 1134 mtype = mtype_local; 1135 else if (gc_ip_version < IP_VERSION(9, 5, 0) && !is_vram) 1136 mtype = MTYPE_UC; 1137 else 1138 mtype = MTYPE_NC; 1139 } 1140 1141 break; 1142 default: 1143 if (uncached || coherent) 1144 mtype = MTYPE_UC; 1145 else 1146 mtype = MTYPE_NC; 1147 1148 /* FIXME: is this still needed? Or does 1149 * amdgpu_ttm_tt_pde_flags already handle this? 1150 */ 1151 if (!is_vram) 1152 snoop = true; 1153 } 1154 1155 if (mtype != MTYPE_NC) 1156 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype); 1157 1158 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1159 } 1160 1161 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1162 struct amdgpu_vm *vm, 1163 struct amdgpu_bo *bo, 1164 uint32_t vm_flags, 1165 uint64_t *flags) 1166 { 1167 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) 1168 *flags |= AMDGPU_PTE_EXECUTABLE; 1169 else 1170 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1171 1172 switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { 1173 case AMDGPU_VM_MTYPE_DEFAULT: 1174 case AMDGPU_VM_MTYPE_NC: 1175 default: 1176 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_NC); 1177 break; 1178 case AMDGPU_VM_MTYPE_WC: 1179 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_WC); 1180 break; 1181 case AMDGPU_VM_MTYPE_RW: 1182 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_RW); 1183 break; 1184 case AMDGPU_VM_MTYPE_CC: 1185 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC); 1186 break; 1187 case AMDGPU_VM_MTYPE_UC: 1188 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_UC); 1189 break; 1190 } 1191 1192 if (vm_flags & AMDGPU_VM_PAGE_PRT) { 1193 *flags |= AMDGPU_PTE_PRT; 1194 *flags &= ~AMDGPU_PTE_VALID; 1195 } 1196 1197 if ((*flags & AMDGPU_PTE_VALID) && bo) 1198 gmc_v9_0_get_coherence_flags(adev, vm, bo, vm_flags, flags); 1199 } 1200 1201 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1202 struct amdgpu_vm *vm, 1203 uint64_t addr, uint64_t *flags) 1204 { 1205 int local_node, nid; 1206 1207 /* MTYPE_NC is the same default and can be overridden. 1208 * MTYPE_UC will be present if the memory is extended-coherent 1209 * and can also be overridden. 1210 */ 1211 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1212 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC) && 1213 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1214 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC)) { 1215 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n"); 1216 return; 1217 } 1218 1219 if (vm->mem_id >= 0) { 1220 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1221 } else { 1222 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n"); 1223 return; 1224 } 1225 1226 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1227 * page or NUMA nodes. 1228 */ 1229 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1230 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n"); 1231 return; 1232 } 1233 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1234 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1235 vm->mem_id, local_node, nid); 1236 if (nid == local_node) { 1237 uint64_t old_flags = *flags; 1238 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) == 1239 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC)) { 1240 unsigned int mtype_local = MTYPE_RW; 1241 1242 if (amdgpu_mtype_local == 1) 1243 mtype_local = MTYPE_NC; 1244 else if (amdgpu_mtype_local == 2) 1245 mtype_local = MTYPE_CC; 1246 1247 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype_local); 1248 } else { 1249 /* MTYPE_UC case */ 1250 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC); 1251 } 1252 1253 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n", 1254 old_flags, *flags); 1255 } 1256 } 1257 1258 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1259 { 1260 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1261 unsigned int size; 1262 1263 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1264 1265 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1266 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1267 } else { 1268 u32 viewport; 1269 1270 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1271 case IP_VERSION(1, 0, 0): 1272 case IP_VERSION(1, 0, 1): 1273 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1274 size = (REG_GET_FIELD(viewport, 1275 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1276 REG_GET_FIELD(viewport, 1277 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1278 4); 1279 break; 1280 case IP_VERSION(2, 1, 0): 1281 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1282 size = (REG_GET_FIELD(viewport, 1283 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1284 REG_GET_FIELD(viewport, 1285 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1286 4); 1287 break; 1288 default: 1289 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1290 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1291 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1292 4); 1293 break; 1294 } 1295 } 1296 1297 return size; 1298 } 1299 1300 static bool gmc_v9_0_need_reset_on_init(struct amdgpu_device *adev) 1301 { 1302 if (adev->nbio.funcs && adev->nbio.funcs->is_nps_switch_requested && 1303 adev->nbio.funcs->is_nps_switch_requested(adev)) { 1304 adev->gmc.reset_flags |= AMDGPU_GMC_INIT_RESET_NPS; 1305 return true; 1306 } 1307 1308 return false; 1309 } 1310 1311 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1312 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1313 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1314 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1315 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1316 .get_vm_pde = gmc_v9_0_get_vm_pde, 1317 .get_vm_pte = gmc_v9_0_get_vm_pte, 1318 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1319 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1320 .query_mem_partition_mode = &amdgpu_gmc_query_memory_partition, 1321 .request_mem_partition_mode = &amdgpu_gmc_request_memory_partition, 1322 .need_reset_on_init = &gmc_v9_0_need_reset_on_init, 1323 }; 1324 1325 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1326 { 1327 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1328 1329 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes, local system 1330 * memory can use more efficient MTYPEs. 1331 * 1332 * APUs mapping system memory may need different MTYPEs on different 1333 * NUMA nodes. 1334 * 1335 * Only direct-mapped memory allows us to determine the NUMA node from 1336 * the DMA address. 1337 */ 1338 adev->gmc.override_pte = adev->gmc.is_app_apu && 1339 num_possible_nodes() > 1 && 1340 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 1341 adev->ram_is_direct_mapped; 1342 } 1343 1344 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1345 { 1346 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1347 case IP_VERSION(6, 0, 0): 1348 adev->umc.funcs = &umc_v6_0_funcs; 1349 break; 1350 case IP_VERSION(6, 1, 1): 1351 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1352 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1353 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1354 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1355 adev->umc.retire_unit = 1; 1356 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1357 adev->umc.ras = &umc_v6_1_ras; 1358 break; 1359 case IP_VERSION(6, 1, 2): 1360 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1361 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1362 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1363 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1364 adev->umc.retire_unit = 1; 1365 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1366 adev->umc.ras = &umc_v6_1_ras; 1367 break; 1368 case IP_VERSION(6, 7, 0): 1369 adev->umc.max_ras_err_cnt_per_query = 1370 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1371 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1372 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1373 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1374 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1375 if (!adev->gmc.xgmi.connected_to_cpu) 1376 adev->umc.ras = &umc_v6_7_ras; 1377 if (1 & adev->smuio.funcs->get_die_id(adev)) 1378 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1379 else 1380 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1381 break; 1382 case IP_VERSION(12, 0, 0): 1383 case IP_VERSION(12, 5, 0): 1384 adev->umc.max_ras_err_cnt_per_query = 1385 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1386 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM; 1387 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM; 1388 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM; 1389 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET; 1390 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1391 adev->umc.ras = &umc_v12_0_ras; 1392 break; 1393 default: 1394 break; 1395 } 1396 } 1397 1398 static void gmc_v9_0_init_mmhub_client_info(struct amdgpu_device *adev) 1399 { 1400 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1401 case IP_VERSION(9, 0, 0): 1402 amdgpu_mmhub_init_client_info(&adev->mmhub, 1403 mmhub_client_ids_vega10, 1404 ARRAY_SIZE(mmhub_client_ids_vega10)); 1405 break; 1406 case IP_VERSION(9, 3, 0): 1407 amdgpu_mmhub_init_client_info(&adev->mmhub, 1408 mmhub_client_ids_vega12, 1409 ARRAY_SIZE(mmhub_client_ids_vega12)); 1410 break; 1411 case IP_VERSION(9, 4, 0): 1412 amdgpu_mmhub_init_client_info(&adev->mmhub, 1413 mmhub_client_ids_vega20, 1414 ARRAY_SIZE(mmhub_client_ids_vega20)); 1415 break; 1416 case IP_VERSION(9, 4, 1): 1417 amdgpu_mmhub_init_client_info(&adev->mmhub, 1418 mmhub_client_ids_arcturus, 1419 ARRAY_SIZE(mmhub_client_ids_arcturus)); 1420 break; 1421 case IP_VERSION(9, 1, 0): 1422 case IP_VERSION(9, 2, 0): 1423 amdgpu_mmhub_init_client_info(&adev->mmhub, 1424 mmhub_client_ids_raven, 1425 ARRAY_SIZE(mmhub_client_ids_raven)); 1426 break; 1427 case IP_VERSION(1, 5, 0): 1428 case IP_VERSION(2, 4, 0): 1429 amdgpu_mmhub_init_client_info(&adev->mmhub, 1430 mmhub_client_ids_renoir, 1431 ARRAY_SIZE(mmhub_client_ids_renoir)); 1432 break; 1433 case IP_VERSION(1, 8, 0): 1434 case IP_VERSION(9, 4, 2): 1435 amdgpu_mmhub_init_client_info(&adev->mmhub, 1436 mmhub_client_ids_aldebaran, 1437 ARRAY_SIZE(mmhub_client_ids_aldebaran)); 1438 break; 1439 default: 1440 break; 1441 } 1442 } 1443 1444 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1445 { 1446 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1447 case IP_VERSION(9, 4, 1): 1448 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1449 break; 1450 case IP_VERSION(9, 4, 2): 1451 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1452 break; 1453 case IP_VERSION(1, 8, 0): 1454 case IP_VERSION(1, 8, 1): 1455 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1456 break; 1457 default: 1458 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1459 break; 1460 } 1461 1462 gmc_v9_0_init_mmhub_client_info(adev); 1463 } 1464 1465 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1466 { 1467 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1468 case IP_VERSION(9, 4, 0): 1469 adev->mmhub.ras = &mmhub_v1_0_ras; 1470 break; 1471 case IP_VERSION(9, 4, 1): 1472 adev->mmhub.ras = &mmhub_v9_4_ras; 1473 break; 1474 case IP_VERSION(9, 4, 2): 1475 adev->mmhub.ras = &mmhub_v1_7_ras; 1476 break; 1477 case IP_VERSION(1, 8, 0): 1478 case IP_VERSION(1, 8, 1): 1479 adev->mmhub.ras = &mmhub_v1_8_ras; 1480 break; 1481 default: 1482 /* mmhub ras is not available */ 1483 break; 1484 } 1485 } 1486 1487 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1488 { 1489 if (amdgpu_is_multi_aid(adev)) 1490 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1491 else 1492 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1493 } 1494 1495 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1496 { 1497 adev->hdp.ras = &hdp_v4_0_ras; 1498 } 1499 1500 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1501 { 1502 struct amdgpu_mca *mca = &adev->mca; 1503 1504 /* is UMC the right IP to check for MCA? Maybe DF? */ 1505 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1506 case IP_VERSION(6, 7, 0): 1507 if (!adev->gmc.xgmi.connected_to_cpu) { 1508 mca->mp0.ras = &mca_v3_0_mp0_ras; 1509 mca->mp1.ras = &mca_v3_0_mp1_ras; 1510 mca->mpio.ras = &mca_v3_0_mpio_ras; 1511 } 1512 break; 1513 default: 1514 break; 1515 } 1516 } 1517 1518 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1519 { 1520 if (!adev->gmc.xgmi.connected_to_cpu) 1521 adev->gmc.xgmi.ras = &xgmi_ras; 1522 } 1523 1524 static void gmc_v9_0_init_nps_details(struct amdgpu_device *adev) 1525 { 1526 enum amdgpu_memory_partition mode; 1527 uint32_t supp_modes; 1528 int i; 1529 1530 adev->gmc.supported_nps_modes = 0; 1531 1532 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 1533 return; 1534 1535 mode = amdgpu_gmc_get_memory_partition(adev, &supp_modes); 1536 1537 /* Mode detected by hardware and supported modes available */ 1538 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && supp_modes) { 1539 while ((i = ffs(supp_modes))) { 1540 if (AMDGPU_ALL_NPS_MASK & BIT(i)) 1541 adev->gmc.supported_nps_modes |= BIT(i); 1542 supp_modes &= supp_modes - 1; 1543 } 1544 } else { 1545 /*TODO: Check PSP version also which supports NPS switch. Otherwise keep 1546 * supported modes as 0. 1547 */ 1548 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1549 case IP_VERSION(9, 4, 3): 1550 case IP_VERSION(9, 4, 4): 1551 adev->gmc.supported_nps_modes = 1552 BIT(AMDGPU_NPS1_PARTITION_MODE) | 1553 BIT(AMDGPU_NPS4_PARTITION_MODE); 1554 break; 1555 default: 1556 break; 1557 } 1558 } 1559 } 1560 1561 static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block) 1562 { 1563 struct amdgpu_device *adev = ip_block->adev; 1564 1565 /* 1566 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1567 * in their IP discovery tables 1568 */ 1569 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) || 1570 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 1571 amdgpu_is_multi_aid(adev)) 1572 adev->gmc.xgmi.supported = true; 1573 1574 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) { 1575 adev->gmc.xgmi.supported = true; 1576 adev->gmc.xgmi.connected_to_cpu = 1577 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1578 } 1579 1580 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 1581 enum amdgpu_pkg_type pkg_type = 1582 adev->smuio.funcs->get_pkg_type(adev); 1583 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1584 * and the APU, can be in used two possible modes: 1585 * - carveout mode 1586 * - native APU mode 1587 * "is_app_apu" can be used to identify the APU in the native 1588 * mode. 1589 */ 1590 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1591 !pci_resource_len(adev->pdev, 0)); 1592 } 1593 1594 gmc_v9_0_set_gmc_funcs(adev); 1595 gmc_v9_0_set_irq_funcs(adev); 1596 gmc_v9_0_set_umc_funcs(adev); 1597 gmc_v9_0_set_mmhub_funcs(adev); 1598 gmc_v9_0_set_mmhub_ras_funcs(adev); 1599 gmc_v9_0_set_gfxhub_funcs(adev); 1600 gmc_v9_0_set_hdp_ras_funcs(adev); 1601 gmc_v9_0_set_mca_ras_funcs(adev); 1602 gmc_v9_0_set_xgmi_ras_funcs(adev); 1603 1604 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1605 adev->gmc.shared_aperture_end = 1606 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1607 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1608 adev->gmc.private_aperture_end = 1609 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1610 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1611 1612 return 0; 1613 } 1614 1615 static int gmc_v9_0_late_init(struct amdgpu_ip_block *ip_block) 1616 { 1617 struct amdgpu_device *adev = ip_block->adev; 1618 int r; 1619 1620 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1621 if (r) 1622 return r; 1623 1624 /* 1625 * Workaround performance drop issue with VBIOS enables partial 1626 * writes, while disables HBM ECC for vega10. 1627 */ 1628 if (!amdgpu_sriov_vf(adev) && 1629 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) { 1630 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1631 if (adev->df.funcs && 1632 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1633 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1634 } 1635 } 1636 1637 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1638 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB); 1639 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP); 1640 } 1641 1642 r = amdgpu_gmc_ras_late_init(adev); 1643 if (r) 1644 return r; 1645 1646 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1647 } 1648 1649 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1650 struct amdgpu_gmc *mc) 1651 { 1652 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1653 1654 amdgpu_gmc_set_agp_default(adev, mc); 1655 1656 /* add the xgmi offset of the physical node */ 1657 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1658 if (amdgpu_gmc_is_pdb0_enabled(adev)) { 1659 amdgpu_gmc_sysvm_location(adev, mc); 1660 } else { 1661 amdgpu_gmc_vram_location(adev, mc, base); 1662 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 1663 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 1664 amdgpu_gmc_agp_location(adev, mc); 1665 } 1666 /* base offset of vram pages */ 1667 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1668 1669 /* XXX: add the xgmi offset of the physical node? */ 1670 adev->vm_manager.vram_base_offset += 1671 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1672 } 1673 1674 /** 1675 * gmc_v9_0_mc_init - initialize the memory controller driver params 1676 * 1677 * @adev: amdgpu_device pointer 1678 * 1679 * Look up the amount of vram, vram width, and decide how to place 1680 * vram and gart within the GPU's physical address space. 1681 * Returns 0 for success. 1682 */ 1683 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1684 { 1685 int r; 1686 1687 /* size in MB on si */ 1688 if (!adev->gmc.is_app_apu) { 1689 adev->gmc.mc_vram_size = 1690 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1691 } else { 1692 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1693 adev->gmc.mc_vram_size = 0; 1694 } 1695 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1696 1697 if (!(adev->flags & AMD_IS_APU) && 1698 !adev->gmc.xgmi.connected_to_cpu) { 1699 r = amdgpu_device_resize_fb_bar(adev); 1700 if (r) 1701 return r; 1702 } 1703 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1704 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1705 1706 #ifdef CONFIG_X86_64 1707 /* 1708 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1709 * interface can use VRAM through here as it appears system reserved 1710 * memory in host address space. 1711 * 1712 * For APUs, VRAM is just the stolen system memory and can be accessed 1713 * directly. 1714 * 1715 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1716 */ 1717 1718 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1719 if ((!amdgpu_sriov_vf(adev) && 1720 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1721 (adev->gmc.xgmi.supported && 1722 adev->gmc.xgmi.connected_to_cpu)) { 1723 adev->gmc.aper_base = 1724 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1725 adev->gmc.xgmi.physical_node_id * 1726 adev->gmc.xgmi.node_segment_size; 1727 adev->gmc.aper_size = adev->gmc.real_vram_size; 1728 } 1729 1730 #endif 1731 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1732 1733 /* set the gart size */ 1734 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1735 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1736 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1737 case IP_VERSION(9, 3, 0): 1738 amdgpu_gmc_set_gart_size(adev, SZ_1G); 1739 break; 1740 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1741 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1742 case IP_VERSION(9, 4, 0): 1743 case IP_VERSION(9, 4, 1): 1744 case IP_VERSION(9, 4, 2): 1745 case IP_VERSION(9, 4, 3): 1746 case IP_VERSION(9, 4, 4): 1747 case IP_VERSION(9, 5, 0): 1748 default: 1749 amdgpu_gmc_set_gart_size(adev, SZ_512M); 1750 break; 1751 } 1752 1753 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1754 1755 return 0; 1756 } 1757 1758 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1759 { 1760 int r; 1761 1762 if (adev->gart.bo) { 1763 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1764 return 0; 1765 } 1766 1767 if (amdgpu_gmc_is_pdb0_enabled(adev)) { 1768 adev->gmc.vmid0_page_table_depth = 1; 1769 adev->gmc.vmid0_page_table_block_size = 12; 1770 } else { 1771 adev->gmc.vmid0_page_table_depth = 0; 1772 adev->gmc.vmid0_page_table_block_size = 0; 1773 } 1774 1775 /* Initialize common gart structure */ 1776 r = amdgpu_gart_init(adev); 1777 if (r) 1778 return r; 1779 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1780 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC) | 1781 AMDGPU_PTE_EXECUTABLE; 1782 1783 if (!adev->gmc.real_vram_size) { 1784 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1785 r = amdgpu_gart_table_ram_alloc(adev); 1786 if (r) 1787 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1788 } else { 1789 r = amdgpu_gart_table_vram_alloc(adev); 1790 if (r) 1791 return r; 1792 1793 if (amdgpu_gmc_is_pdb0_enabled(adev)) 1794 r = amdgpu_gmc_pdb0_alloc(adev); 1795 } 1796 1797 return r; 1798 } 1799 1800 /** 1801 * gmc_v9_0_save_registers - saves regs 1802 * 1803 * @adev: amdgpu_device pointer 1804 * 1805 * This saves potential register values that should be 1806 * restored upon resume 1807 */ 1808 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1809 { 1810 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1811 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) 1812 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1813 } 1814 1815 static void gmc_v9_0_init_vram_info(struct amdgpu_device *adev) 1816 { 1817 static const u32 regBIF_BIOS_SCRATCH_4 = 0x50; 1818 int dev_var = adev->pdev->device & 0xF; 1819 u32 vram_info; 1820 1821 if (adev->gmc.is_app_apu) { 1822 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1823 adev->gmc.vram_width = 128 * 64; 1824 } else if (adev->flags & AMD_IS_APU) { 1825 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 1826 adev->gmc.vram_width = 64 * 64; 1827 } else if (amdgpu_is_multi_aid(adev)) { 1828 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1829 adev->gmc.vram_width = 128 * 64; 1830 1831 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 1832 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; 1833 1834 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) && 1835 adev->rev_id == 0x3) 1836 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; 1837 1838 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 1839 (dev_var == 0x5)) 1840 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; 1841 1842 if (!(adev->flags & AMD_IS_APU) && !amdgpu_sriov_vf(adev)) { 1843 vram_info = RREG32(regBIF_BIOS_SCRATCH_4); 1844 adev->gmc.vram_vendor = vram_info & 0xF; 1845 } 1846 } 1847 } 1848 1849 static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) 1850 { 1851 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 1852 struct amdgpu_device *adev = ip_block->adev; 1853 unsigned long inst_mask = adev->aid_mask; 1854 1855 adev->gfxhub.funcs->init(adev); 1856 1857 adev->mmhub.funcs->init(adev); 1858 1859 spin_lock_init(&adev->gmc.invalidate_lock); 1860 1861 if (!adev->bios) { 1862 gmc_v9_0_init_vram_info(adev); 1863 } else { 1864 r = amdgpu_gmc_get_vram_info(adev, 1865 &vram_width, &vram_type, &vram_vendor); 1866 if (amdgpu_sriov_vf(adev)) 1867 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1868 * and DF related registers is not readable, seems hardcord is the 1869 * only way to set the correct vram_width 1870 */ 1871 adev->gmc.vram_width = 2048; 1872 else if (amdgpu_emu_mode != 1) 1873 adev->gmc.vram_width = vram_width; 1874 1875 if (!adev->gmc.vram_width) { 1876 int chansize, numchan; 1877 1878 /* hbm memory channel size */ 1879 if (adev->flags & AMD_IS_APU) 1880 chansize = 64; 1881 else 1882 chansize = 128; 1883 if (adev->df.funcs && 1884 adev->df.funcs->get_hbm_channel_number) { 1885 numchan = adev->df.funcs->get_hbm_channel_number(adev); 1886 adev->gmc.vram_width = numchan * chansize; 1887 } 1888 } 1889 1890 adev->gmc.vram_type = vram_type; 1891 adev->gmc.vram_vendor = vram_vendor; 1892 } 1893 1894 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1895 case IP_VERSION(9, 1, 0): 1896 case IP_VERSION(9, 2, 2): 1897 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1898 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1899 1900 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1901 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1902 } else { 1903 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1904 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1905 adev->gmc.translate_further = 1906 adev->vm_manager.num_level > 1; 1907 } 1908 break; 1909 case IP_VERSION(9, 0, 1): 1910 case IP_VERSION(9, 2, 1): 1911 case IP_VERSION(9, 4, 0): 1912 case IP_VERSION(9, 3, 0): 1913 case IP_VERSION(9, 4, 2): 1914 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1915 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1916 1917 /* 1918 * To fulfill 4-level page support, 1919 * vm size is 256TB (48bit), maximum size of Vega10, 1920 * block size 512 (9bit) 1921 */ 1922 1923 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1924 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 1925 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1926 break; 1927 case IP_VERSION(9, 4, 1): 1928 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1929 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1930 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 1931 1932 /* Keep the vm size same with Vega20 */ 1933 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1934 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1935 break; 1936 case IP_VERSION(9, 4, 3): 1937 case IP_VERSION(9, 4, 4): 1938 case IP_VERSION(9, 5, 0): 1939 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 1940 NUM_XCC(adev->gfx.xcc_mask)); 1941 1942 inst_mask <<= AMDGPU_MMHUB0(0); 1943 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 1944 1945 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1946 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1947 break; 1948 default: 1949 break; 1950 } 1951 1952 /* This interrupt is VMC page fault.*/ 1953 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1954 &adev->gmc.vm_fault); 1955 if (r) 1956 return r; 1957 1958 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) { 1959 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1960 &adev->gmc.vm_fault); 1961 if (r) 1962 return r; 1963 } 1964 1965 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1966 &adev->gmc.vm_fault); 1967 1968 if (r) 1969 return r; 1970 1971 if (!amdgpu_sriov_vf(adev) && 1972 !adev->gmc.xgmi.connected_to_cpu && 1973 !adev->gmc.is_app_apu) { 1974 /* interrupt sent to DF. */ 1975 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1976 &adev->gmc.ecc_irq); 1977 if (r) 1978 return r; 1979 } 1980 1981 /* Set the internal MC address mask 1982 * This is the max address of the GPU's 1983 * internal address space. 1984 */ 1985 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1986 1987 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= 1988 IP_VERSION(9, 4, 2) ? 1989 48 : 1990 44; 1991 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 1992 if (r) { 1993 drm_warn(adev_to_drm(adev), "No suitable DMA available.\n"); 1994 return r; 1995 } 1996 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 1997 1998 r = gmc_v9_0_mc_init(adev); 1999 if (r) 2000 return r; 2001 2002 if (amdgpu_is_multi_aid(adev)) { 2003 r = amdgpu_gmc_init_mem_ranges(adev); 2004 if (r) 2005 return r; 2006 } 2007 2008 /* Memory manager */ 2009 r = amdgpu_bo_init(adev); 2010 if (r) 2011 return r; 2012 2013 r = gmc_v9_0_gart_init(adev); 2014 if (r) 2015 return r; 2016 2017 gmc_v9_0_init_nps_details(adev); 2018 /* 2019 * number of VMs 2020 * VMID 0 is reserved for System 2021 * amdgpu graphics/compute will use VMIDs 1..n-1 2022 * amdkfd will use VMIDs n..15 2023 * 2024 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2025 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2026 * for video processing. 2027 */ 2028 adev->vm_manager.first_kfd_vmid = 2029 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 2030 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 2031 amdgpu_is_multi_aid(adev)) ? 2032 3 : 2033 8; 2034 2035 amdgpu_vm_manager_init(adev); 2036 2037 gmc_v9_0_save_registers(adev); 2038 2039 r = amdgpu_gmc_ras_sw_init(adev); 2040 if (r) 2041 return r; 2042 2043 if (amdgpu_is_multi_aid(adev)) 2044 amdgpu_gmc_sysfs_init(adev); 2045 2046 return 0; 2047 } 2048 2049 static int gmc_v9_0_sw_fini(struct amdgpu_ip_block *ip_block) 2050 { 2051 struct amdgpu_device *adev = ip_block->adev; 2052 2053 if (amdgpu_is_multi_aid(adev)) 2054 amdgpu_gmc_sysfs_fini(adev); 2055 2056 amdgpu_gmc_ras_fini(adev); 2057 amdgpu_gem_force_release(adev); 2058 amdgpu_vm_manager_fini(adev); 2059 if (!adev->gmc.real_vram_size) { 2060 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2061 amdgpu_gart_table_ram_free(adev); 2062 } else { 2063 amdgpu_gart_table_vram_free(adev); 2064 } 2065 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2066 amdgpu_bo_fini(adev); 2067 2068 adev->gmc.num_mem_partitions = 0; 2069 kfree(adev->gmc.mem_partitions); 2070 2071 return 0; 2072 } 2073 2074 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2075 { 2076 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 2077 case IP_VERSION(9, 0, 0): 2078 if (amdgpu_sriov_vf(adev)) 2079 break; 2080 fallthrough; 2081 case IP_VERSION(9, 4, 0): 2082 soc15_program_register_sequence(adev, 2083 golden_settings_mmhub_1_0_0, 2084 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2085 soc15_program_register_sequence(adev, 2086 golden_settings_athub_1_0_0, 2087 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2088 break; 2089 case IP_VERSION(9, 1, 0): 2090 case IP_VERSION(9, 2, 0): 2091 /* TODO for renoir */ 2092 soc15_program_register_sequence(adev, 2093 golden_settings_athub_1_0_0, 2094 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2095 break; 2096 default: 2097 break; 2098 } 2099 } 2100 2101 /** 2102 * gmc_v9_0_restore_registers - restores regs 2103 * 2104 * @adev: amdgpu_device pointer 2105 * 2106 * This restores register values, saved at suspend. 2107 */ 2108 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2109 { 2110 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 2111 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) { 2112 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2113 WARN_ON(adev->gmc.sdpif_register != 2114 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2115 } 2116 } 2117 2118 /** 2119 * gmc_v9_0_gart_enable - gart enable 2120 * 2121 * @adev: amdgpu_device pointer 2122 */ 2123 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2124 { 2125 int r; 2126 2127 if (amdgpu_gmc_is_pdb0_enabled(adev)) 2128 amdgpu_gmc_init_pdb0(adev); 2129 2130 if (adev->gart.bo == NULL) { 2131 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2132 return -EINVAL; 2133 } 2134 2135 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2136 2137 if (!adev->in_s0ix) { 2138 r = adev->gfxhub.funcs->gart_enable(adev); 2139 if (r) 2140 return r; 2141 } 2142 2143 r = adev->mmhub.funcs->gart_enable(adev); 2144 if (r) 2145 return r; 2146 2147 drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled.\n", 2148 (unsigned int)(adev->gmc.gart_size >> 20)); 2149 if (adev->gmc.pdb0_bo) 2150 drm_info(adev_to_drm(adev), "PDB0 located at 0x%016llX\n", 2151 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2152 drm_info(adev_to_drm(adev), "PTB located at 0x%016llX\n", 2153 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2154 2155 return 0; 2156 } 2157 2158 static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block) 2159 { 2160 struct amdgpu_device *adev = ip_block->adev; 2161 bool value; 2162 int i, r; 2163 2164 adev->gmc.flush_pasid_uses_kiq = true; 2165 2166 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush 2167 * (type 2), which flushes both. Due to a race condition with 2168 * concurrent memory accesses using the same TLB cache line, we still 2169 * need a second TLB flush after this. 2170 */ 2171 adev->gmc.flush_tlb_needs_extra_type_2 = 2172 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) && 2173 adev->gmc.xgmi.num_physical_nodes; 2174 2175 /* The sequence of these two function calls matters.*/ 2176 gmc_v9_0_init_golden_registers(adev); 2177 2178 if (adev->mode_info.num_crtc) { 2179 /* Lockout access through VGA aperture*/ 2180 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2181 /* disable VGA render */ 2182 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2183 } 2184 2185 if (adev->mmhub.funcs->update_power_gating) 2186 adev->mmhub.funcs->update_power_gating(adev, true); 2187 2188 adev->hdp.funcs->init_registers(adev); 2189 2190 /* After HDP is initialized, flush HDP.*/ 2191 amdgpu_device_flush_hdp(adev, NULL); 2192 2193 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2194 value = false; 2195 else 2196 value = true; 2197 2198 if (!amdgpu_sriov_vf(adev)) { 2199 if (!adev->in_s0ix) 2200 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2201 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2202 } 2203 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2204 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2205 continue; 2206 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2207 } 2208 2209 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2210 adev->umc.funcs->init_registers(adev); 2211 2212 r = gmc_v9_0_gart_enable(adev); 2213 if (r) 2214 return r; 2215 2216 if (amdgpu_emu_mode == 1) 2217 return amdgpu_gmc_vram_checking(adev); 2218 2219 return 0; 2220 } 2221 2222 /** 2223 * gmc_v9_0_gart_disable - gart disable 2224 * 2225 * @adev: amdgpu_device pointer 2226 * 2227 * This disables all VM page table. 2228 */ 2229 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2230 { 2231 if (!adev->in_s0ix) 2232 adev->gfxhub.funcs->gart_disable(adev); 2233 adev->mmhub.funcs->gart_disable(adev); 2234 } 2235 2236 static int gmc_v9_0_hw_fini(struct amdgpu_ip_block *ip_block) 2237 { 2238 struct amdgpu_device *adev = ip_block->adev; 2239 2240 gmc_v9_0_gart_disable(adev); 2241 2242 if (amdgpu_sriov_vf(adev)) { 2243 /* full access mode, so don't touch any GMC register */ 2244 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2245 return 0; 2246 } 2247 2248 /* 2249 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2250 * a correct cached state for GMC. Otherwise, the "gate" again 2251 * operation on S3 resuming will fail due to wrong cached state. 2252 */ 2253 if (adev->mmhub.funcs->update_power_gating) 2254 adev->mmhub.funcs->update_power_gating(adev, false); 2255 2256 /* 2257 * For minimal init, late_init is not called, hence VM fault/RAS irqs 2258 * are not enabled. 2259 */ 2260 if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { 2261 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2262 2263 if (adev->gmc.ecc_irq.funcs && 2264 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2265 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 2266 } 2267 2268 return 0; 2269 } 2270 2271 static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block) 2272 { 2273 return gmc_v9_0_hw_fini(ip_block); 2274 } 2275 2276 static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block) 2277 { 2278 struct amdgpu_device *adev = ip_block->adev; 2279 int r; 2280 2281 /* If a reset is done for NPS mode switch, read the memory range 2282 * information again. 2283 */ 2284 if (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS) { 2285 amdgpu_gmc_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 2286 adev->gmc.reset_flags &= ~AMDGPU_GMC_INIT_RESET_NPS; 2287 } 2288 2289 r = gmc_v9_0_hw_init(ip_block); 2290 if (r) 2291 return r; 2292 2293 amdgpu_vmid_reset_all(ip_block->adev); 2294 2295 return 0; 2296 } 2297 2298 static bool gmc_v9_0_is_idle(struct amdgpu_ip_block *ip_block) 2299 { 2300 /* MC is always ready in GMC v9.*/ 2301 return true; 2302 } 2303 2304 static int gmc_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 2305 { 2306 /* There is no need to wait for MC idle in GMC v9.*/ 2307 return 0; 2308 } 2309 2310 static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block) 2311 { 2312 /* XXX for emulation.*/ 2313 return 0; 2314 } 2315 2316 static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2317 enum amd_clockgating_state state) 2318 { 2319 struct amdgpu_device *adev = ip_block->adev; 2320 2321 adev->mmhub.funcs->set_clockgating(adev, state); 2322 2323 athub_v1_0_set_clockgating(adev, state); 2324 2325 return 0; 2326 } 2327 2328 static void gmc_v9_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2329 { 2330 struct amdgpu_device *adev = ip_block->adev; 2331 2332 adev->mmhub.funcs->get_clockgating(adev, flags); 2333 2334 athub_v1_0_get_clockgating(adev, flags); 2335 } 2336 2337 static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 2338 enum amd_powergating_state state) 2339 { 2340 return 0; 2341 } 2342 2343 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2344 .name = "gmc_v9_0", 2345 .early_init = gmc_v9_0_early_init, 2346 .late_init = gmc_v9_0_late_init, 2347 .sw_init = gmc_v9_0_sw_init, 2348 .sw_fini = gmc_v9_0_sw_fini, 2349 .hw_init = gmc_v9_0_hw_init, 2350 .hw_fini = gmc_v9_0_hw_fini, 2351 .suspend = gmc_v9_0_suspend, 2352 .resume = gmc_v9_0_resume, 2353 .is_idle = gmc_v9_0_is_idle, 2354 .wait_for_idle = gmc_v9_0_wait_for_idle, 2355 .soft_reset = gmc_v9_0_soft_reset, 2356 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2357 .set_powergating_state = gmc_v9_0_set_powergating_state, 2358 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2359 }; 2360 2361 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = { 2362 .type = AMD_IP_BLOCK_TYPE_GMC, 2363 .major = 9, 2364 .minor = 0, 2365 .rev = 0, 2366 .funcs = &gmc_v9_0_ip_funcs, 2367 }; 2368