1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "umc_v12_0.h" 60 #include "hdp_v4_0.h" 61 #include "mca_v3_0.h" 62 63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 64 65 #include "amdgpu_ras.h" 66 #include "amdgpu_xgmi.h" 67 68 /* add these here since we already include dce12 headers and these are for DCN */ 69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 77 78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 80 81 static const char * const gfxhub_client_ids[] = { 82 "CB", 83 "DB", 84 "IA", 85 "WD", 86 "CPF", 87 "CPC", 88 "CPG", 89 "RLC", 90 "TCP", 91 "SQC (inst)", 92 "SQC (data)", 93 "SQG", 94 "PA", 95 }; 96 97 static const char *mmhub_client_ids_raven[][2] = { 98 [0][0] = "MP1", 99 [1][0] = "MP0", 100 [2][0] = "VCN", 101 [3][0] = "VCNU", 102 [4][0] = "HDP", 103 [5][0] = "DCE", 104 [13][0] = "UTCL2", 105 [19][0] = "TLS", 106 [26][0] = "OSS", 107 [27][0] = "SDMA0", 108 [0][1] = "MP1", 109 [1][1] = "MP0", 110 [2][1] = "VCN", 111 [3][1] = "VCNU", 112 [4][1] = "HDP", 113 [5][1] = "XDP", 114 [6][1] = "DBGU0", 115 [7][1] = "DCE", 116 [8][1] = "DCEDWB0", 117 [9][1] = "DCEDWB1", 118 [26][1] = "OSS", 119 [27][1] = "SDMA0", 120 }; 121 122 static const char *mmhub_client_ids_renoir[][2] = { 123 [0][0] = "MP1", 124 [1][0] = "MP0", 125 [2][0] = "HDP", 126 [4][0] = "DCEDMC", 127 [5][0] = "DCEVGA", 128 [13][0] = "UTCL2", 129 [19][0] = "TLS", 130 [26][0] = "OSS", 131 [27][0] = "SDMA0", 132 [28][0] = "VCN", 133 [29][0] = "VCNU", 134 [30][0] = "JPEG", 135 [0][1] = "MP1", 136 [1][1] = "MP0", 137 [2][1] = "HDP", 138 [3][1] = "XDP", 139 [6][1] = "DBGU0", 140 [7][1] = "DCEDMC", 141 [8][1] = "DCEVGA", 142 [9][1] = "DCEDWB", 143 [26][1] = "OSS", 144 [27][1] = "SDMA0", 145 [28][1] = "VCN", 146 [29][1] = "VCNU", 147 [30][1] = "JPEG", 148 }; 149 150 static const char *mmhub_client_ids_vega10[][2] = { 151 [0][0] = "MP0", 152 [1][0] = "UVD", 153 [2][0] = "UVDU", 154 [3][0] = "HDP", 155 [13][0] = "UTCL2", 156 [14][0] = "OSS", 157 [15][0] = "SDMA1", 158 [32+0][0] = "VCE0", 159 [32+1][0] = "VCE0U", 160 [32+2][0] = "XDMA", 161 [32+3][0] = "DCE", 162 [32+4][0] = "MP1", 163 [32+14][0] = "SDMA0", 164 [0][1] = "MP0", 165 [1][1] = "UVD", 166 [2][1] = "UVDU", 167 [3][1] = "DBGU0", 168 [4][1] = "HDP", 169 [5][1] = "XDP", 170 [14][1] = "OSS", 171 [15][1] = "SDMA0", 172 [32+0][1] = "VCE0", 173 [32+1][1] = "VCE0U", 174 [32+2][1] = "XDMA", 175 [32+3][1] = "DCE", 176 [32+4][1] = "DCEDWB", 177 [32+5][1] = "MP1", 178 [32+6][1] = "DBGU1", 179 [32+14][1] = "SDMA1", 180 }; 181 182 static const char *mmhub_client_ids_vega12[][2] = { 183 [0][0] = "MP0", 184 [1][0] = "VCE0", 185 [2][0] = "VCE0U", 186 [3][0] = "HDP", 187 [13][0] = "UTCL2", 188 [14][0] = "OSS", 189 [15][0] = "SDMA1", 190 [32+0][0] = "DCE", 191 [32+1][0] = "XDMA", 192 [32+2][0] = "UVD", 193 [32+3][0] = "UVDU", 194 [32+4][0] = "MP1", 195 [32+15][0] = "SDMA0", 196 [0][1] = "MP0", 197 [1][1] = "VCE0", 198 [2][1] = "VCE0U", 199 [3][1] = "DBGU0", 200 [4][1] = "HDP", 201 [5][1] = "XDP", 202 [14][1] = "OSS", 203 [15][1] = "SDMA0", 204 [32+0][1] = "DCE", 205 [32+1][1] = "DCEDWB", 206 [32+2][1] = "XDMA", 207 [32+3][1] = "UVD", 208 [32+4][1] = "UVDU", 209 [32+5][1] = "MP1", 210 [32+6][1] = "DBGU1", 211 [32+15][1] = "SDMA1", 212 }; 213 214 static const char *mmhub_client_ids_vega20[][2] = { 215 [0][0] = "XDMA", 216 [1][0] = "DCE", 217 [2][0] = "VCE0", 218 [3][0] = "VCE0U", 219 [4][0] = "UVD", 220 [5][0] = "UVD1U", 221 [13][0] = "OSS", 222 [14][0] = "HDP", 223 [15][0] = "SDMA0", 224 [32+0][0] = "UVD", 225 [32+1][0] = "UVDU", 226 [32+2][0] = "MP1", 227 [32+3][0] = "MP0", 228 [32+12][0] = "UTCL2", 229 [32+14][0] = "SDMA1", 230 [0][1] = "XDMA", 231 [1][1] = "DCE", 232 [2][1] = "DCEDWB", 233 [3][1] = "VCE0", 234 [4][1] = "VCE0U", 235 [5][1] = "UVD1", 236 [6][1] = "UVD1U", 237 [7][1] = "DBGU0", 238 [8][1] = "XDP", 239 [13][1] = "OSS", 240 [14][1] = "HDP", 241 [15][1] = "SDMA0", 242 [32+0][1] = "UVD", 243 [32+1][1] = "UVDU", 244 [32+2][1] = "DBGU1", 245 [32+3][1] = "MP1", 246 [32+4][1] = "MP0", 247 [32+14][1] = "SDMA1", 248 }; 249 250 static const char *mmhub_client_ids_arcturus[][2] = { 251 [0][0] = "DBGU1", 252 [1][0] = "XDP", 253 [2][0] = "MP1", 254 [14][0] = "HDP", 255 [171][0] = "JPEG", 256 [172][0] = "VCN", 257 [173][0] = "VCNU", 258 [203][0] = "JPEG1", 259 [204][0] = "VCN1", 260 [205][0] = "VCN1U", 261 [256][0] = "SDMA0", 262 [257][0] = "SDMA1", 263 [258][0] = "SDMA2", 264 [259][0] = "SDMA3", 265 [260][0] = "SDMA4", 266 [261][0] = "SDMA5", 267 [262][0] = "SDMA6", 268 [263][0] = "SDMA7", 269 [384][0] = "OSS", 270 [0][1] = "DBGU1", 271 [1][1] = "XDP", 272 [2][1] = "MP1", 273 [14][1] = "HDP", 274 [171][1] = "JPEG", 275 [172][1] = "VCN", 276 [173][1] = "VCNU", 277 [203][1] = "JPEG1", 278 [204][1] = "VCN1", 279 [205][1] = "VCN1U", 280 [256][1] = "SDMA0", 281 [257][1] = "SDMA1", 282 [258][1] = "SDMA2", 283 [259][1] = "SDMA3", 284 [260][1] = "SDMA4", 285 [261][1] = "SDMA5", 286 [262][1] = "SDMA6", 287 [263][1] = "SDMA7", 288 [384][1] = "OSS", 289 }; 290 291 static const char *mmhub_client_ids_aldebaran[][2] = { 292 [2][0] = "MP1", 293 [3][0] = "MP0", 294 [32+1][0] = "DBGU_IO0", 295 [32+2][0] = "DBGU_IO2", 296 [32+4][0] = "MPIO", 297 [96+11][0] = "JPEG0", 298 [96+12][0] = "VCN0", 299 [96+13][0] = "VCNU0", 300 [128+11][0] = "JPEG1", 301 [128+12][0] = "VCN1", 302 [128+13][0] = "VCNU1", 303 [160+1][0] = "XDP", 304 [160+14][0] = "HDP", 305 [256+0][0] = "SDMA0", 306 [256+1][0] = "SDMA1", 307 [256+2][0] = "SDMA2", 308 [256+3][0] = "SDMA3", 309 [256+4][0] = "SDMA4", 310 [384+0][0] = "OSS", 311 [2][1] = "MP1", 312 [3][1] = "MP0", 313 [32+1][1] = "DBGU_IO0", 314 [32+2][1] = "DBGU_IO2", 315 [32+4][1] = "MPIO", 316 [96+11][1] = "JPEG0", 317 [96+12][1] = "VCN0", 318 [96+13][1] = "VCNU0", 319 [128+11][1] = "JPEG1", 320 [128+12][1] = "VCN1", 321 [128+13][1] = "VCNU1", 322 [160+1][1] = "XDP", 323 [160+14][1] = "HDP", 324 [256+0][1] = "SDMA0", 325 [256+1][1] = "SDMA1", 326 [256+2][1] = "SDMA2", 327 [256+3][1] = "SDMA3", 328 [256+4][1] = "SDMA4", 329 [384+0][1] = "OSS", 330 }; 331 332 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { 333 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 334 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 335 }; 336 337 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { 338 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 339 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 340 }; 341 342 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 343 (0x000143c0 + 0x00000000), 344 (0x000143c0 + 0x00000800), 345 (0x000143c0 + 0x00001000), 346 (0x000143c0 + 0x00001800), 347 (0x000543c0 + 0x00000000), 348 (0x000543c0 + 0x00000800), 349 (0x000543c0 + 0x00001000), 350 (0x000543c0 + 0x00001800), 351 (0x000943c0 + 0x00000000), 352 (0x000943c0 + 0x00000800), 353 (0x000943c0 + 0x00001000), 354 (0x000943c0 + 0x00001800), 355 (0x000d43c0 + 0x00000000), 356 (0x000d43c0 + 0x00000800), 357 (0x000d43c0 + 0x00001000), 358 (0x000d43c0 + 0x00001800), 359 (0x001143c0 + 0x00000000), 360 (0x001143c0 + 0x00000800), 361 (0x001143c0 + 0x00001000), 362 (0x001143c0 + 0x00001800), 363 (0x001543c0 + 0x00000000), 364 (0x001543c0 + 0x00000800), 365 (0x001543c0 + 0x00001000), 366 (0x001543c0 + 0x00001800), 367 (0x001943c0 + 0x00000000), 368 (0x001943c0 + 0x00000800), 369 (0x001943c0 + 0x00001000), 370 (0x001943c0 + 0x00001800), 371 (0x001d43c0 + 0x00000000), 372 (0x001d43c0 + 0x00000800), 373 (0x001d43c0 + 0x00001000), 374 (0x001d43c0 + 0x00001800), 375 }; 376 377 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 378 (0x000143e0 + 0x00000000), 379 (0x000143e0 + 0x00000800), 380 (0x000143e0 + 0x00001000), 381 (0x000143e0 + 0x00001800), 382 (0x000543e0 + 0x00000000), 383 (0x000543e0 + 0x00000800), 384 (0x000543e0 + 0x00001000), 385 (0x000543e0 + 0x00001800), 386 (0x000943e0 + 0x00000000), 387 (0x000943e0 + 0x00000800), 388 (0x000943e0 + 0x00001000), 389 (0x000943e0 + 0x00001800), 390 (0x000d43e0 + 0x00000000), 391 (0x000d43e0 + 0x00000800), 392 (0x000d43e0 + 0x00001000), 393 (0x000d43e0 + 0x00001800), 394 (0x001143e0 + 0x00000000), 395 (0x001143e0 + 0x00000800), 396 (0x001143e0 + 0x00001000), 397 (0x001143e0 + 0x00001800), 398 (0x001543e0 + 0x00000000), 399 (0x001543e0 + 0x00000800), 400 (0x001543e0 + 0x00001000), 401 (0x001543e0 + 0x00001800), 402 (0x001943e0 + 0x00000000), 403 (0x001943e0 + 0x00000800), 404 (0x001943e0 + 0x00001000), 405 (0x001943e0 + 0x00001800), 406 (0x001d43e0 + 0x00000000), 407 (0x001d43e0 + 0x00000800), 408 (0x001d43e0 + 0x00001000), 409 (0x001d43e0 + 0x00001800), 410 }; 411 412 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 413 struct amdgpu_irq_src *src, 414 unsigned int type, 415 enum amdgpu_interrupt_state state) 416 { 417 u32 bits, i, tmp, reg; 418 419 /* Devices newer then VEGA10/12 shall have these programming 420 * sequences performed by PSP BL 421 */ 422 if (adev->asic_type >= CHIP_VEGA20) 423 return 0; 424 425 bits = 0x7f; 426 427 switch (state) { 428 case AMDGPU_IRQ_STATE_DISABLE: 429 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 430 reg = ecc_umc_mcumc_ctrl_addrs[i]; 431 tmp = RREG32(reg); 432 tmp &= ~bits; 433 WREG32(reg, tmp); 434 } 435 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 436 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 437 tmp = RREG32(reg); 438 tmp &= ~bits; 439 WREG32(reg, tmp); 440 } 441 break; 442 case AMDGPU_IRQ_STATE_ENABLE: 443 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 444 reg = ecc_umc_mcumc_ctrl_addrs[i]; 445 tmp = RREG32(reg); 446 tmp |= bits; 447 WREG32(reg, tmp); 448 } 449 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 450 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 451 tmp = RREG32(reg); 452 tmp |= bits; 453 WREG32(reg, tmp); 454 } 455 break; 456 default: 457 break; 458 } 459 460 return 0; 461 } 462 463 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 464 struct amdgpu_irq_src *src, 465 unsigned int type, 466 enum amdgpu_interrupt_state state) 467 { 468 struct amdgpu_vmhub *hub; 469 u32 tmp, reg, bits, i, j; 470 471 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 472 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 473 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 478 479 switch (state) { 480 case AMDGPU_IRQ_STATE_DISABLE: 481 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 482 hub = &adev->vmhub[j]; 483 for (i = 0; i < 16; i++) { 484 reg = hub->vm_context0_cntl + i; 485 486 /* This works because this interrupt is only 487 * enabled at init/resume and disabled in 488 * fini/suspend, so the overall state doesn't 489 * change over the course of suspend/resume. 490 */ 491 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 492 continue; 493 494 if (j >= AMDGPU_MMHUB0(0)) 495 tmp = RREG32_SOC15_IP(MMHUB, reg); 496 else 497 tmp = RREG32_XCC(reg, j); 498 499 tmp &= ~bits; 500 501 if (j >= AMDGPU_MMHUB0(0)) 502 WREG32_SOC15_IP(MMHUB, reg, tmp); 503 else 504 WREG32_XCC(reg, tmp, j); 505 } 506 } 507 break; 508 case AMDGPU_IRQ_STATE_ENABLE: 509 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 510 hub = &adev->vmhub[j]; 511 for (i = 0; i < 16; i++) { 512 reg = hub->vm_context0_cntl + i; 513 514 /* This works because this interrupt is only 515 * enabled at init/resume and disabled in 516 * fini/suspend, so the overall state doesn't 517 * change over the course of suspend/resume. 518 */ 519 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 520 continue; 521 522 if (j >= AMDGPU_MMHUB0(0)) 523 tmp = RREG32_SOC15_IP(MMHUB, reg); 524 else 525 tmp = RREG32_XCC(reg, j); 526 527 tmp |= bits; 528 529 if (j >= AMDGPU_MMHUB0(0)) 530 WREG32_SOC15_IP(MMHUB, reg, tmp); 531 else 532 WREG32_XCC(reg, tmp, j); 533 } 534 } 535 break; 536 default: 537 break; 538 } 539 540 return 0; 541 } 542 543 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 544 struct amdgpu_irq_src *source, 545 struct amdgpu_iv_entry *entry) 546 { 547 bool retry_fault = !!(entry->src_data[1] & 0x80); 548 bool write_fault = !!(entry->src_data[1] & 0x20); 549 uint32_t status = 0, cid = 0, rw = 0, fed = 0; 550 struct amdgpu_task_info *task_info; 551 struct amdgpu_vmhub *hub; 552 const char *mmhub_cid; 553 const char *hub_name; 554 unsigned int vmhub; 555 u64 addr; 556 uint32_t cam_index = 0; 557 int ret, xcc_id = 0; 558 uint32_t node_id; 559 560 node_id = entry->node_id; 561 562 addr = (u64)entry->src_data[0] << 12; 563 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 564 565 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 566 hub_name = "mmhub0"; 567 vmhub = AMDGPU_MMHUB0(node_id / 4); 568 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 569 hub_name = "mmhub1"; 570 vmhub = AMDGPU_MMHUB1(0); 571 } else { 572 hub_name = "gfxhub0"; 573 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 574 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 575 node_id); 576 if (xcc_id < 0) 577 xcc_id = 0; 578 } 579 vmhub = xcc_id; 580 } 581 hub = &adev->vmhub[vmhub]; 582 583 if (retry_fault) { 584 if (adev->irq.retry_cam_enabled) { 585 /* Delegate it to a different ring if the hardware hasn't 586 * already done it. 587 */ 588 if (entry->ih == &adev->irq.ih) { 589 amdgpu_irq_delegate(adev, entry, 8); 590 return 1; 591 } 592 593 cam_index = entry->src_data[2] & 0x3ff; 594 595 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 596 addr, entry->timestamp, write_fault); 597 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 598 if (ret) 599 return 1; 600 } else { 601 /* Process it onyl if it's the first fault for this address */ 602 if (entry->ih != &adev->irq.ih_soft && 603 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 604 entry->timestamp)) 605 return 1; 606 607 /* Delegate it to a different ring if the hardware hasn't 608 * already done it. 609 */ 610 if (entry->ih == &adev->irq.ih) { 611 amdgpu_irq_delegate(adev, entry, 8); 612 return 1; 613 } 614 615 /* Try to handle the recoverable page faults by filling page 616 * tables 617 */ 618 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 619 addr, entry->timestamp, write_fault)) 620 return 1; 621 } 622 } 623 624 if (kgd2kfd_vmfault_fast_path(adev, entry, retry_fault)) 625 return 1; 626 627 if (!printk_ratelimit()) 628 return 0; 629 630 dev_err(adev->dev, 631 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name, 632 retry_fault ? "retry" : "no-retry", 633 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 634 635 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 636 if (task_info) { 637 dev_err(adev->dev, 638 " for process %s pid %d thread %s pid %d)\n", 639 task_info->process_name, task_info->tgid, 640 task_info->task_name, task_info->pid); 641 amdgpu_vm_put_task_info(task_info); 642 } 643 644 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 645 addr, entry->client_id, 646 soc15_ih_clientid_name[entry->client_id]); 647 648 if (amdgpu_is_multi_aid(adev)) 649 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 650 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 651 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 652 653 if (amdgpu_sriov_vf(adev)) 654 return 0; 655 656 /* 657 * Issue a dummy read to wait for the status register to 658 * be updated to avoid reading an incorrect value due to 659 * the new fast GRBM interface. 660 */ 661 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 662 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 663 RREG32(hub->vm_l2_pro_fault_status); 664 665 status = RREG32(hub->vm_l2_pro_fault_status); 666 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 667 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 668 fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED); 669 670 /* for fed error, kfd will handle it, return directly */ 671 if (fed && amdgpu_ras_is_poison_mode_supported(adev) && 672 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2))) 673 return 0; 674 675 /* Only print L2 fault status if the status register could be read and 676 * contains useful information 677 */ 678 if (!status) 679 return 0; 680 681 if (!amdgpu_sriov_vf(adev)) 682 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 683 684 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub); 685 686 dev_err(adev->dev, 687 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 688 status); 689 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 690 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 691 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 692 gfxhub_client_ids[cid], 693 cid); 694 } else { 695 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 696 case IP_VERSION(9, 0, 0): 697 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 698 break; 699 case IP_VERSION(9, 3, 0): 700 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 701 break; 702 case IP_VERSION(9, 4, 0): 703 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 704 break; 705 case IP_VERSION(9, 4, 1): 706 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 707 break; 708 case IP_VERSION(9, 1, 0): 709 case IP_VERSION(9, 2, 0): 710 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 711 break; 712 case IP_VERSION(1, 5, 0): 713 case IP_VERSION(2, 4, 0): 714 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 715 break; 716 case IP_VERSION(1, 8, 0): 717 case IP_VERSION(9, 4, 2): 718 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 719 break; 720 default: 721 mmhub_cid = NULL; 722 break; 723 } 724 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 725 mmhub_cid ? mmhub_cid : "unknown", cid); 726 } 727 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 728 REG_GET_FIELD(status, 729 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 730 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 731 REG_GET_FIELD(status, 732 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 733 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 734 REG_GET_FIELD(status, 735 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 736 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 737 REG_GET_FIELD(status, 738 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 739 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 740 return 0; 741 } 742 743 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 744 .set = gmc_v9_0_vm_fault_interrupt_state, 745 .process = gmc_v9_0_process_interrupt, 746 }; 747 748 749 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 750 .set = gmc_v9_0_ecc_interrupt_state, 751 .process = amdgpu_umc_process_ecc_irq, 752 }; 753 754 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 755 { 756 adev->gmc.vm_fault.num_types = 1; 757 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 758 759 if (!amdgpu_sriov_vf(adev) && 760 !adev->gmc.xgmi.connected_to_cpu && 761 !adev->gmc.is_app_apu) { 762 adev->gmc.ecc_irq.num_types = 1; 763 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 764 } 765 } 766 767 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 768 uint32_t flush_type) 769 { 770 u32 req = 0; 771 772 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 773 PER_VMID_INVALIDATE_REQ, 1 << vmid); 774 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 775 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 776 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 777 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 778 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 779 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 780 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 781 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 782 783 return req; 784 } 785 786 /** 787 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 788 * 789 * @adev: amdgpu_device pointer 790 * @vmhub: vmhub type 791 * 792 */ 793 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 794 uint32_t vmhub) 795 { 796 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 797 amdgpu_is_multi_aid(adev)) 798 return false; 799 800 return ((vmhub == AMDGPU_MMHUB0(0) || 801 vmhub == AMDGPU_MMHUB1(0)) && 802 (!amdgpu_sriov_vf(adev)) && 803 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 804 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 805 } 806 807 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 808 uint8_t vmid, uint16_t *p_pasid) 809 { 810 uint32_t value; 811 812 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 813 + vmid); 814 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 815 816 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 817 } 818 819 /* 820 * GART 821 * VMID 0 is the physical GPU addresses as used by the kernel. 822 * VMIDs 1-15 are used for userspace clients and are handled 823 * by the amdgpu vm/hsa code. 824 */ 825 826 /** 827 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 828 * 829 * @adev: amdgpu_device pointer 830 * @vmid: vm instance to flush 831 * @vmhub: which hub to flush 832 * @flush_type: the flush type 833 * 834 * Flush the TLB for the requested page table using certain type. 835 */ 836 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 837 uint32_t vmhub, uint32_t flush_type) 838 { 839 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 840 u32 j, inv_req, tmp, sem, req, ack, inst; 841 const unsigned int eng = 17; 842 struct amdgpu_vmhub *hub; 843 844 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 845 846 hub = &adev->vmhub[vmhub]; 847 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 848 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 849 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 850 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 851 852 if (vmhub >= AMDGPU_MMHUB0(0)) 853 inst = 0; 854 else 855 inst = vmhub; 856 857 /* This is necessary for SRIOV as well as for GFXOFF to function 858 * properly under bare metal 859 */ 860 if (adev->gfx.kiq[inst].ring.sched.ready && 861 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 862 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 863 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 864 865 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 866 1 << vmid, inst); 867 return; 868 } 869 870 /* This path is needed before KIQ/MES/GFXOFF are set up */ 871 spin_lock(&adev->gmc.invalidate_lock); 872 873 /* 874 * It may lose gpuvm invalidate acknowldege state across power-gating 875 * off cycle, add semaphore acquire before invalidation and semaphore 876 * release after invalidation to avoid entering power gated state 877 * to WA the Issue 878 */ 879 880 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 881 if (use_semaphore) { 882 for (j = 0; j < adev->usec_timeout; j++) { 883 /* a read return value of 1 means semaphore acquire */ 884 if (vmhub >= AMDGPU_MMHUB0(0)) 885 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst)); 886 else 887 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst)); 888 if (tmp & 0x1) 889 break; 890 udelay(1); 891 } 892 893 if (j >= adev->usec_timeout) 894 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 895 } 896 897 if (vmhub >= AMDGPU_MMHUB0(0)) 898 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst)); 899 else 900 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst)); 901 902 /* 903 * Issue a dummy read to wait for the ACK register to 904 * be cleared to avoid a false ACK due to the new fast 905 * GRBM interface. 906 */ 907 if ((vmhub == AMDGPU_GFXHUB(0)) && 908 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 909 RREG32_NO_KIQ(req); 910 911 for (j = 0; j < adev->usec_timeout; j++) { 912 if (vmhub >= AMDGPU_MMHUB0(0)) 913 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst)); 914 else 915 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst)); 916 if (tmp & (1 << vmid)) 917 break; 918 udelay(1); 919 } 920 921 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 922 if (use_semaphore) { 923 /* 924 * add semaphore release after invalidation, 925 * write with 0 means semaphore release 926 */ 927 if (vmhub >= AMDGPU_MMHUB0(0)) 928 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst)); 929 else 930 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst)); 931 } 932 933 spin_unlock(&adev->gmc.invalidate_lock); 934 935 if (j < adev->usec_timeout) 936 return; 937 938 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 939 } 940 941 /** 942 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 943 * 944 * @adev: amdgpu_device pointer 945 * @pasid: pasid to be flush 946 * @flush_type: the flush type 947 * @all_hub: flush all hubs 948 * @inst: is used to select which instance of KIQ to use for the invalidation 949 * 950 * Flush the TLB for the requested pasid. 951 */ 952 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 953 uint16_t pasid, uint32_t flush_type, 954 bool all_hub, uint32_t inst) 955 { 956 uint16_t queried; 957 int i, vmid; 958 959 for (vmid = 1; vmid < 16; vmid++) { 960 bool valid; 961 962 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 963 &queried); 964 if (!valid || queried != pasid) 965 continue; 966 967 if (all_hub) { 968 for_each_set_bit(i, adev->vmhubs_mask, 969 AMDGPU_MAX_VMHUBS) 970 gmc_v9_0_flush_gpu_tlb(adev, vmid, i, 971 flush_type); 972 } else { 973 gmc_v9_0_flush_gpu_tlb(adev, vmid, 974 AMDGPU_GFXHUB(0), 975 flush_type); 976 } 977 } 978 } 979 980 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 981 unsigned int vmid, uint64_t pd_addr) 982 { 983 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 984 struct amdgpu_device *adev = ring->adev; 985 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 986 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 987 unsigned int eng = ring->vm_inv_eng; 988 989 /* 990 * It may lose gpuvm invalidate acknowldege state across power-gating 991 * off cycle, add semaphore acquire before invalidation and semaphore 992 * release after invalidation to avoid entering power gated state 993 * to WA the Issue 994 */ 995 996 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 997 if (use_semaphore) 998 /* a read return value of 1 means semaphore acuqire */ 999 amdgpu_ring_emit_reg_wait(ring, 1000 hub->vm_inv_eng0_sem + 1001 hub->eng_distance * eng, 0x1, 0x1); 1002 1003 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1004 (hub->ctx_addr_distance * vmid), 1005 lower_32_bits(pd_addr)); 1006 1007 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1008 (hub->ctx_addr_distance * vmid), 1009 upper_32_bits(pd_addr)); 1010 1011 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 1012 hub->eng_distance * eng, 1013 hub->vm_inv_eng0_ack + 1014 hub->eng_distance * eng, 1015 req, 1 << vmid); 1016 1017 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1018 if (use_semaphore) 1019 /* 1020 * add semaphore release after invalidation, 1021 * write with 0 means semaphore release 1022 */ 1023 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1024 hub->eng_distance * eng, 0); 1025 1026 return pd_addr; 1027 } 1028 1029 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 1030 unsigned int pasid) 1031 { 1032 struct amdgpu_device *adev = ring->adev; 1033 uint32_t reg; 1034 1035 /* Do nothing because there's no lut register for mmhub1. */ 1036 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 1037 return; 1038 1039 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 1040 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1041 else 1042 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1043 1044 amdgpu_ring_emit_wreg(ring, reg, pasid); 1045 } 1046 1047 /* 1048 * PTE format on VEGA 10: 1049 * 63:59 reserved 1050 * 58:57 mtype 1051 * 56 F 1052 * 55 L 1053 * 54 P 1054 * 53 SW 1055 * 52 T 1056 * 50:48 reserved 1057 * 47:12 4k physical page base address 1058 * 11:7 fragment 1059 * 6 write 1060 * 5 read 1061 * 4 exe 1062 * 3 Z 1063 * 2 snooped 1064 * 1 system 1065 * 0 valid 1066 * 1067 * PDE format on VEGA 10: 1068 * 63:59 block fragment size 1069 * 58:55 reserved 1070 * 54 P 1071 * 53:48 reserved 1072 * 47:6 physical base address of PD or PTE 1073 * 5:3 reserved 1074 * 2 C 1075 * 1 system 1076 * 0 valid 1077 */ 1078 1079 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1080 1081 { 1082 switch (flags) { 1083 case AMDGPU_VM_MTYPE_DEFAULT: 1084 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1085 case AMDGPU_VM_MTYPE_NC: 1086 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1087 case AMDGPU_VM_MTYPE_WC: 1088 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_WC); 1089 case AMDGPU_VM_MTYPE_RW: 1090 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_RW); 1091 case AMDGPU_VM_MTYPE_CC: 1092 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_CC); 1093 case AMDGPU_VM_MTYPE_UC: 1094 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC); 1095 default: 1096 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1097 } 1098 } 1099 1100 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1101 uint64_t *addr, uint64_t *flags) 1102 { 1103 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1104 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1105 BUG_ON(*addr & 0xFFFF00000000003FULL); 1106 1107 if (!adev->gmc.translate_further) 1108 return; 1109 1110 if (level == AMDGPU_VM_PDB1) { 1111 /* Set the block fragment size */ 1112 if (!(*flags & AMDGPU_PDE_PTE)) 1113 *flags |= AMDGPU_PDE_BFS(0x9); 1114 1115 } else if (level == AMDGPU_VM_PDB0) { 1116 if (*flags & AMDGPU_PDE_PTE) { 1117 *flags &= ~AMDGPU_PDE_PTE; 1118 if (!(*flags & AMDGPU_PTE_VALID)) 1119 *addr |= 1 << PAGE_SHIFT; 1120 } else { 1121 *flags |= AMDGPU_PTE_TF; 1122 } 1123 } 1124 } 1125 1126 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1127 struct amdgpu_bo *bo, 1128 struct amdgpu_bo_va_mapping *mapping, 1129 uint64_t *flags) 1130 { 1131 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1132 bool is_vram = bo->tbo.resource && 1133 bo->tbo.resource->mem_type == TTM_PL_VRAM; 1134 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 1135 AMDGPU_GEM_CREATE_EXT_COHERENT); 1136 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; 1137 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1138 struct amdgpu_vm *vm = mapping->bo_va->base.vm; 1139 unsigned int mtype_local, mtype; 1140 uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); 1141 bool snoop = false; 1142 bool is_local; 1143 1144 dma_resv_assert_held(bo->tbo.base.resv); 1145 1146 switch (gc_ip_version) { 1147 case IP_VERSION(9, 4, 1): 1148 case IP_VERSION(9, 4, 2): 1149 if (is_vram) { 1150 if (bo_adev == adev) { 1151 if (uncached) 1152 mtype = MTYPE_UC; 1153 else if (coherent) 1154 mtype = MTYPE_CC; 1155 else 1156 mtype = MTYPE_RW; 1157 /* FIXME: is this still needed? Or does 1158 * amdgpu_ttm_tt_pde_flags already handle this? 1159 */ 1160 if (gc_ip_version == IP_VERSION(9, 4, 2) && 1161 adev->gmc.xgmi.connected_to_cpu) 1162 snoop = true; 1163 } else { 1164 if (uncached || coherent) 1165 mtype = MTYPE_UC; 1166 else 1167 mtype = MTYPE_NC; 1168 if (mapping->bo_va->is_xgmi) 1169 snoop = true; 1170 } 1171 } else { 1172 if (uncached || coherent) 1173 mtype = MTYPE_UC; 1174 else 1175 mtype = MTYPE_NC; 1176 /* FIXME: is this still needed? Or does 1177 * amdgpu_ttm_tt_pde_flags already handle this? 1178 */ 1179 snoop = true; 1180 } 1181 break; 1182 case IP_VERSION(9, 4, 3): 1183 case IP_VERSION(9, 4, 4): 1184 case IP_VERSION(9, 5, 0): 1185 /* Only local VRAM BOs or system memory on non-NUMA APUs 1186 * can be assumed to be local in their entirety. Choose 1187 * MTYPE_NC as safe fallback for all system memory BOs on 1188 * NUMA systems. Their MTYPE can be overridden per-page in 1189 * gmc_v9_0_override_vm_pte_flags. 1190 */ 1191 mtype_local = MTYPE_RW; 1192 if (amdgpu_mtype_local == 1) { 1193 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); 1194 mtype_local = MTYPE_NC; 1195 } else if (amdgpu_mtype_local == 2) { 1196 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n"); 1197 mtype_local = MTYPE_CC; 1198 } else { 1199 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); 1200 } 1201 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1202 num_possible_nodes() <= 1) || 1203 (is_vram && adev == bo_adev && 1204 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id); 1205 snoop = true; 1206 if (uncached) { 1207 mtype = MTYPE_UC; 1208 } else if (ext_coherent) { 1209 mtype = is_local ? MTYPE_CC : MTYPE_UC; 1210 } else if (adev->flags & AMD_IS_APU) { 1211 mtype = is_local ? mtype_local : MTYPE_NC; 1212 } else { 1213 /* dGPU */ 1214 if (is_local) 1215 mtype = mtype_local; 1216 else if (gc_ip_version < IP_VERSION(9, 5, 0) && !is_vram) 1217 mtype = MTYPE_UC; 1218 else 1219 mtype = MTYPE_NC; 1220 } 1221 1222 break; 1223 default: 1224 if (uncached || coherent) 1225 mtype = MTYPE_UC; 1226 else 1227 mtype = MTYPE_NC; 1228 1229 /* FIXME: is this still needed? Or does 1230 * amdgpu_ttm_tt_pde_flags already handle this? 1231 */ 1232 if (!is_vram) 1233 snoop = true; 1234 } 1235 1236 if (mtype != MTYPE_NC) 1237 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype); 1238 1239 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1240 } 1241 1242 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1243 struct amdgpu_bo_va_mapping *mapping, 1244 uint64_t *flags) 1245 { 1246 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1247 1248 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1249 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1250 1251 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1252 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1253 1254 if (mapping->flags & AMDGPU_PTE_PRT) { 1255 *flags |= AMDGPU_PTE_PRT; 1256 *flags &= ~AMDGPU_PTE_VALID; 1257 } 1258 1259 if ((*flags & AMDGPU_PTE_VALID) && bo) 1260 gmc_v9_0_get_coherence_flags(adev, bo, mapping, flags); 1261 } 1262 1263 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1264 struct amdgpu_vm *vm, 1265 uint64_t addr, uint64_t *flags) 1266 { 1267 int local_node, nid; 1268 1269 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system 1270 * memory can use more efficient MTYPEs. 1271 */ 1272 if (!(adev->flags & AMD_IS_APU) || 1273 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) 1274 return; 1275 1276 /* Only direct-mapped memory allows us to determine the NUMA node from 1277 * the DMA address. 1278 */ 1279 if (!adev->ram_is_direct_mapped) { 1280 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n"); 1281 return; 1282 } 1283 1284 /* MTYPE_NC is the same default and can be overridden. 1285 * MTYPE_UC will be present if the memory is extended-coherent 1286 * and can also be overridden. 1287 */ 1288 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1289 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC) && 1290 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1291 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC)) { 1292 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n"); 1293 return; 1294 } 1295 1296 /* FIXME: Only supported on native mode for now. For carve-out, the 1297 * NUMA affinity of the GPU/VM needs to come from the PCI info because 1298 * memory partitions are not associated with different NUMA nodes. 1299 */ 1300 if (adev->gmc.is_app_apu && vm->mem_id >= 0) { 1301 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1302 } else { 1303 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n"); 1304 return; 1305 } 1306 1307 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1308 * page or NUMA nodes. 1309 */ 1310 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1311 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n"); 1312 return; 1313 } 1314 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1315 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1316 vm->mem_id, local_node, nid); 1317 if (nid == local_node) { 1318 uint64_t old_flags = *flags; 1319 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) == 1320 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC)) { 1321 unsigned int mtype_local = MTYPE_RW; 1322 1323 if (amdgpu_mtype_local == 1) 1324 mtype_local = MTYPE_NC; 1325 else if (amdgpu_mtype_local == 2) 1326 mtype_local = MTYPE_CC; 1327 1328 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype_local); 1329 } else { 1330 /* MTYPE_UC case */ 1331 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC); 1332 } 1333 1334 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n", 1335 old_flags, *flags); 1336 } 1337 } 1338 1339 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1340 { 1341 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1342 unsigned int size; 1343 1344 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1345 1346 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1347 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1348 } else { 1349 u32 viewport; 1350 1351 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1352 case IP_VERSION(1, 0, 0): 1353 case IP_VERSION(1, 0, 1): 1354 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1355 size = (REG_GET_FIELD(viewport, 1356 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1357 REG_GET_FIELD(viewport, 1358 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1359 4); 1360 break; 1361 case IP_VERSION(2, 1, 0): 1362 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1363 size = (REG_GET_FIELD(viewport, 1364 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1365 REG_GET_FIELD(viewport, 1366 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1367 4); 1368 break; 1369 default: 1370 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1371 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1372 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1373 4); 1374 break; 1375 } 1376 } 1377 1378 return size; 1379 } 1380 1381 static bool gmc_v9_0_need_reset_on_init(struct amdgpu_device *adev) 1382 { 1383 if (adev->nbio.funcs && adev->nbio.funcs->is_nps_switch_requested && 1384 adev->nbio.funcs->is_nps_switch_requested(adev)) { 1385 adev->gmc.reset_flags |= AMDGPU_GMC_INIT_RESET_NPS; 1386 return true; 1387 } 1388 1389 return false; 1390 } 1391 1392 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1393 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1394 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1395 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1396 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1397 .map_mtype = gmc_v9_0_map_mtype, 1398 .get_vm_pde = gmc_v9_0_get_vm_pde, 1399 .get_vm_pte = gmc_v9_0_get_vm_pte, 1400 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1401 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1402 .query_mem_partition_mode = &amdgpu_gmc_query_memory_partition, 1403 .request_mem_partition_mode = &amdgpu_gmc_request_memory_partition, 1404 .need_reset_on_init = &gmc_v9_0_need_reset_on_init, 1405 }; 1406 1407 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1408 { 1409 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1410 } 1411 1412 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1413 { 1414 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1415 case IP_VERSION(6, 0, 0): 1416 adev->umc.funcs = &umc_v6_0_funcs; 1417 break; 1418 case IP_VERSION(6, 1, 1): 1419 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1420 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1421 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1422 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1423 adev->umc.retire_unit = 1; 1424 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1425 adev->umc.ras = &umc_v6_1_ras; 1426 break; 1427 case IP_VERSION(6, 1, 2): 1428 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1429 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1430 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1431 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1432 adev->umc.retire_unit = 1; 1433 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1434 adev->umc.ras = &umc_v6_1_ras; 1435 break; 1436 case IP_VERSION(6, 7, 0): 1437 adev->umc.max_ras_err_cnt_per_query = 1438 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1439 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1440 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1441 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1442 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1443 if (!adev->gmc.xgmi.connected_to_cpu) 1444 adev->umc.ras = &umc_v6_7_ras; 1445 if (1 & adev->smuio.funcs->get_die_id(adev)) 1446 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1447 else 1448 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1449 break; 1450 case IP_VERSION(12, 0, 0): 1451 case IP_VERSION(12, 5, 0): 1452 adev->umc.max_ras_err_cnt_per_query = 1453 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1454 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM; 1455 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM; 1456 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM; 1457 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET; 1458 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1459 adev->umc.ras = &umc_v12_0_ras; 1460 break; 1461 default: 1462 break; 1463 } 1464 } 1465 1466 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1467 { 1468 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1469 case IP_VERSION(9, 4, 1): 1470 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1471 break; 1472 case IP_VERSION(9, 4, 2): 1473 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1474 break; 1475 case IP_VERSION(1, 8, 0): 1476 case IP_VERSION(1, 8, 1): 1477 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1478 break; 1479 default: 1480 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1481 break; 1482 } 1483 } 1484 1485 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1486 { 1487 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1488 case IP_VERSION(9, 4, 0): 1489 adev->mmhub.ras = &mmhub_v1_0_ras; 1490 break; 1491 case IP_VERSION(9, 4, 1): 1492 adev->mmhub.ras = &mmhub_v9_4_ras; 1493 break; 1494 case IP_VERSION(9, 4, 2): 1495 adev->mmhub.ras = &mmhub_v1_7_ras; 1496 break; 1497 case IP_VERSION(1, 8, 0): 1498 case IP_VERSION(1, 8, 1): 1499 adev->mmhub.ras = &mmhub_v1_8_ras; 1500 break; 1501 default: 1502 /* mmhub ras is not available */ 1503 break; 1504 } 1505 } 1506 1507 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1508 { 1509 if (amdgpu_is_multi_aid(adev)) 1510 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1511 else 1512 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1513 } 1514 1515 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1516 { 1517 adev->hdp.ras = &hdp_v4_0_ras; 1518 } 1519 1520 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1521 { 1522 struct amdgpu_mca *mca = &adev->mca; 1523 1524 /* is UMC the right IP to check for MCA? Maybe DF? */ 1525 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1526 case IP_VERSION(6, 7, 0): 1527 if (!adev->gmc.xgmi.connected_to_cpu) { 1528 mca->mp0.ras = &mca_v3_0_mp0_ras; 1529 mca->mp1.ras = &mca_v3_0_mp1_ras; 1530 mca->mpio.ras = &mca_v3_0_mpio_ras; 1531 } 1532 break; 1533 default: 1534 break; 1535 } 1536 } 1537 1538 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1539 { 1540 if (!adev->gmc.xgmi.connected_to_cpu) 1541 adev->gmc.xgmi.ras = &xgmi_ras; 1542 } 1543 1544 static void gmc_v9_0_init_nps_details(struct amdgpu_device *adev) 1545 { 1546 enum amdgpu_memory_partition mode; 1547 uint32_t supp_modes; 1548 int i; 1549 1550 adev->gmc.supported_nps_modes = 0; 1551 1552 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 1553 return; 1554 1555 mode = amdgpu_gmc_get_memory_partition(adev, &supp_modes); 1556 1557 /* Mode detected by hardware and supported modes available */ 1558 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && supp_modes) { 1559 while ((i = ffs(supp_modes))) { 1560 if (AMDGPU_ALL_NPS_MASK & BIT(i)) 1561 adev->gmc.supported_nps_modes |= BIT(i); 1562 supp_modes &= supp_modes - 1; 1563 } 1564 } else { 1565 /*TODO: Check PSP version also which supports NPS switch. Otherwise keep 1566 * supported modes as 0. 1567 */ 1568 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1569 case IP_VERSION(9, 4, 3): 1570 case IP_VERSION(9, 4, 4): 1571 adev->gmc.supported_nps_modes = 1572 BIT(AMDGPU_NPS1_PARTITION_MODE) | 1573 BIT(AMDGPU_NPS4_PARTITION_MODE); 1574 break; 1575 default: 1576 break; 1577 } 1578 } 1579 } 1580 1581 static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block) 1582 { 1583 struct amdgpu_device *adev = ip_block->adev; 1584 1585 /* 1586 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1587 * in their IP discovery tables 1588 */ 1589 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) || 1590 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 1591 amdgpu_is_multi_aid(adev)) 1592 adev->gmc.xgmi.supported = true; 1593 1594 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) { 1595 adev->gmc.xgmi.supported = true; 1596 adev->gmc.xgmi.connected_to_cpu = 1597 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1598 } 1599 1600 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 1601 enum amdgpu_pkg_type pkg_type = 1602 adev->smuio.funcs->get_pkg_type(adev); 1603 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1604 * and the APU, can be in used two possible modes: 1605 * - carveout mode 1606 * - native APU mode 1607 * "is_app_apu" can be used to identify the APU in the native 1608 * mode. 1609 */ 1610 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1611 !pci_resource_len(adev->pdev, 0)); 1612 } 1613 1614 gmc_v9_0_set_gmc_funcs(adev); 1615 gmc_v9_0_set_irq_funcs(adev); 1616 gmc_v9_0_set_umc_funcs(adev); 1617 gmc_v9_0_set_mmhub_funcs(adev); 1618 gmc_v9_0_set_mmhub_ras_funcs(adev); 1619 gmc_v9_0_set_gfxhub_funcs(adev); 1620 gmc_v9_0_set_hdp_ras_funcs(adev); 1621 gmc_v9_0_set_mca_ras_funcs(adev); 1622 gmc_v9_0_set_xgmi_ras_funcs(adev); 1623 1624 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1625 adev->gmc.shared_aperture_end = 1626 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1627 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1628 adev->gmc.private_aperture_end = 1629 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1630 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1631 1632 return 0; 1633 } 1634 1635 static int gmc_v9_0_late_init(struct amdgpu_ip_block *ip_block) 1636 { 1637 struct amdgpu_device *adev = ip_block->adev; 1638 int r; 1639 1640 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1641 if (r) 1642 return r; 1643 1644 /* 1645 * Workaround performance drop issue with VBIOS enables partial 1646 * writes, while disables HBM ECC for vega10. 1647 */ 1648 if (!amdgpu_sriov_vf(adev) && 1649 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) { 1650 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1651 if (adev->df.funcs && 1652 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1653 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1654 } 1655 } 1656 1657 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1658 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB); 1659 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP); 1660 } 1661 1662 r = amdgpu_gmc_ras_late_init(adev); 1663 if (r) 1664 return r; 1665 1666 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1667 } 1668 1669 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1670 struct amdgpu_gmc *mc) 1671 { 1672 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1673 1674 amdgpu_gmc_set_agp_default(adev, mc); 1675 1676 /* add the xgmi offset of the physical node */ 1677 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1678 if (amdgpu_gmc_is_pdb0_enabled(adev)) { 1679 amdgpu_gmc_sysvm_location(adev, mc); 1680 } else { 1681 amdgpu_gmc_vram_location(adev, mc, base); 1682 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 1683 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 1684 amdgpu_gmc_agp_location(adev, mc); 1685 } 1686 /* base offset of vram pages */ 1687 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1688 1689 /* XXX: add the xgmi offset of the physical node? */ 1690 adev->vm_manager.vram_base_offset += 1691 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1692 } 1693 1694 /** 1695 * gmc_v9_0_mc_init - initialize the memory controller driver params 1696 * 1697 * @adev: amdgpu_device pointer 1698 * 1699 * Look up the amount of vram, vram width, and decide how to place 1700 * vram and gart within the GPU's physical address space. 1701 * Returns 0 for success. 1702 */ 1703 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1704 { 1705 int r; 1706 1707 /* size in MB on si */ 1708 if (!adev->gmc.is_app_apu) { 1709 adev->gmc.mc_vram_size = 1710 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1711 } else { 1712 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1713 adev->gmc.mc_vram_size = 0; 1714 } 1715 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1716 1717 if (!(adev->flags & AMD_IS_APU) && 1718 !adev->gmc.xgmi.connected_to_cpu) { 1719 r = amdgpu_device_resize_fb_bar(adev); 1720 if (r) 1721 return r; 1722 } 1723 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1724 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1725 1726 #ifdef CONFIG_X86_64 1727 /* 1728 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1729 * interface can use VRAM through here as it appears system reserved 1730 * memory in host address space. 1731 * 1732 * For APUs, VRAM is just the stolen system memory and can be accessed 1733 * directly. 1734 * 1735 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1736 */ 1737 1738 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1739 if ((!amdgpu_sriov_vf(adev) && 1740 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1741 (adev->gmc.xgmi.supported && 1742 adev->gmc.xgmi.connected_to_cpu)) { 1743 adev->gmc.aper_base = 1744 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1745 adev->gmc.xgmi.physical_node_id * 1746 adev->gmc.xgmi.node_segment_size; 1747 adev->gmc.aper_size = adev->gmc.real_vram_size; 1748 } 1749 1750 #endif 1751 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1752 1753 /* set the gart size */ 1754 if (amdgpu_gart_size == -1) { 1755 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1756 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1757 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1758 case IP_VERSION(9, 4, 0): 1759 case IP_VERSION(9, 4, 1): 1760 case IP_VERSION(9, 4, 2): 1761 case IP_VERSION(9, 4, 3): 1762 case IP_VERSION(9, 4, 4): 1763 case IP_VERSION(9, 5, 0): 1764 default: 1765 adev->gmc.gart_size = 512ULL << 20; 1766 break; 1767 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1768 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1769 case IP_VERSION(9, 3, 0): 1770 adev->gmc.gart_size = 1024ULL << 20; 1771 break; 1772 } 1773 } else { 1774 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1775 } 1776 1777 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1778 1779 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1780 1781 return 0; 1782 } 1783 1784 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1785 { 1786 int r; 1787 1788 if (adev->gart.bo) { 1789 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1790 return 0; 1791 } 1792 1793 if (amdgpu_gmc_is_pdb0_enabled(adev)) { 1794 adev->gmc.vmid0_page_table_depth = 1; 1795 adev->gmc.vmid0_page_table_block_size = 12; 1796 } else { 1797 adev->gmc.vmid0_page_table_depth = 0; 1798 adev->gmc.vmid0_page_table_block_size = 0; 1799 } 1800 1801 /* Initialize common gart structure */ 1802 r = amdgpu_gart_init(adev); 1803 if (r) 1804 return r; 1805 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1806 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC) | 1807 AMDGPU_PTE_EXECUTABLE; 1808 1809 if (!adev->gmc.real_vram_size) { 1810 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1811 r = amdgpu_gart_table_ram_alloc(adev); 1812 if (r) 1813 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1814 } else { 1815 r = amdgpu_gart_table_vram_alloc(adev); 1816 if (r) 1817 return r; 1818 1819 if (amdgpu_gmc_is_pdb0_enabled(adev)) 1820 r = amdgpu_gmc_pdb0_alloc(adev); 1821 } 1822 1823 return r; 1824 } 1825 1826 /** 1827 * gmc_v9_0_save_registers - saves regs 1828 * 1829 * @adev: amdgpu_device pointer 1830 * 1831 * This saves potential register values that should be 1832 * restored upon resume 1833 */ 1834 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1835 { 1836 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1837 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) 1838 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1839 } 1840 1841 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 1842 { 1843 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1844 adev->gmc.vram_width = 128 * 64; 1845 1846 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 1847 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; 1848 } 1849 1850 static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) 1851 { 1852 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 1853 struct amdgpu_device *adev = ip_block->adev; 1854 unsigned long inst_mask = adev->aid_mask; 1855 1856 adev->gfxhub.funcs->init(adev); 1857 1858 adev->mmhub.funcs->init(adev); 1859 1860 spin_lock_init(&adev->gmc.invalidate_lock); 1861 1862 if (amdgpu_is_multi_aid(adev)) { 1863 gmc_v9_4_3_init_vram_info(adev); 1864 } else if (!adev->bios) { 1865 if (adev->flags & AMD_IS_APU) { 1866 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 1867 adev->gmc.vram_width = 64 * 64; 1868 } else { 1869 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1870 adev->gmc.vram_width = 128 * 64; 1871 } 1872 } else { 1873 r = amdgpu_atomfirmware_get_vram_info(adev, 1874 &vram_width, &vram_type, &vram_vendor); 1875 if (amdgpu_sriov_vf(adev)) 1876 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1877 * and DF related registers is not readable, seems hardcord is the 1878 * only way to set the correct vram_width 1879 */ 1880 adev->gmc.vram_width = 2048; 1881 else if (amdgpu_emu_mode != 1) 1882 adev->gmc.vram_width = vram_width; 1883 1884 if (!adev->gmc.vram_width) { 1885 int chansize, numchan; 1886 1887 /* hbm memory channel size */ 1888 if (adev->flags & AMD_IS_APU) 1889 chansize = 64; 1890 else 1891 chansize = 128; 1892 if (adev->df.funcs && 1893 adev->df.funcs->get_hbm_channel_number) { 1894 numchan = adev->df.funcs->get_hbm_channel_number(adev); 1895 adev->gmc.vram_width = numchan * chansize; 1896 } 1897 } 1898 1899 adev->gmc.vram_type = vram_type; 1900 adev->gmc.vram_vendor = vram_vendor; 1901 } 1902 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1903 case IP_VERSION(9, 1, 0): 1904 case IP_VERSION(9, 2, 2): 1905 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1906 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1907 1908 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1909 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1910 } else { 1911 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1912 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1913 adev->gmc.translate_further = 1914 adev->vm_manager.num_level > 1; 1915 } 1916 break; 1917 case IP_VERSION(9, 0, 1): 1918 case IP_VERSION(9, 2, 1): 1919 case IP_VERSION(9, 4, 0): 1920 case IP_VERSION(9, 3, 0): 1921 case IP_VERSION(9, 4, 2): 1922 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1923 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1924 1925 /* 1926 * To fulfill 4-level page support, 1927 * vm size is 256TB (48bit), maximum size of Vega10, 1928 * block size 512 (9bit) 1929 */ 1930 1931 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1932 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 1933 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1934 break; 1935 case IP_VERSION(9, 4, 1): 1936 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1937 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1938 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 1939 1940 /* Keep the vm size same with Vega20 */ 1941 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1942 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1943 break; 1944 case IP_VERSION(9, 4, 3): 1945 case IP_VERSION(9, 4, 4): 1946 case IP_VERSION(9, 5, 0): 1947 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 1948 NUM_XCC(adev->gfx.xcc_mask)); 1949 1950 inst_mask <<= AMDGPU_MMHUB0(0); 1951 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 1952 1953 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1954 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1955 break; 1956 default: 1957 break; 1958 } 1959 1960 /* This interrupt is VMC page fault.*/ 1961 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1962 &adev->gmc.vm_fault); 1963 if (r) 1964 return r; 1965 1966 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) { 1967 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1968 &adev->gmc.vm_fault); 1969 if (r) 1970 return r; 1971 } 1972 1973 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1974 &adev->gmc.vm_fault); 1975 1976 if (r) 1977 return r; 1978 1979 if (!amdgpu_sriov_vf(adev) && 1980 !adev->gmc.xgmi.connected_to_cpu && 1981 !adev->gmc.is_app_apu) { 1982 /* interrupt sent to DF. */ 1983 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1984 &adev->gmc.ecc_irq); 1985 if (r) 1986 return r; 1987 } 1988 1989 /* Set the internal MC address mask 1990 * This is the max address of the GPU's 1991 * internal address space. 1992 */ 1993 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1994 1995 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= 1996 IP_VERSION(9, 4, 2) ? 1997 48 : 1998 44; 1999 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 2000 if (r) { 2001 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 2002 return r; 2003 } 2004 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 2005 2006 r = gmc_v9_0_mc_init(adev); 2007 if (r) 2008 return r; 2009 2010 amdgpu_gmc_get_vbios_allocations(adev); 2011 2012 if (amdgpu_is_multi_aid(adev)) { 2013 r = amdgpu_gmc_init_mem_ranges(adev); 2014 if (r) 2015 return r; 2016 } 2017 2018 /* Memory manager */ 2019 r = amdgpu_bo_init(adev); 2020 if (r) 2021 return r; 2022 2023 r = gmc_v9_0_gart_init(adev); 2024 if (r) 2025 return r; 2026 2027 gmc_v9_0_init_nps_details(adev); 2028 /* 2029 * number of VMs 2030 * VMID 0 is reserved for System 2031 * amdgpu graphics/compute will use VMIDs 1..n-1 2032 * amdkfd will use VMIDs n..15 2033 * 2034 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2035 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2036 * for video processing. 2037 */ 2038 adev->vm_manager.first_kfd_vmid = 2039 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 2040 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 2041 amdgpu_is_multi_aid(adev)) ? 2042 3 : 2043 8; 2044 2045 amdgpu_vm_manager_init(adev); 2046 2047 gmc_v9_0_save_registers(adev); 2048 2049 r = amdgpu_gmc_ras_sw_init(adev); 2050 if (r) 2051 return r; 2052 2053 if (amdgpu_is_multi_aid(adev)) 2054 amdgpu_gmc_sysfs_init(adev); 2055 2056 return 0; 2057 } 2058 2059 static int gmc_v9_0_sw_fini(struct amdgpu_ip_block *ip_block) 2060 { 2061 struct amdgpu_device *adev = ip_block->adev; 2062 2063 if (amdgpu_is_multi_aid(adev)) 2064 amdgpu_gmc_sysfs_fini(adev); 2065 2066 amdgpu_gmc_ras_fini(adev); 2067 amdgpu_gem_force_release(adev); 2068 amdgpu_vm_manager_fini(adev); 2069 if (!adev->gmc.real_vram_size) { 2070 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2071 amdgpu_gart_table_ram_free(adev); 2072 } else { 2073 amdgpu_gart_table_vram_free(adev); 2074 } 2075 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2076 amdgpu_bo_fini(adev); 2077 2078 adev->gmc.num_mem_partitions = 0; 2079 kfree(adev->gmc.mem_partitions); 2080 2081 return 0; 2082 } 2083 2084 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2085 { 2086 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 2087 case IP_VERSION(9, 0, 0): 2088 if (amdgpu_sriov_vf(adev)) 2089 break; 2090 fallthrough; 2091 case IP_VERSION(9, 4, 0): 2092 soc15_program_register_sequence(adev, 2093 golden_settings_mmhub_1_0_0, 2094 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2095 soc15_program_register_sequence(adev, 2096 golden_settings_athub_1_0_0, 2097 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2098 break; 2099 case IP_VERSION(9, 1, 0): 2100 case IP_VERSION(9, 2, 0): 2101 /* TODO for renoir */ 2102 soc15_program_register_sequence(adev, 2103 golden_settings_athub_1_0_0, 2104 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2105 break; 2106 default: 2107 break; 2108 } 2109 } 2110 2111 /** 2112 * gmc_v9_0_restore_registers - restores regs 2113 * 2114 * @adev: amdgpu_device pointer 2115 * 2116 * This restores register values, saved at suspend. 2117 */ 2118 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2119 { 2120 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 2121 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) { 2122 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2123 WARN_ON(adev->gmc.sdpif_register != 2124 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2125 } 2126 } 2127 2128 /** 2129 * gmc_v9_0_gart_enable - gart enable 2130 * 2131 * @adev: amdgpu_device pointer 2132 */ 2133 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2134 { 2135 int r; 2136 2137 if (amdgpu_gmc_is_pdb0_enabled(adev)) 2138 amdgpu_gmc_init_pdb0(adev); 2139 2140 if (adev->gart.bo == NULL) { 2141 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2142 return -EINVAL; 2143 } 2144 2145 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2146 2147 if (!adev->in_s0ix) { 2148 r = adev->gfxhub.funcs->gart_enable(adev); 2149 if (r) 2150 return r; 2151 } 2152 2153 r = adev->mmhub.funcs->gart_enable(adev); 2154 if (r) 2155 return r; 2156 2157 DRM_INFO("PCIE GART of %uM enabled.\n", 2158 (unsigned int)(adev->gmc.gart_size >> 20)); 2159 if (adev->gmc.pdb0_bo) 2160 DRM_INFO("PDB0 located at 0x%016llX\n", 2161 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2162 DRM_INFO("PTB located at 0x%016llX\n", 2163 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2164 2165 return 0; 2166 } 2167 2168 static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block) 2169 { 2170 struct amdgpu_device *adev = ip_block->adev; 2171 bool value; 2172 int i, r; 2173 2174 adev->gmc.flush_pasid_uses_kiq = true; 2175 2176 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush 2177 * (type 2), which flushes both. Due to a race condition with 2178 * concurrent memory accesses using the same TLB cache line, we still 2179 * need a second TLB flush after this. 2180 */ 2181 adev->gmc.flush_tlb_needs_extra_type_2 = 2182 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) && 2183 adev->gmc.xgmi.num_physical_nodes; 2184 2185 /* The sequence of these two function calls matters.*/ 2186 gmc_v9_0_init_golden_registers(adev); 2187 2188 if (adev->mode_info.num_crtc) { 2189 /* Lockout access through VGA aperture*/ 2190 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2191 /* disable VGA render */ 2192 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2193 } 2194 2195 if (adev->mmhub.funcs->update_power_gating) 2196 adev->mmhub.funcs->update_power_gating(adev, true); 2197 2198 adev->hdp.funcs->init_registers(adev); 2199 2200 /* After HDP is initialized, flush HDP.*/ 2201 amdgpu_device_flush_hdp(adev, NULL); 2202 2203 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2204 value = false; 2205 else 2206 value = true; 2207 2208 if (!amdgpu_sriov_vf(adev)) { 2209 if (!adev->in_s0ix) 2210 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2211 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2212 } 2213 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2214 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2215 continue; 2216 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2217 } 2218 2219 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2220 adev->umc.funcs->init_registers(adev); 2221 2222 r = gmc_v9_0_gart_enable(adev); 2223 if (r) 2224 return r; 2225 2226 if (amdgpu_emu_mode == 1) 2227 return amdgpu_gmc_vram_checking(adev); 2228 2229 return 0; 2230 } 2231 2232 /** 2233 * gmc_v9_0_gart_disable - gart disable 2234 * 2235 * @adev: amdgpu_device pointer 2236 * 2237 * This disables all VM page table. 2238 */ 2239 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2240 { 2241 if (!adev->in_s0ix) 2242 adev->gfxhub.funcs->gart_disable(adev); 2243 adev->mmhub.funcs->gart_disable(adev); 2244 } 2245 2246 static int gmc_v9_0_hw_fini(struct amdgpu_ip_block *ip_block) 2247 { 2248 struct amdgpu_device *adev = ip_block->adev; 2249 2250 gmc_v9_0_gart_disable(adev); 2251 2252 if (amdgpu_sriov_vf(adev)) { 2253 /* full access mode, so don't touch any GMC register */ 2254 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2255 return 0; 2256 } 2257 2258 /* 2259 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2260 * a correct cached state for GMC. Otherwise, the "gate" again 2261 * operation on S3 resuming will fail due to wrong cached state. 2262 */ 2263 if (adev->mmhub.funcs->update_power_gating) 2264 adev->mmhub.funcs->update_power_gating(adev, false); 2265 2266 /* 2267 * For minimal init, late_init is not called, hence VM fault/RAS irqs 2268 * are not enabled. 2269 */ 2270 if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { 2271 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2272 2273 if (adev->gmc.ecc_irq.funcs && 2274 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2275 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 2276 } 2277 2278 return 0; 2279 } 2280 2281 static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block) 2282 { 2283 return gmc_v9_0_hw_fini(ip_block); 2284 } 2285 2286 static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block) 2287 { 2288 struct amdgpu_device *adev = ip_block->adev; 2289 int r; 2290 2291 /* If a reset is done for NPS mode switch, read the memory range 2292 * information again. 2293 */ 2294 if (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS) { 2295 amdgpu_gmc_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 2296 adev->gmc.reset_flags &= ~AMDGPU_GMC_INIT_RESET_NPS; 2297 } 2298 2299 r = gmc_v9_0_hw_init(ip_block); 2300 if (r) 2301 return r; 2302 2303 amdgpu_vmid_reset_all(ip_block->adev); 2304 2305 return 0; 2306 } 2307 2308 static bool gmc_v9_0_is_idle(struct amdgpu_ip_block *ip_block) 2309 { 2310 /* MC is always ready in GMC v9.*/ 2311 return true; 2312 } 2313 2314 static int gmc_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 2315 { 2316 /* There is no need to wait for MC idle in GMC v9.*/ 2317 return 0; 2318 } 2319 2320 static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block) 2321 { 2322 /* XXX for emulation.*/ 2323 return 0; 2324 } 2325 2326 static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2327 enum amd_clockgating_state state) 2328 { 2329 struct amdgpu_device *adev = ip_block->adev; 2330 2331 adev->mmhub.funcs->set_clockgating(adev, state); 2332 2333 athub_v1_0_set_clockgating(adev, state); 2334 2335 return 0; 2336 } 2337 2338 static void gmc_v9_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2339 { 2340 struct amdgpu_device *adev = ip_block->adev; 2341 2342 adev->mmhub.funcs->get_clockgating(adev, flags); 2343 2344 athub_v1_0_get_clockgating(adev, flags); 2345 } 2346 2347 static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 2348 enum amd_powergating_state state) 2349 { 2350 return 0; 2351 } 2352 2353 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2354 .name = "gmc_v9_0", 2355 .early_init = gmc_v9_0_early_init, 2356 .late_init = gmc_v9_0_late_init, 2357 .sw_init = gmc_v9_0_sw_init, 2358 .sw_fini = gmc_v9_0_sw_fini, 2359 .hw_init = gmc_v9_0_hw_init, 2360 .hw_fini = gmc_v9_0_hw_fini, 2361 .suspend = gmc_v9_0_suspend, 2362 .resume = gmc_v9_0_resume, 2363 .is_idle = gmc_v9_0_is_idle, 2364 .wait_for_idle = gmc_v9_0_wait_for_idle, 2365 .soft_reset = gmc_v9_0_soft_reset, 2366 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2367 .set_powergating_state = gmc_v9_0_set_powergating_state, 2368 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2369 }; 2370 2371 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = { 2372 .type = AMD_IP_BLOCK_TYPE_GMC, 2373 .major = 9, 2374 .minor = 0, 2375 .rev = 0, 2376 .funcs = &gmc_v9_0_ip_funcs, 2377 }; 2378