1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "hdp/hdp_4_0_offset.h" 35 #include "hdp/hdp_4_0_sh_mask.h" 36 #include "gc/gc_9_0_sh_mask.h" 37 #include "dce/dce_12_0_offset.h" 38 #include "dce/dce_12_0_sh_mask.h" 39 #include "vega10_enum.h" 40 #include "mmhub/mmhub_1_0_offset.h" 41 #include "athub/athub_1_0_offset.h" 42 #include "oss/osssys_4_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "gfxhub_v1_1.h" 51 #include "mmhub_v9_4.h" 52 #include "umc_v6_1.h" 53 54 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 55 56 #include "amdgpu_ras.h" 57 58 /* add these here since we already include dce12 headers and these are for DCN */ 59 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 60 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 61 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 62 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 63 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 64 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 65 66 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ 67 #define AMDGPU_NUM_OF_VMIDS 8 68 69 static const u32 golden_settings_vega10_hdp[] = 70 { 71 0xf64, 0x0fffffff, 0x00000000, 72 0xf65, 0x0fffffff, 0x00000000, 73 0xf66, 0x0fffffff, 0x00000000, 74 0xf67, 0x0fffffff, 0x00000000, 75 0xf68, 0x0fffffff, 0x00000000, 76 0xf6a, 0x0fffffff, 0x00000000, 77 0xf6b, 0x0fffffff, 0x00000000, 78 0xf6c, 0x0fffffff, 0x00000000, 79 0xf6d, 0x0fffffff, 0x00000000, 80 0xf6e, 0x0fffffff, 0x00000000, 81 }; 82 83 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = 84 { 85 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 86 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 87 }; 88 89 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = 90 { 91 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 92 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 93 }; 94 95 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 96 (0x000143c0 + 0x00000000), 97 (0x000143c0 + 0x00000800), 98 (0x000143c0 + 0x00001000), 99 (0x000143c0 + 0x00001800), 100 (0x000543c0 + 0x00000000), 101 (0x000543c0 + 0x00000800), 102 (0x000543c0 + 0x00001000), 103 (0x000543c0 + 0x00001800), 104 (0x000943c0 + 0x00000000), 105 (0x000943c0 + 0x00000800), 106 (0x000943c0 + 0x00001000), 107 (0x000943c0 + 0x00001800), 108 (0x000d43c0 + 0x00000000), 109 (0x000d43c0 + 0x00000800), 110 (0x000d43c0 + 0x00001000), 111 (0x000d43c0 + 0x00001800), 112 (0x001143c0 + 0x00000000), 113 (0x001143c0 + 0x00000800), 114 (0x001143c0 + 0x00001000), 115 (0x001143c0 + 0x00001800), 116 (0x001543c0 + 0x00000000), 117 (0x001543c0 + 0x00000800), 118 (0x001543c0 + 0x00001000), 119 (0x001543c0 + 0x00001800), 120 (0x001943c0 + 0x00000000), 121 (0x001943c0 + 0x00000800), 122 (0x001943c0 + 0x00001000), 123 (0x001943c0 + 0x00001800), 124 (0x001d43c0 + 0x00000000), 125 (0x001d43c0 + 0x00000800), 126 (0x001d43c0 + 0x00001000), 127 (0x001d43c0 + 0x00001800), 128 }; 129 130 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 131 (0x000143e0 + 0x00000000), 132 (0x000143e0 + 0x00000800), 133 (0x000143e0 + 0x00001000), 134 (0x000143e0 + 0x00001800), 135 (0x000543e0 + 0x00000000), 136 (0x000543e0 + 0x00000800), 137 (0x000543e0 + 0x00001000), 138 (0x000543e0 + 0x00001800), 139 (0x000943e0 + 0x00000000), 140 (0x000943e0 + 0x00000800), 141 (0x000943e0 + 0x00001000), 142 (0x000943e0 + 0x00001800), 143 (0x000d43e0 + 0x00000000), 144 (0x000d43e0 + 0x00000800), 145 (0x000d43e0 + 0x00001000), 146 (0x000d43e0 + 0x00001800), 147 (0x001143e0 + 0x00000000), 148 (0x001143e0 + 0x00000800), 149 (0x001143e0 + 0x00001000), 150 (0x001143e0 + 0x00001800), 151 (0x001543e0 + 0x00000000), 152 (0x001543e0 + 0x00000800), 153 (0x001543e0 + 0x00001000), 154 (0x001543e0 + 0x00001800), 155 (0x001943e0 + 0x00000000), 156 (0x001943e0 + 0x00000800), 157 (0x001943e0 + 0x00001000), 158 (0x001943e0 + 0x00001800), 159 (0x001d43e0 + 0x00000000), 160 (0x001d43e0 + 0x00000800), 161 (0x001d43e0 + 0x00001000), 162 (0x001d43e0 + 0x00001800), 163 }; 164 165 static const uint32_t ecc_umc_mcumc_status_addrs[] = { 166 (0x000143c2 + 0x00000000), 167 (0x000143c2 + 0x00000800), 168 (0x000143c2 + 0x00001000), 169 (0x000143c2 + 0x00001800), 170 (0x000543c2 + 0x00000000), 171 (0x000543c2 + 0x00000800), 172 (0x000543c2 + 0x00001000), 173 (0x000543c2 + 0x00001800), 174 (0x000943c2 + 0x00000000), 175 (0x000943c2 + 0x00000800), 176 (0x000943c2 + 0x00001000), 177 (0x000943c2 + 0x00001800), 178 (0x000d43c2 + 0x00000000), 179 (0x000d43c2 + 0x00000800), 180 (0x000d43c2 + 0x00001000), 181 (0x000d43c2 + 0x00001800), 182 (0x001143c2 + 0x00000000), 183 (0x001143c2 + 0x00000800), 184 (0x001143c2 + 0x00001000), 185 (0x001143c2 + 0x00001800), 186 (0x001543c2 + 0x00000000), 187 (0x001543c2 + 0x00000800), 188 (0x001543c2 + 0x00001000), 189 (0x001543c2 + 0x00001800), 190 (0x001943c2 + 0x00000000), 191 (0x001943c2 + 0x00000800), 192 (0x001943c2 + 0x00001000), 193 (0x001943c2 + 0x00001800), 194 (0x001d43c2 + 0x00000000), 195 (0x001d43c2 + 0x00000800), 196 (0x001d43c2 + 0x00001000), 197 (0x001d43c2 + 0x00001800), 198 }; 199 200 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 201 struct amdgpu_irq_src *src, 202 unsigned type, 203 enum amdgpu_interrupt_state state) 204 { 205 u32 bits, i, tmp, reg; 206 207 bits = 0x7f; 208 209 switch (state) { 210 case AMDGPU_IRQ_STATE_DISABLE: 211 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 212 reg = ecc_umc_mcumc_ctrl_addrs[i]; 213 tmp = RREG32(reg); 214 tmp &= ~bits; 215 WREG32(reg, tmp); 216 } 217 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 218 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 219 tmp = RREG32(reg); 220 tmp &= ~bits; 221 WREG32(reg, tmp); 222 } 223 break; 224 case AMDGPU_IRQ_STATE_ENABLE: 225 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 226 reg = ecc_umc_mcumc_ctrl_addrs[i]; 227 tmp = RREG32(reg); 228 tmp |= bits; 229 WREG32(reg, tmp); 230 } 231 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 232 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 233 tmp = RREG32(reg); 234 tmp |= bits; 235 WREG32(reg, tmp); 236 } 237 break; 238 default: 239 break; 240 } 241 242 return 0; 243 } 244 245 static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev, 246 struct ras_err_data *err_data, 247 struct amdgpu_iv_entry *entry) 248 { 249 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 250 if (adev->umc.funcs->query_ras_error_count) 251 adev->umc.funcs->query_ras_error_count(adev, err_data); 252 /* umc query_ras_error_address is also responsible for clearing 253 * error status 254 */ 255 if (adev->umc.funcs->query_ras_error_address) 256 adev->umc.funcs->query_ras_error_address(adev, err_data); 257 258 /* only uncorrectable error needs gpu reset */ 259 if (err_data->ue_count) 260 amdgpu_ras_reset_gpu(adev, 0); 261 262 return AMDGPU_RAS_SUCCESS; 263 } 264 265 static int gmc_v9_0_process_ecc_irq(struct amdgpu_device *adev, 266 struct amdgpu_irq_src *source, 267 struct amdgpu_iv_entry *entry) 268 { 269 struct ras_common_if *ras_if = adev->gmc.ras_if; 270 struct ras_dispatch_if ih_data = { 271 .entry = entry, 272 }; 273 274 if (!ras_if) 275 return 0; 276 277 ih_data.head = *ras_if; 278 279 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 280 return 0; 281 } 282 283 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 284 struct amdgpu_irq_src *src, 285 unsigned type, 286 enum amdgpu_interrupt_state state) 287 { 288 struct amdgpu_vmhub *hub; 289 u32 tmp, reg, bits, i, j; 290 291 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 292 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 293 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 294 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 295 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 296 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 297 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 298 299 switch (state) { 300 case AMDGPU_IRQ_STATE_DISABLE: 301 for (j = 0; j < adev->num_vmhubs; j++) { 302 hub = &adev->vmhub[j]; 303 for (i = 0; i < 16; i++) { 304 reg = hub->vm_context0_cntl + i; 305 tmp = RREG32(reg); 306 tmp &= ~bits; 307 WREG32(reg, tmp); 308 } 309 } 310 break; 311 case AMDGPU_IRQ_STATE_ENABLE: 312 for (j = 0; j < adev->num_vmhubs; j++) { 313 hub = &adev->vmhub[j]; 314 for (i = 0; i < 16; i++) { 315 reg = hub->vm_context0_cntl + i; 316 tmp = RREG32(reg); 317 tmp |= bits; 318 WREG32(reg, tmp); 319 } 320 } 321 default: 322 break; 323 } 324 325 return 0; 326 } 327 328 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 329 struct amdgpu_irq_src *source, 330 struct amdgpu_iv_entry *entry) 331 { 332 struct amdgpu_vmhub *hub; 333 bool retry_fault = !!(entry->src_data[1] & 0x80); 334 uint32_t status = 0; 335 u64 addr; 336 char hub_name[10]; 337 338 addr = (u64)entry->src_data[0] << 12; 339 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 340 341 if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid, 342 entry->timestamp)) 343 return 1; /* This also prevents sending it to KFD */ 344 345 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 346 snprintf(hub_name, sizeof(hub_name), "mmhub0"); 347 hub = &adev->vmhub[AMDGPU_MMHUB_0]; 348 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 349 snprintf(hub_name, sizeof(hub_name), "mmhub1"); 350 hub = &adev->vmhub[AMDGPU_MMHUB_1]; 351 } else { 352 snprintf(hub_name, sizeof(hub_name), "gfxhub0"); 353 hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 354 } 355 356 /* If it's the first fault for this address, process it normally */ 357 if (!amdgpu_sriov_vf(adev)) { 358 status = RREG32(hub->vm_l2_pro_fault_status); 359 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 360 } 361 362 if (printk_ratelimit()) { 363 struct amdgpu_task_info task_info; 364 365 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 366 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 367 368 dev_err(adev->dev, 369 "[%s] %s page fault (src_id:%u ring:%u vmid:%u " 370 "pasid:%u, for process %s pid %d thread %s pid %d)\n", 371 hub_name, retry_fault ? "retry" : "no-retry", 372 entry->src_id, entry->ring_id, entry->vmid, 373 entry->pasid, task_info.process_name, task_info.tgid, 374 task_info.task_name, task_info.pid); 375 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 376 addr, entry->client_id); 377 if (!amdgpu_sriov_vf(adev)) { 378 dev_err(adev->dev, 379 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 380 status); 381 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 382 REG_GET_FIELD(status, 383 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 384 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 385 REG_GET_FIELD(status, 386 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 387 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 388 REG_GET_FIELD(status, 389 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 390 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 391 REG_GET_FIELD(status, 392 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 393 394 } 395 } 396 397 return 0; 398 } 399 400 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 401 .set = gmc_v9_0_vm_fault_interrupt_state, 402 .process = gmc_v9_0_process_interrupt, 403 }; 404 405 406 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 407 .set = gmc_v9_0_ecc_interrupt_state, 408 .process = gmc_v9_0_process_ecc_irq, 409 }; 410 411 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 412 { 413 adev->gmc.vm_fault.num_types = 1; 414 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 415 416 adev->gmc.ecc_irq.num_types = 1; 417 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 418 } 419 420 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 421 uint32_t flush_type) 422 { 423 u32 req = 0; 424 425 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 426 PER_VMID_INVALIDATE_REQ, 1 << vmid); 427 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 428 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 429 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 430 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 431 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 432 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 433 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 434 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 435 436 return req; 437 } 438 439 /* 440 * GART 441 * VMID 0 is the physical GPU addresses as used by the kernel. 442 * VMIDs 1-15 are used for userspace clients and are handled 443 * by the amdgpu vm/hsa code. 444 */ 445 446 /** 447 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 448 * 449 * @adev: amdgpu_device pointer 450 * @vmid: vm instance to flush 451 * @flush_type: the flush type 452 * 453 * Flush the TLB for the requested page table using certain type. 454 */ 455 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, 456 uint32_t vmid, uint32_t flush_type) 457 { 458 const unsigned eng = 17; 459 unsigned i, j; 460 461 for (i = 0; i < adev->num_vmhubs; ++i) { 462 struct amdgpu_vmhub *hub = &adev->vmhub[i]; 463 u32 tmp = gmc_v9_0_get_invalidate_req(vmid, flush_type); 464 465 /* This is necessary for a HW workaround under SRIOV as well 466 * as GFXOFF under bare metal 467 */ 468 if (adev->gfx.kiq.ring.sched.ready && 469 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 470 !adev->in_gpu_reset) { 471 uint32_t req = hub->vm_inv_eng0_req + eng; 472 uint32_t ack = hub->vm_inv_eng0_ack + eng; 473 474 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, tmp, 475 1 << vmid); 476 continue; 477 } 478 479 spin_lock(&adev->gmc.invalidate_lock); 480 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); 481 for (j = 0; j < adev->usec_timeout; j++) { 482 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 483 if (tmp & (1 << vmid)) 484 break; 485 udelay(1); 486 } 487 spin_unlock(&adev->gmc.invalidate_lock); 488 if (j < adev->usec_timeout) 489 continue; 490 491 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 492 } 493 } 494 495 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 496 unsigned vmid, uint64_t pd_addr) 497 { 498 struct amdgpu_device *adev = ring->adev; 499 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub]; 500 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 501 unsigned eng = ring->vm_inv_eng; 502 503 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid), 504 lower_32_bits(pd_addr)); 505 506 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid), 507 upper_32_bits(pd_addr)); 508 509 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng, 510 hub->vm_inv_eng0_ack + eng, 511 req, 1 << vmid); 512 513 return pd_addr; 514 } 515 516 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 517 unsigned pasid) 518 { 519 struct amdgpu_device *adev = ring->adev; 520 uint32_t reg; 521 522 /* Do nothing because there's no lut register for mmhub1. */ 523 if (ring->funcs->vmhub == AMDGPU_MMHUB_1) 524 return; 525 526 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 527 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 528 else 529 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 530 531 amdgpu_ring_emit_wreg(ring, reg, pasid); 532 } 533 534 /* 535 * PTE format on VEGA 10: 536 * 63:59 reserved 537 * 58:57 mtype 538 * 56 F 539 * 55 L 540 * 54 P 541 * 53 SW 542 * 52 T 543 * 50:48 reserved 544 * 47:12 4k physical page base address 545 * 11:7 fragment 546 * 6 write 547 * 5 read 548 * 4 exe 549 * 3 Z 550 * 2 snooped 551 * 1 system 552 * 0 valid 553 * 554 * PDE format on VEGA 10: 555 * 63:59 block fragment size 556 * 58:55 reserved 557 * 54 P 558 * 53:48 reserved 559 * 47:6 physical base address of PD or PTE 560 * 5:3 reserved 561 * 2 C 562 * 1 system 563 * 0 valid 564 */ 565 566 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, 567 uint32_t flags) 568 569 { 570 uint64_t pte_flag = 0; 571 572 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 573 pte_flag |= AMDGPU_PTE_EXECUTABLE; 574 if (flags & AMDGPU_VM_PAGE_READABLE) 575 pte_flag |= AMDGPU_PTE_READABLE; 576 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 577 pte_flag |= AMDGPU_PTE_WRITEABLE; 578 579 switch (flags & AMDGPU_VM_MTYPE_MASK) { 580 case AMDGPU_VM_MTYPE_DEFAULT: 581 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 582 break; 583 case AMDGPU_VM_MTYPE_NC: 584 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 585 break; 586 case AMDGPU_VM_MTYPE_WC: 587 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 588 break; 589 case AMDGPU_VM_MTYPE_CC: 590 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 591 break; 592 case AMDGPU_VM_MTYPE_UC: 593 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 594 break; 595 default: 596 pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 597 break; 598 } 599 600 if (flags & AMDGPU_VM_PAGE_PRT) 601 pte_flag |= AMDGPU_PTE_PRT; 602 603 return pte_flag; 604 } 605 606 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 607 uint64_t *addr, uint64_t *flags) 608 { 609 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 610 *addr = adev->vm_manager.vram_base_offset + *addr - 611 adev->gmc.vram_start; 612 BUG_ON(*addr & 0xFFFF00000000003FULL); 613 614 if (!adev->gmc.translate_further) 615 return; 616 617 if (level == AMDGPU_VM_PDB1) { 618 /* Set the block fragment size */ 619 if (!(*flags & AMDGPU_PDE_PTE)) 620 *flags |= AMDGPU_PDE_BFS(0x9); 621 622 } else if (level == AMDGPU_VM_PDB0) { 623 if (*flags & AMDGPU_PDE_PTE) 624 *flags &= ~AMDGPU_PDE_PTE; 625 else 626 *flags |= AMDGPU_PTE_TF; 627 } 628 } 629 630 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 631 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 632 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 633 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 634 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags, 635 .get_vm_pde = gmc_v9_0_get_vm_pde 636 }; 637 638 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 639 { 640 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 641 } 642 643 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 644 { 645 switch (adev->asic_type) { 646 case CHIP_VEGA20: 647 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 648 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 649 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 650 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET; 651 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 652 adev->umc.funcs = &umc_v6_1_funcs; 653 break; 654 default: 655 break; 656 } 657 } 658 659 static int gmc_v9_0_early_init(void *handle) 660 { 661 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 662 663 gmc_v9_0_set_gmc_funcs(adev); 664 gmc_v9_0_set_irq_funcs(adev); 665 gmc_v9_0_set_umc_funcs(adev); 666 667 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 668 adev->gmc.shared_aperture_end = 669 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 670 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 671 adev->gmc.private_aperture_end = 672 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 673 674 return 0; 675 } 676 677 static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev) 678 { 679 680 /* 681 * TODO: 682 * Currently there is a bug where some memory client outside 683 * of the driver writes to first 8M of VRAM on S3 resume, 684 * this overrides GART which by default gets placed in first 8M and 685 * causes VM_FAULTS once GTT is accessed. 686 * Keep the stolen memory reservation until the while this is not solved. 687 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init 688 */ 689 switch (adev->asic_type) { 690 case CHIP_VEGA10: 691 case CHIP_RAVEN: 692 case CHIP_ARCTURUS: 693 return true; 694 case CHIP_VEGA12: 695 case CHIP_VEGA20: 696 default: 697 return false; 698 } 699 } 700 701 static int gmc_v9_0_allocate_vm_inv_eng(struct amdgpu_device *adev) 702 { 703 struct amdgpu_ring *ring; 704 unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] = 705 {GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP, 706 GFXHUB_FREE_VM_INV_ENGS_BITMAP}; 707 unsigned i; 708 unsigned vmhub, inv_eng; 709 710 for (i = 0; i < adev->num_rings; ++i) { 711 ring = adev->rings[i]; 712 vmhub = ring->funcs->vmhub; 713 714 inv_eng = ffs(vm_inv_engs[vmhub]); 715 if (!inv_eng) { 716 dev_err(adev->dev, "no VM inv eng for ring %s\n", 717 ring->name); 718 return -EINVAL; 719 } 720 721 ring->vm_inv_eng = inv_eng - 1; 722 vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng); 723 724 dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n", 725 ring->name, ring->vm_inv_eng, ring->funcs->vmhub); 726 } 727 728 return 0; 729 } 730 731 static int gmc_v9_0_ecc_late_init(void *handle) 732 { 733 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 734 struct ras_common_if **ras_if = &adev->gmc.ras_if; 735 struct ras_ih_if ih_info = { 736 .cb = gmc_v9_0_process_ras_data_cb, 737 }; 738 struct ras_fs_if fs_info = { 739 .sysfs_name = "umc_err_count", 740 .debugfs_name = "umc_err_inject", 741 }; 742 struct ras_common_if ras_block = { 743 .block = AMDGPU_RAS_BLOCK__UMC, 744 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 745 .sub_block_index = 0, 746 .name = "umc", 747 }; 748 int r; 749 750 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) { 751 amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0); 752 return 0; 753 } 754 755 /* handle resume path. */ 756 if (*ras_if) { 757 /* resend ras TA enable cmd during resume. 758 * prepare to handle failure. 759 */ 760 ih_info.head = **ras_if; 761 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 762 if (r) { 763 if (r == -EAGAIN) { 764 /* request a gpu reset. will run again. */ 765 amdgpu_ras_request_reset_on_boot(adev, 766 AMDGPU_RAS_BLOCK__UMC); 767 return 0; 768 } 769 /* fail to enable ras, cleanup all. */ 770 goto irq; 771 } 772 /* enable successfully. continue. */ 773 goto resume; 774 } 775 776 *ras_if = kmalloc(sizeof(**ras_if), GFP_KERNEL); 777 if (!*ras_if) 778 return -ENOMEM; 779 780 **ras_if = ras_block; 781 782 r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1); 783 if (r) { 784 if (r == -EAGAIN) { 785 amdgpu_ras_request_reset_on_boot(adev, 786 AMDGPU_RAS_BLOCK__UMC); 787 r = 0; 788 } 789 goto feature; 790 } 791 792 ih_info.head = **ras_if; 793 fs_info.head = **ras_if; 794 795 r = amdgpu_ras_interrupt_add_handler(adev, &ih_info); 796 if (r) 797 goto interrupt; 798 799 amdgpu_ras_debugfs_create(adev, &fs_info); 800 801 r = amdgpu_ras_sysfs_create(adev, &fs_info); 802 if (r) 803 goto sysfs; 804 resume: 805 r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); 806 if (r) 807 goto irq; 808 809 return 0; 810 irq: 811 amdgpu_ras_sysfs_remove(adev, *ras_if); 812 sysfs: 813 amdgpu_ras_debugfs_remove(adev, *ras_if); 814 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 815 interrupt: 816 amdgpu_ras_feature_enable(adev, *ras_if, 0); 817 feature: 818 kfree(*ras_if); 819 *ras_if = NULL; 820 return r; 821 } 822 823 824 static int gmc_v9_0_late_init(void *handle) 825 { 826 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 827 bool r; 828 829 if (!gmc_v9_0_keep_stolen_memory(adev)) 830 amdgpu_bo_late_init(adev); 831 832 r = gmc_v9_0_allocate_vm_inv_eng(adev); 833 if (r) 834 return r; 835 /* Check if ecc is available */ 836 if (!amdgpu_sriov_vf(adev)) { 837 switch (adev->asic_type) { 838 case CHIP_VEGA10: 839 case CHIP_VEGA20: 840 r = amdgpu_atomfirmware_mem_ecc_supported(adev); 841 if (!r) { 842 DRM_INFO("ECC is not present.\n"); 843 if (adev->df_funcs->enable_ecc_force_par_wr_rmw) 844 adev->df_funcs->enable_ecc_force_par_wr_rmw(adev, false); 845 } else { 846 DRM_INFO("ECC is active.\n"); 847 } 848 849 r = amdgpu_atomfirmware_sram_ecc_supported(adev); 850 if (!r) { 851 DRM_INFO("SRAM ECC is not present.\n"); 852 } else { 853 DRM_INFO("SRAM ECC is active.\n"); 854 } 855 break; 856 default: 857 break; 858 } 859 } 860 861 r = gmc_v9_0_ecc_late_init(handle); 862 if (r) 863 return r; 864 865 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 866 } 867 868 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 869 struct amdgpu_gmc *mc) 870 { 871 u64 base = 0; 872 if (!amdgpu_sriov_vf(adev)) { 873 if (adev->asic_type == CHIP_ARCTURUS) 874 base = mmhub_v9_4_get_fb_location(adev); 875 else 876 base = mmhub_v1_0_get_fb_location(adev); 877 } 878 /* add the xgmi offset of the physical node */ 879 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 880 amdgpu_gmc_vram_location(adev, mc, base); 881 amdgpu_gmc_gart_location(adev, mc); 882 if (!amdgpu_sriov_vf(adev)) 883 amdgpu_gmc_agp_location(adev, mc); 884 /* base offset of vram pages */ 885 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); 886 887 /* XXX: add the xgmi offset of the physical node? */ 888 adev->vm_manager.vram_base_offset += 889 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 890 } 891 892 /** 893 * gmc_v9_0_mc_init - initialize the memory controller driver params 894 * 895 * @adev: amdgpu_device pointer 896 * 897 * Look up the amount of vram, vram width, and decide how to place 898 * vram and gart within the GPU's physical address space. 899 * Returns 0 for success. 900 */ 901 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 902 { 903 int chansize, numchan; 904 int r; 905 906 if (amdgpu_sriov_vf(adev)) { 907 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 908 * and DF related registers is not readable, seems hardcord is the 909 * only way to set the correct vram_width 910 */ 911 adev->gmc.vram_width = 2048; 912 } else if (amdgpu_emu_mode != 1) { 913 adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); 914 } 915 916 if (!adev->gmc.vram_width) { 917 /* hbm memory channel size */ 918 if (adev->flags & AMD_IS_APU) 919 chansize = 64; 920 else 921 chansize = 128; 922 923 numchan = adev->df_funcs->get_hbm_channel_number(adev); 924 adev->gmc.vram_width = numchan * chansize; 925 } 926 927 /* size in MB on si */ 928 adev->gmc.mc_vram_size = 929 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; 930 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 931 932 if (!(adev->flags & AMD_IS_APU)) { 933 r = amdgpu_device_resize_fb_bar(adev); 934 if (r) 935 return r; 936 } 937 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 938 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 939 940 #ifdef CONFIG_X86_64 941 if (adev->flags & AMD_IS_APU) { 942 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev); 943 adev->gmc.aper_size = adev->gmc.real_vram_size; 944 } 945 #endif 946 /* In case the PCI BAR is larger than the actual amount of vram */ 947 adev->gmc.visible_vram_size = adev->gmc.aper_size; 948 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 949 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 950 951 /* set the gart size */ 952 if (amdgpu_gart_size == -1) { 953 switch (adev->asic_type) { 954 case CHIP_VEGA10: /* all engines support GPUVM */ 955 case CHIP_VEGA12: /* all engines support GPUVM */ 956 case CHIP_VEGA20: 957 case CHIP_ARCTURUS: 958 default: 959 adev->gmc.gart_size = 512ULL << 20; 960 break; 961 case CHIP_RAVEN: /* DCE SG support */ 962 adev->gmc.gart_size = 1024ULL << 20; 963 break; 964 } 965 } else { 966 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 967 } 968 969 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 970 971 return 0; 972 } 973 974 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 975 { 976 int r; 977 978 if (adev->gart.bo) { 979 WARN(1, "VEGA10 PCIE GART already initialized\n"); 980 return 0; 981 } 982 /* Initialize common gart structure */ 983 r = amdgpu_gart_init(adev); 984 if (r) 985 return r; 986 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 987 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 988 AMDGPU_PTE_EXECUTABLE; 989 return amdgpu_gart_table_vram_alloc(adev); 990 } 991 992 static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 993 { 994 u32 d1vga_control; 995 unsigned size; 996 997 /* 998 * TODO Remove once GART corruption is resolved 999 * Check related code in gmc_v9_0_sw_fini 1000 * */ 1001 if (gmc_v9_0_keep_stolen_memory(adev)) 1002 return 9 * 1024 * 1024; 1003 1004 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1005 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1006 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 1007 } else { 1008 u32 viewport; 1009 1010 switch (adev->asic_type) { 1011 case CHIP_RAVEN: 1012 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1013 size = (REG_GET_FIELD(viewport, 1014 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1015 REG_GET_FIELD(viewport, 1016 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1017 4); 1018 break; 1019 case CHIP_VEGA10: 1020 case CHIP_VEGA12: 1021 case CHIP_VEGA20: 1022 default: 1023 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1024 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1025 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1026 4); 1027 break; 1028 } 1029 } 1030 /* return 0 if the pre-OS buffer uses up most of vram */ 1031 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 1032 return 0; 1033 1034 return size; 1035 } 1036 1037 static int gmc_v9_0_sw_init(void *handle) 1038 { 1039 int r; 1040 int dma_bits; 1041 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1042 1043 gfxhub_v1_0_init(adev); 1044 if (adev->asic_type == CHIP_ARCTURUS) 1045 mmhub_v9_4_init(adev); 1046 else 1047 mmhub_v1_0_init(adev); 1048 1049 spin_lock_init(&adev->gmc.invalidate_lock); 1050 1051 adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); 1052 switch (adev->asic_type) { 1053 case CHIP_RAVEN: 1054 adev->num_vmhubs = 2; 1055 1056 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1057 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1058 } else { 1059 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1060 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1061 adev->gmc.translate_further = 1062 adev->vm_manager.num_level > 1; 1063 } 1064 break; 1065 case CHIP_VEGA10: 1066 case CHIP_VEGA12: 1067 case CHIP_VEGA20: 1068 adev->num_vmhubs = 2; 1069 1070 /* 1071 * To fulfill 4-level page support, 1072 * vm size is 256TB (48bit), maximum size of Vega10, 1073 * block size 512 (9bit) 1074 */ 1075 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 1076 if (amdgpu_sriov_vf(adev)) 1077 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 1078 else 1079 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1080 break; 1081 case CHIP_ARCTURUS: 1082 adev->num_vmhubs = 3; 1083 1084 /* Keep the vm size same with Vega20 */ 1085 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1086 break; 1087 default: 1088 break; 1089 } 1090 1091 /* This interrupt is VMC page fault.*/ 1092 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1093 &adev->gmc.vm_fault); 1094 if (r) 1095 return r; 1096 1097 if (adev->asic_type == CHIP_ARCTURUS) { 1098 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1099 &adev->gmc.vm_fault); 1100 if (r) 1101 return r; 1102 } 1103 1104 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1105 &adev->gmc.vm_fault); 1106 1107 if (r) 1108 return r; 1109 1110 /* interrupt sent to DF. */ 1111 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1112 &adev->gmc.ecc_irq); 1113 if (r) 1114 return r; 1115 1116 /* Set the internal MC address mask 1117 * This is the max address of the GPU's 1118 * internal address space. 1119 */ 1120 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1121 1122 /* set DMA mask + need_dma32 flags. 1123 * PCIE - can handle 44-bits. 1124 * IGP - can handle 44-bits 1125 * PCI - dma32 for legacy pci gart, 44 bits on vega10 1126 */ 1127 adev->need_dma32 = false; 1128 dma_bits = adev->need_dma32 ? 32 : 44; 1129 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1130 if (r) { 1131 adev->need_dma32 = true; 1132 dma_bits = 32; 1133 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 1134 } 1135 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1136 if (r) { 1137 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 1138 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); 1139 } 1140 adev->need_swiotlb = drm_need_swiotlb(dma_bits); 1141 1142 if (adev->gmc.xgmi.supported) { 1143 r = gfxhub_v1_1_get_xgmi_info(adev); 1144 if (r) 1145 return r; 1146 } 1147 1148 r = gmc_v9_0_mc_init(adev); 1149 if (r) 1150 return r; 1151 1152 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev); 1153 1154 /* Memory manager */ 1155 r = amdgpu_bo_init(adev); 1156 if (r) 1157 return r; 1158 1159 r = gmc_v9_0_gart_init(adev); 1160 if (r) 1161 return r; 1162 1163 /* 1164 * number of VMs 1165 * VMID 0 is reserved for System 1166 * amdgpu graphics/compute will use VMIDs 1-7 1167 * amdkfd will use VMIDs 8-15 1168 */ 1169 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 1170 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; 1171 adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS; 1172 1173 amdgpu_vm_manager_init(adev); 1174 1175 return 0; 1176 } 1177 1178 static int gmc_v9_0_sw_fini(void *handle) 1179 { 1180 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1181 1182 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) && 1183 adev->gmc.ras_if) { 1184 struct ras_common_if *ras_if = adev->gmc.ras_if; 1185 struct ras_ih_if ih_info = { 1186 .head = *ras_if, 1187 }; 1188 1189 /*remove fs first*/ 1190 amdgpu_ras_debugfs_remove(adev, ras_if); 1191 amdgpu_ras_sysfs_remove(adev, ras_if); 1192 /*remove the IH*/ 1193 amdgpu_ras_interrupt_remove_handler(adev, &ih_info); 1194 amdgpu_ras_feature_enable(adev, ras_if, 0); 1195 kfree(ras_if); 1196 } 1197 1198 amdgpu_gem_force_release(adev); 1199 amdgpu_vm_manager_fini(adev); 1200 1201 if (gmc_v9_0_keep_stolen_memory(adev)) 1202 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL); 1203 1204 amdgpu_gart_table_vram_free(adev); 1205 amdgpu_bo_fini(adev); 1206 amdgpu_gart_fini(adev); 1207 1208 return 0; 1209 } 1210 1211 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 1212 { 1213 1214 switch (adev->asic_type) { 1215 case CHIP_VEGA10: 1216 if (amdgpu_sriov_vf(adev)) 1217 break; 1218 /* fall through */ 1219 case CHIP_VEGA20: 1220 soc15_program_register_sequence(adev, 1221 golden_settings_mmhub_1_0_0, 1222 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 1223 soc15_program_register_sequence(adev, 1224 golden_settings_athub_1_0_0, 1225 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1226 break; 1227 case CHIP_VEGA12: 1228 break; 1229 case CHIP_RAVEN: 1230 soc15_program_register_sequence(adev, 1231 golden_settings_athub_1_0_0, 1232 ARRAY_SIZE(golden_settings_athub_1_0_0)); 1233 break; 1234 default: 1235 break; 1236 } 1237 } 1238 1239 /** 1240 * gmc_v9_0_gart_enable - gart enable 1241 * 1242 * @adev: amdgpu_device pointer 1243 */ 1244 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 1245 { 1246 int r; 1247 bool value; 1248 u32 tmp; 1249 1250 amdgpu_device_program_register_sequence(adev, 1251 golden_settings_vega10_hdp, 1252 ARRAY_SIZE(golden_settings_vega10_hdp)); 1253 1254 if (adev->gart.bo == NULL) { 1255 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1256 return -EINVAL; 1257 } 1258 r = amdgpu_gart_table_vram_pin(adev); 1259 if (r) 1260 return r; 1261 1262 switch (adev->asic_type) { 1263 case CHIP_RAVEN: 1264 mmhub_v1_0_update_power_gating(adev, true); 1265 break; 1266 default: 1267 break; 1268 } 1269 1270 r = gfxhub_v1_0_gart_enable(adev); 1271 if (r) 1272 return r; 1273 1274 if (adev->asic_type == CHIP_ARCTURUS) 1275 r = mmhub_v9_4_gart_enable(adev); 1276 else 1277 r = mmhub_v1_0_gart_enable(adev); 1278 if (r) 1279 return r; 1280 1281 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); 1282 1283 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); 1284 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); 1285 1286 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 1287 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); 1288 1289 /* After HDP is initialized, flush HDP.*/ 1290 adev->nbio_funcs->hdp_flush(adev, NULL); 1291 1292 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 1293 value = false; 1294 else 1295 value = true; 1296 1297 gfxhub_v1_0_set_fault_enable_default(adev, value); 1298 if (adev->asic_type == CHIP_ARCTURUS) 1299 mmhub_v9_4_set_fault_enable_default(adev, value); 1300 else 1301 mmhub_v1_0_set_fault_enable_default(adev, value); 1302 gmc_v9_0_flush_gpu_tlb(adev, 0, 0); 1303 1304 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1305 (unsigned)(adev->gmc.gart_size >> 20), 1306 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1307 adev->gart.ready = true; 1308 return 0; 1309 } 1310 1311 static int gmc_v9_0_hw_init(void *handle) 1312 { 1313 int r; 1314 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1315 1316 /* The sequence of these two function calls matters.*/ 1317 gmc_v9_0_init_golden_registers(adev); 1318 1319 if (adev->mode_info.num_crtc) { 1320 /* Lockout access through VGA aperture*/ 1321 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 1322 1323 /* disable VGA render */ 1324 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 1325 } 1326 1327 r = gmc_v9_0_gart_enable(adev); 1328 1329 return r; 1330 } 1331 1332 /** 1333 * gmc_v9_0_gart_disable - gart disable 1334 * 1335 * @adev: amdgpu_device pointer 1336 * 1337 * This disables all VM page table. 1338 */ 1339 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 1340 { 1341 gfxhub_v1_0_gart_disable(adev); 1342 if (adev->asic_type == CHIP_ARCTURUS) 1343 mmhub_v9_4_gart_disable(adev); 1344 else 1345 mmhub_v1_0_gart_disable(adev); 1346 amdgpu_gart_table_vram_unpin(adev); 1347 } 1348 1349 static int gmc_v9_0_hw_fini(void *handle) 1350 { 1351 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1352 1353 if (amdgpu_sriov_vf(adev)) { 1354 /* full access mode, so don't touch any GMC register */ 1355 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1356 return 0; 1357 } 1358 1359 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1360 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1361 gmc_v9_0_gart_disable(adev); 1362 1363 return 0; 1364 } 1365 1366 static int gmc_v9_0_suspend(void *handle) 1367 { 1368 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1369 1370 return gmc_v9_0_hw_fini(adev); 1371 } 1372 1373 static int gmc_v9_0_resume(void *handle) 1374 { 1375 int r; 1376 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1377 1378 r = gmc_v9_0_hw_init(adev); 1379 if (r) 1380 return r; 1381 1382 amdgpu_vmid_reset_all(adev); 1383 1384 return 0; 1385 } 1386 1387 static bool gmc_v9_0_is_idle(void *handle) 1388 { 1389 /* MC is always ready in GMC v9.*/ 1390 return true; 1391 } 1392 1393 static int gmc_v9_0_wait_for_idle(void *handle) 1394 { 1395 /* There is no need to wait for MC idle in GMC v9.*/ 1396 return 0; 1397 } 1398 1399 static int gmc_v9_0_soft_reset(void *handle) 1400 { 1401 /* XXX for emulation.*/ 1402 return 0; 1403 } 1404 1405 static int gmc_v9_0_set_clockgating_state(void *handle, 1406 enum amd_clockgating_state state) 1407 { 1408 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1409 1410 if (adev->asic_type == CHIP_ARCTURUS) 1411 return 0; 1412 1413 return mmhub_v1_0_set_clockgating(adev, state); 1414 } 1415 1416 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags) 1417 { 1418 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1419 1420 if (adev->asic_type == CHIP_ARCTURUS) 1421 return; 1422 1423 mmhub_v1_0_get_clockgating(adev, flags); 1424 } 1425 1426 static int gmc_v9_0_set_powergating_state(void *handle, 1427 enum amd_powergating_state state) 1428 { 1429 return 0; 1430 } 1431 1432 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 1433 .name = "gmc_v9_0", 1434 .early_init = gmc_v9_0_early_init, 1435 .late_init = gmc_v9_0_late_init, 1436 .sw_init = gmc_v9_0_sw_init, 1437 .sw_fini = gmc_v9_0_sw_fini, 1438 .hw_init = gmc_v9_0_hw_init, 1439 .hw_fini = gmc_v9_0_hw_fini, 1440 .suspend = gmc_v9_0_suspend, 1441 .resume = gmc_v9_0_resume, 1442 .is_idle = gmc_v9_0_is_idle, 1443 .wait_for_idle = gmc_v9_0_wait_for_idle, 1444 .soft_reset = gmc_v9_0_soft_reset, 1445 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 1446 .set_powergating_state = gmc_v9_0_set_powergating_state, 1447 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 1448 }; 1449 1450 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 1451 { 1452 .type = AMD_IP_BLOCK_TYPE_GMC, 1453 .major = 9, 1454 .minor = 0, 1455 .rev = 0, 1456 .funcs = &gmc_v9_0_ip_funcs, 1457 }; 1458