1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "umc_v12_0.h" 60 #include "ras_umc_v12_0.h" 61 #include "hdp_v4_0.h" 62 #include "mca_v3_0.h" 63 64 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 65 66 #include "amdgpu_ras.h" 67 #include "amdgpu_xgmi.h" 68 69 /* add these here since we already include dce12 headers and these are for DCN */ 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 71 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 75 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 77 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 78 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 80 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 81 82 static const char * const gfxhub_client_ids[] = { 83 "CB", 84 "DB", 85 "IA", 86 "WD", 87 "CPF", 88 "CPC", 89 "CPG", 90 "RLC", 91 "TCP", 92 "SQC (inst)", 93 "SQC (data)", 94 "SQG", 95 "PA", 96 }; 97 98 static const char *mmhub_client_ids_raven[][2] = { 99 [0][0] = "MP1", 100 [1][0] = "MP0", 101 [2][0] = "VCN", 102 [3][0] = "VCNU", 103 [4][0] = "HDP", 104 [5][0] = "DCE", 105 [13][0] = "UTCL2", 106 [19][0] = "TLS", 107 [26][0] = "OSS", 108 [27][0] = "SDMA0", 109 [0][1] = "MP1", 110 [1][1] = "MP0", 111 [2][1] = "VCN", 112 [3][1] = "VCNU", 113 [4][1] = "HDP", 114 [5][1] = "XDP", 115 [6][1] = "DBGU0", 116 [7][1] = "DCE", 117 [8][1] = "DCEDWB0", 118 [9][1] = "DCEDWB1", 119 [26][1] = "OSS", 120 [27][1] = "SDMA0", 121 }; 122 123 static const char *mmhub_client_ids_renoir[][2] = { 124 [0][0] = "MP1", 125 [1][0] = "MP0", 126 [2][0] = "HDP", 127 [4][0] = "DCEDMC", 128 [5][0] = "DCEVGA", 129 [13][0] = "UTCL2", 130 [19][0] = "TLS", 131 [26][0] = "OSS", 132 [27][0] = "SDMA0", 133 [28][0] = "VCN", 134 [29][0] = "VCNU", 135 [30][0] = "JPEG", 136 [0][1] = "MP1", 137 [1][1] = "MP0", 138 [2][1] = "HDP", 139 [3][1] = "XDP", 140 [6][1] = "DBGU0", 141 [7][1] = "DCEDMC", 142 [8][1] = "DCEVGA", 143 [9][1] = "DCEDWB", 144 [26][1] = "OSS", 145 [27][1] = "SDMA0", 146 [28][1] = "VCN", 147 [29][1] = "VCNU", 148 [30][1] = "JPEG", 149 }; 150 151 static const char *mmhub_client_ids_vega10[][2] = { 152 [0][0] = "MP0", 153 [1][0] = "UVD", 154 [2][0] = "UVDU", 155 [3][0] = "HDP", 156 [13][0] = "UTCL2", 157 [14][0] = "OSS", 158 [15][0] = "SDMA1", 159 [32+0][0] = "VCE0", 160 [32+1][0] = "VCE0U", 161 [32+2][0] = "XDMA", 162 [32+3][0] = "DCE", 163 [32+4][0] = "MP1", 164 [32+14][0] = "SDMA0", 165 [0][1] = "MP0", 166 [1][1] = "UVD", 167 [2][1] = "UVDU", 168 [3][1] = "DBGU0", 169 [4][1] = "HDP", 170 [5][1] = "XDP", 171 [14][1] = "OSS", 172 [15][1] = "SDMA0", 173 [32+0][1] = "VCE0", 174 [32+1][1] = "VCE0U", 175 [32+2][1] = "XDMA", 176 [32+3][1] = "DCE", 177 [32+4][1] = "DCEDWB", 178 [32+5][1] = "MP1", 179 [32+6][1] = "DBGU1", 180 [32+14][1] = "SDMA1", 181 }; 182 183 static const char *mmhub_client_ids_vega12[][2] = { 184 [0][0] = "MP0", 185 [1][0] = "VCE0", 186 [2][0] = "VCE0U", 187 [3][0] = "HDP", 188 [13][0] = "UTCL2", 189 [14][0] = "OSS", 190 [15][0] = "SDMA1", 191 [32+0][0] = "DCE", 192 [32+1][0] = "XDMA", 193 [32+2][0] = "UVD", 194 [32+3][0] = "UVDU", 195 [32+4][0] = "MP1", 196 [32+15][0] = "SDMA0", 197 [0][1] = "MP0", 198 [1][1] = "VCE0", 199 [2][1] = "VCE0U", 200 [3][1] = "DBGU0", 201 [4][1] = "HDP", 202 [5][1] = "XDP", 203 [14][1] = "OSS", 204 [15][1] = "SDMA0", 205 [32+0][1] = "DCE", 206 [32+1][1] = "DCEDWB", 207 [32+2][1] = "XDMA", 208 [32+3][1] = "UVD", 209 [32+4][1] = "UVDU", 210 [32+5][1] = "MP1", 211 [32+6][1] = "DBGU1", 212 [32+15][1] = "SDMA1", 213 }; 214 215 static const char *mmhub_client_ids_vega20[][2] = { 216 [0][0] = "XDMA", 217 [1][0] = "DCE", 218 [2][0] = "VCE0", 219 [3][0] = "VCE0U", 220 [4][0] = "UVD", 221 [5][0] = "UVD1U", 222 [13][0] = "OSS", 223 [14][0] = "HDP", 224 [15][0] = "SDMA0", 225 [32+0][0] = "UVD", 226 [32+1][0] = "UVDU", 227 [32+2][0] = "MP1", 228 [32+3][0] = "MP0", 229 [32+12][0] = "UTCL2", 230 [32+14][0] = "SDMA1", 231 [0][1] = "XDMA", 232 [1][1] = "DCE", 233 [2][1] = "DCEDWB", 234 [3][1] = "VCE0", 235 [4][1] = "VCE0U", 236 [5][1] = "UVD1", 237 [6][1] = "UVD1U", 238 [7][1] = "DBGU0", 239 [8][1] = "XDP", 240 [13][1] = "OSS", 241 [14][1] = "HDP", 242 [15][1] = "SDMA0", 243 [32+0][1] = "UVD", 244 [32+1][1] = "UVDU", 245 [32+2][1] = "DBGU1", 246 [32+3][1] = "MP1", 247 [32+4][1] = "MP0", 248 [32+14][1] = "SDMA1", 249 }; 250 251 static const char *mmhub_client_ids_arcturus[][2] = { 252 [0][0] = "DBGU1", 253 [1][0] = "XDP", 254 [2][0] = "MP1", 255 [14][0] = "HDP", 256 [171][0] = "JPEG", 257 [172][0] = "VCN", 258 [173][0] = "VCNU", 259 [203][0] = "JPEG1", 260 [204][0] = "VCN1", 261 [205][0] = "VCN1U", 262 [256][0] = "SDMA0", 263 [257][0] = "SDMA1", 264 [258][0] = "SDMA2", 265 [259][0] = "SDMA3", 266 [260][0] = "SDMA4", 267 [261][0] = "SDMA5", 268 [262][0] = "SDMA6", 269 [263][0] = "SDMA7", 270 [384][0] = "OSS", 271 [0][1] = "DBGU1", 272 [1][1] = "XDP", 273 [2][1] = "MP1", 274 [14][1] = "HDP", 275 [171][1] = "JPEG", 276 [172][1] = "VCN", 277 [173][1] = "VCNU", 278 [203][1] = "JPEG1", 279 [204][1] = "VCN1", 280 [205][1] = "VCN1U", 281 [256][1] = "SDMA0", 282 [257][1] = "SDMA1", 283 [258][1] = "SDMA2", 284 [259][1] = "SDMA3", 285 [260][1] = "SDMA4", 286 [261][1] = "SDMA5", 287 [262][1] = "SDMA6", 288 [263][1] = "SDMA7", 289 [384][1] = "OSS", 290 }; 291 292 static const char *mmhub_client_ids_aldebaran[][2] = { 293 [2][0] = "MP1", 294 [3][0] = "MP0", 295 [32+1][0] = "DBGU_IO0", 296 [32+2][0] = "DBGU_IO2", 297 [32+4][0] = "MPIO", 298 [96+11][0] = "JPEG0", 299 [96+12][0] = "VCN0", 300 [96+13][0] = "VCNU0", 301 [128+11][0] = "JPEG1", 302 [128+12][0] = "VCN1", 303 [128+13][0] = "VCNU1", 304 [160+1][0] = "XDP", 305 [160+14][0] = "HDP", 306 [256+0][0] = "SDMA0", 307 [256+1][0] = "SDMA1", 308 [256+2][0] = "SDMA2", 309 [256+3][0] = "SDMA3", 310 [256+4][0] = "SDMA4", 311 [384+0][0] = "OSS", 312 [2][1] = "MP1", 313 [3][1] = "MP0", 314 [32+1][1] = "DBGU_IO0", 315 [32+2][1] = "DBGU_IO2", 316 [32+4][1] = "MPIO", 317 [96+11][1] = "JPEG0", 318 [96+12][1] = "VCN0", 319 [96+13][1] = "VCNU0", 320 [128+11][1] = "JPEG1", 321 [128+12][1] = "VCN1", 322 [128+13][1] = "VCNU1", 323 [160+1][1] = "XDP", 324 [160+14][1] = "HDP", 325 [256+0][1] = "SDMA0", 326 [256+1][1] = "SDMA1", 327 [256+2][1] = "SDMA2", 328 [256+3][1] = "SDMA3", 329 [256+4][1] = "SDMA4", 330 [384+0][1] = "OSS", 331 }; 332 333 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { 334 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 335 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 336 }; 337 338 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { 339 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 340 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 341 }; 342 343 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 344 (0x000143c0 + 0x00000000), 345 (0x000143c0 + 0x00000800), 346 (0x000143c0 + 0x00001000), 347 (0x000143c0 + 0x00001800), 348 (0x000543c0 + 0x00000000), 349 (0x000543c0 + 0x00000800), 350 (0x000543c0 + 0x00001000), 351 (0x000543c0 + 0x00001800), 352 (0x000943c0 + 0x00000000), 353 (0x000943c0 + 0x00000800), 354 (0x000943c0 + 0x00001000), 355 (0x000943c0 + 0x00001800), 356 (0x000d43c0 + 0x00000000), 357 (0x000d43c0 + 0x00000800), 358 (0x000d43c0 + 0x00001000), 359 (0x000d43c0 + 0x00001800), 360 (0x001143c0 + 0x00000000), 361 (0x001143c0 + 0x00000800), 362 (0x001143c0 + 0x00001000), 363 (0x001143c0 + 0x00001800), 364 (0x001543c0 + 0x00000000), 365 (0x001543c0 + 0x00000800), 366 (0x001543c0 + 0x00001000), 367 (0x001543c0 + 0x00001800), 368 (0x001943c0 + 0x00000000), 369 (0x001943c0 + 0x00000800), 370 (0x001943c0 + 0x00001000), 371 (0x001943c0 + 0x00001800), 372 (0x001d43c0 + 0x00000000), 373 (0x001d43c0 + 0x00000800), 374 (0x001d43c0 + 0x00001000), 375 (0x001d43c0 + 0x00001800), 376 }; 377 378 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 379 (0x000143e0 + 0x00000000), 380 (0x000143e0 + 0x00000800), 381 (0x000143e0 + 0x00001000), 382 (0x000143e0 + 0x00001800), 383 (0x000543e0 + 0x00000000), 384 (0x000543e0 + 0x00000800), 385 (0x000543e0 + 0x00001000), 386 (0x000543e0 + 0x00001800), 387 (0x000943e0 + 0x00000000), 388 (0x000943e0 + 0x00000800), 389 (0x000943e0 + 0x00001000), 390 (0x000943e0 + 0x00001800), 391 (0x000d43e0 + 0x00000000), 392 (0x000d43e0 + 0x00000800), 393 (0x000d43e0 + 0x00001000), 394 (0x000d43e0 + 0x00001800), 395 (0x001143e0 + 0x00000000), 396 (0x001143e0 + 0x00000800), 397 (0x001143e0 + 0x00001000), 398 (0x001143e0 + 0x00001800), 399 (0x001543e0 + 0x00000000), 400 (0x001543e0 + 0x00000800), 401 (0x001543e0 + 0x00001000), 402 (0x001543e0 + 0x00001800), 403 (0x001943e0 + 0x00000000), 404 (0x001943e0 + 0x00000800), 405 (0x001943e0 + 0x00001000), 406 (0x001943e0 + 0x00001800), 407 (0x001d43e0 + 0x00000000), 408 (0x001d43e0 + 0x00000800), 409 (0x001d43e0 + 0x00001000), 410 (0x001d43e0 + 0x00001800), 411 }; 412 413 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 414 struct amdgpu_irq_src *src, 415 unsigned int type, 416 enum amdgpu_interrupt_state state) 417 { 418 u32 bits, i, tmp, reg; 419 420 /* Devices newer then VEGA10/12 shall have these programming 421 * sequences performed by PSP BL 422 */ 423 if (adev->asic_type >= CHIP_VEGA20) 424 return 0; 425 426 bits = 0x7f; 427 428 switch (state) { 429 case AMDGPU_IRQ_STATE_DISABLE: 430 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 431 reg = ecc_umc_mcumc_ctrl_addrs[i]; 432 tmp = RREG32(reg); 433 tmp &= ~bits; 434 WREG32(reg, tmp); 435 } 436 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 437 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 438 tmp = RREG32(reg); 439 tmp &= ~bits; 440 WREG32(reg, tmp); 441 } 442 break; 443 case AMDGPU_IRQ_STATE_ENABLE: 444 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 445 reg = ecc_umc_mcumc_ctrl_addrs[i]; 446 tmp = RREG32(reg); 447 tmp |= bits; 448 WREG32(reg, tmp); 449 } 450 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 451 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 452 tmp = RREG32(reg); 453 tmp |= bits; 454 WREG32(reg, tmp); 455 } 456 break; 457 default: 458 break; 459 } 460 461 return 0; 462 } 463 464 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 465 struct amdgpu_irq_src *src, 466 unsigned int type, 467 enum amdgpu_interrupt_state state) 468 { 469 struct amdgpu_vmhub *hub; 470 u32 tmp, reg, bits, i, j; 471 472 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 473 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 479 480 switch (state) { 481 case AMDGPU_IRQ_STATE_DISABLE: 482 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 483 hub = &adev->vmhub[j]; 484 for (i = 0; i < 16; i++) { 485 reg = hub->vm_context0_cntl + i; 486 487 /* This works because this interrupt is only 488 * enabled at init/resume and disabled in 489 * fini/suspend, so the overall state doesn't 490 * change over the course of suspend/resume. 491 */ 492 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 493 continue; 494 495 if (j >= AMDGPU_MMHUB0(0)) 496 tmp = RREG32_SOC15_IP(MMHUB, reg); 497 else 498 tmp = RREG32_XCC(reg, j); 499 500 tmp &= ~bits; 501 502 if (j >= AMDGPU_MMHUB0(0)) 503 WREG32_SOC15_IP(MMHUB, reg, tmp); 504 else 505 WREG32_XCC(reg, tmp, j); 506 } 507 } 508 break; 509 case AMDGPU_IRQ_STATE_ENABLE: 510 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 511 hub = &adev->vmhub[j]; 512 for (i = 0; i < 16; i++) { 513 reg = hub->vm_context0_cntl + i; 514 515 /* This works because this interrupt is only 516 * enabled at init/resume and disabled in 517 * fini/suspend, so the overall state doesn't 518 * change over the course of suspend/resume. 519 */ 520 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 521 continue; 522 523 if (j >= AMDGPU_MMHUB0(0)) 524 tmp = RREG32_SOC15_IP(MMHUB, reg); 525 else 526 tmp = RREG32_XCC(reg, j); 527 528 tmp |= bits; 529 530 if (j >= AMDGPU_MMHUB0(0)) 531 WREG32_SOC15_IP(MMHUB, reg, tmp); 532 else 533 WREG32_XCC(reg, tmp, j); 534 } 535 } 536 break; 537 default: 538 break; 539 } 540 541 return 0; 542 } 543 544 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 545 struct amdgpu_irq_src *source, 546 struct amdgpu_iv_entry *entry) 547 { 548 bool retry_fault = !!(entry->src_data[1] & 549 AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY); 550 bool write_fault = !!(entry->src_data[1] & 551 AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE); 552 uint32_t status = 0, cid = 0, rw = 0, fed = 0; 553 struct amdgpu_task_info *task_info; 554 struct amdgpu_vmhub *hub; 555 const char *mmhub_cid; 556 const char *hub_name; 557 unsigned int vmhub; 558 u64 addr; 559 uint32_t cam_index = 0; 560 int ret, xcc_id = 0; 561 uint32_t node_id; 562 563 node_id = entry->node_id; 564 565 addr = (u64)entry->src_data[0] << 12; 566 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 567 568 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 569 hub_name = "mmhub0"; 570 vmhub = AMDGPU_MMHUB0(node_id / 4); 571 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 572 hub_name = "mmhub1"; 573 vmhub = AMDGPU_MMHUB1(0); 574 } else { 575 hub_name = "gfxhub0"; 576 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 577 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 578 node_id); 579 if (xcc_id < 0) 580 xcc_id = 0; 581 } 582 vmhub = xcc_id; 583 } 584 hub = &adev->vmhub[vmhub]; 585 586 if (retry_fault) { 587 cam_index = entry->src_data[2] & 0x3ff; 588 589 ret = amdgpu_gmc_handle_retry_fault(adev, entry, addr, cam_index, node_id, 590 write_fault); 591 /* Returning 1 here also prevents sending the IV to the KFD */ 592 if (ret == 1) 593 return 1; 594 } 595 596 if (kgd2kfd_vmfault_fast_path(adev, entry, retry_fault)) 597 return 1; 598 599 if (!printk_ratelimit()) 600 return 0; 601 602 dev_err(adev->dev, 603 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name, 604 retry_fault ? "retry" : "no-retry", 605 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 606 607 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 608 if (task_info) { 609 amdgpu_vm_print_task_info(adev, task_info); 610 amdgpu_vm_put_task_info(task_info); 611 } 612 613 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 614 addr, entry->client_id, 615 soc15_ih_clientid_name[entry->client_id]); 616 617 if (amdgpu_is_multi_aid(adev)) 618 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 619 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 620 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 621 622 if (amdgpu_sriov_vf(adev)) 623 return 0; 624 625 /* 626 * Issue a dummy read to wait for the status register to 627 * be updated to avoid reading an incorrect value due to 628 * the new fast GRBM interface. 629 */ 630 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 631 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 632 RREG32(hub->vm_l2_pro_fault_status); 633 634 status = RREG32(hub->vm_l2_pro_fault_status); 635 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 636 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 637 fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED); 638 639 /* for fed error, kfd will handle it, return directly */ 640 if (fed && amdgpu_ras_is_poison_mode_supported(adev) && 641 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2))) 642 return 0; 643 644 /* Only print L2 fault status if the status register could be read and 645 * contains useful information 646 */ 647 if (!status) 648 return 0; 649 650 if (!amdgpu_sriov_vf(adev)) 651 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 652 653 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub); 654 655 dev_err(adev->dev, 656 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 657 status); 658 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 659 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 660 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 661 gfxhub_client_ids[cid], 662 cid); 663 } else { 664 mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); 665 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 666 mmhub_cid ? mmhub_cid : "unknown", cid); 667 } 668 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 669 REG_GET_FIELD(status, 670 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 671 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 672 REG_GET_FIELD(status, 673 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 674 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 675 REG_GET_FIELD(status, 676 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 677 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 678 REG_GET_FIELD(status, 679 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 680 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 681 return 0; 682 } 683 684 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 685 .set = gmc_v9_0_vm_fault_interrupt_state, 686 .process = gmc_v9_0_process_interrupt, 687 }; 688 689 690 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 691 .set = gmc_v9_0_ecc_interrupt_state, 692 .process = amdgpu_umc_process_ecc_irq, 693 }; 694 695 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 696 { 697 adev->gmc.vm_fault.num_types = 1; 698 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 699 700 if (!amdgpu_sriov_vf(adev) && 701 !adev->gmc.xgmi.connected_to_cpu && 702 !adev->gmc.is_app_apu) { 703 adev->gmc.ecc_irq.num_types = 1; 704 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 705 } 706 } 707 708 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 709 uint32_t flush_type) 710 { 711 u32 req = 0; 712 713 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 714 PER_VMID_INVALIDATE_REQ, 1 << vmid); 715 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 716 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 717 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 718 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 719 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 720 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 721 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 722 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 723 724 return req; 725 } 726 727 /** 728 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 729 * 730 * @adev: amdgpu_device pointer 731 * @vmhub: vmhub type 732 * 733 */ 734 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 735 uint32_t vmhub) 736 { 737 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 738 amdgpu_is_multi_aid(adev)) 739 return false; 740 741 return ((vmhub == AMDGPU_MMHUB0(0) || 742 vmhub == AMDGPU_MMHUB1(0)) && 743 (!amdgpu_sriov_vf(adev)) && 744 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 745 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 746 } 747 748 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 749 uint8_t vmid, uint16_t *p_pasid) 750 { 751 uint32_t value; 752 753 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 754 + vmid); 755 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 756 757 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 758 } 759 760 /* 761 * GART 762 * VMID 0 is the physical GPU addresses as used by the kernel. 763 * VMIDs 1-15 are used for userspace clients and are handled 764 * by the amdgpu vm/hsa code. 765 */ 766 767 /** 768 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 769 * 770 * @adev: amdgpu_device pointer 771 * @vmid: vm instance to flush 772 * @vmhub: which hub to flush 773 * @flush_type: the flush type 774 * 775 * Flush the TLB for the requested page table using certain type. 776 */ 777 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 778 uint32_t vmhub, uint32_t flush_type) 779 { 780 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 781 u32 j, inv_req, tmp, sem, req, ack, inst; 782 const unsigned int eng = 17; 783 struct amdgpu_vmhub *hub; 784 785 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 786 787 hub = &adev->vmhub[vmhub]; 788 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 789 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 790 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 791 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 792 793 if (vmhub >= AMDGPU_MMHUB0(0)) 794 inst = 0; 795 else 796 inst = vmhub; 797 798 /* This is necessary for SRIOV as well as for GFXOFF to function 799 * properly under bare metal 800 */ 801 if (adev->gfx.kiq[inst].ring.sched.ready && 802 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 803 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 804 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 805 806 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 807 1 << vmid, inst); 808 return; 809 } 810 811 /* This path is needed before KIQ/MES/GFXOFF are set up */ 812 spin_lock(&adev->gmc.invalidate_lock); 813 814 /* 815 * It may lose gpuvm invalidate acknowldege state across power-gating 816 * off cycle, add semaphore acquire before invalidation and semaphore 817 * release after invalidation to avoid entering power gated state 818 * to WA the Issue 819 */ 820 821 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 822 if (use_semaphore) { 823 for (j = 0; j < adev->usec_timeout; j++) { 824 /* a read return value of 1 means semaphore acquire */ 825 if (vmhub >= AMDGPU_MMHUB0(0)) 826 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst)); 827 else 828 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst)); 829 if (tmp & 0x1) 830 break; 831 udelay(1); 832 } 833 834 if (j >= adev->usec_timeout) 835 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 836 } 837 838 if (vmhub >= AMDGPU_MMHUB0(0)) 839 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst)); 840 else 841 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst)); 842 843 /* 844 * Issue a dummy read to wait for the ACK register to 845 * be cleared to avoid a false ACK due to the new fast 846 * GRBM interface. 847 */ 848 if ((vmhub == AMDGPU_GFXHUB(0)) && 849 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 850 RREG32_NO_KIQ(req); 851 852 for (j = 0; j < adev->usec_timeout; j++) { 853 if (vmhub >= AMDGPU_MMHUB0(0)) 854 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst)); 855 else 856 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst)); 857 if (tmp & (1 << vmid)) 858 break; 859 udelay(1); 860 } 861 862 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 863 if (use_semaphore) { 864 /* 865 * add semaphore release after invalidation, 866 * write with 0 means semaphore release 867 */ 868 if (vmhub >= AMDGPU_MMHUB0(0)) 869 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst)); 870 else 871 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst)); 872 } 873 874 spin_unlock(&adev->gmc.invalidate_lock); 875 876 if (j < adev->usec_timeout) 877 return; 878 879 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 880 } 881 882 /** 883 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 884 * 885 * @adev: amdgpu_device pointer 886 * @pasid: pasid to be flush 887 * @flush_type: the flush type 888 * @all_hub: flush all hubs 889 * @inst: is used to select which instance of KIQ to use for the invalidation 890 * 891 * Flush the TLB for the requested pasid. 892 */ 893 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 894 uint16_t pasid, uint32_t flush_type, 895 bool all_hub, uint32_t inst) 896 { 897 uint16_t queried; 898 int i, vmid; 899 900 for (vmid = 1; vmid < 16; vmid++) { 901 bool valid; 902 903 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 904 &queried); 905 if (!valid || queried != pasid) 906 continue; 907 908 if (all_hub) { 909 for_each_set_bit(i, adev->vmhubs_mask, 910 AMDGPU_MAX_VMHUBS) 911 gmc_v9_0_flush_gpu_tlb(adev, vmid, i, 912 flush_type); 913 } else { 914 gmc_v9_0_flush_gpu_tlb(adev, vmid, 915 AMDGPU_GFXHUB(0), 916 flush_type); 917 } 918 } 919 } 920 921 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 922 unsigned int vmid, uint64_t pd_addr) 923 { 924 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 925 struct amdgpu_device *adev = ring->adev; 926 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 927 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 928 unsigned int eng = ring->vm_inv_eng; 929 930 /* 931 * It may lose gpuvm invalidate acknowldege state across power-gating 932 * off cycle, add semaphore acquire before invalidation and semaphore 933 * release after invalidation to avoid entering power gated state 934 * to WA the Issue 935 */ 936 937 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 938 if (use_semaphore) 939 /* a read return value of 1 means semaphore acuqire */ 940 amdgpu_ring_emit_reg_wait(ring, 941 hub->vm_inv_eng0_sem + 942 hub->eng_distance * eng, 0x1, 0x1); 943 944 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 945 (hub->ctx_addr_distance * vmid), 946 lower_32_bits(pd_addr)); 947 948 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 949 (hub->ctx_addr_distance * vmid), 950 upper_32_bits(pd_addr)); 951 952 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 953 hub->eng_distance * eng, 954 hub->vm_inv_eng0_ack + 955 hub->eng_distance * eng, 956 req, 1 << vmid); 957 958 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 959 if (use_semaphore) 960 /* 961 * add semaphore release after invalidation, 962 * write with 0 means semaphore release 963 */ 964 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 965 hub->eng_distance * eng, 0); 966 967 return pd_addr; 968 } 969 970 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 971 unsigned int pasid) 972 { 973 struct amdgpu_device *adev = ring->adev; 974 uint32_t reg; 975 976 /* Do nothing because there's no lut register for mmhub1. */ 977 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 978 return; 979 980 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 981 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 982 else 983 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 984 985 amdgpu_ring_emit_wreg(ring, reg, pasid); 986 } 987 988 /* 989 * PTE format on VEGA 10: 990 * 63:59 reserved 991 * 58:57 mtype 992 * 56 F 993 * 55 L 994 * 54 P 995 * 53 SW 996 * 52 T 997 * 50:48 reserved 998 * 47:12 4k physical page base address 999 * 11:7 fragment 1000 * 6 write 1001 * 5 read 1002 * 4 exe 1003 * 3 Z 1004 * 2 snooped 1005 * 1 system 1006 * 0 valid 1007 * 1008 * PDE format on VEGA 10: 1009 * 63:59 block fragment size 1010 * 58:55 reserved 1011 * 54 P 1012 * 53:48 reserved 1013 * 47:6 physical base address of PD or PTE 1014 * 5:3 reserved 1015 * 2 C 1016 * 1 system 1017 * 0 valid 1018 */ 1019 1020 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1021 uint64_t *addr, uint64_t *flags) 1022 { 1023 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1024 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1025 BUG_ON(*addr & 0xFFFF00000000003FULL); 1026 1027 if (!adev->gmc.translate_further) 1028 return; 1029 1030 if (level == AMDGPU_VM_PDB1) { 1031 /* Set the block fragment size */ 1032 if (!(*flags & AMDGPU_PDE_PTE)) 1033 *flags |= AMDGPU_PDE_BFS(0x9); 1034 1035 } else if (level == AMDGPU_VM_PDB0) { 1036 if (*flags & AMDGPU_PDE_PTE) { 1037 *flags &= ~AMDGPU_PDE_PTE; 1038 if (!(*flags & AMDGPU_PTE_VALID)) 1039 *addr |= 1 << PAGE_SHIFT; 1040 } else { 1041 *flags |= AMDGPU_PTE_TF; 1042 } 1043 } 1044 } 1045 1046 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1047 struct amdgpu_vm *vm, 1048 struct amdgpu_bo *bo, 1049 uint32_t vm_flags, 1050 uint64_t *flags) 1051 { 1052 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1053 bool is_vram = bo->tbo.resource && 1054 bo->tbo.resource->mem_type == TTM_PL_VRAM; 1055 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 1056 AMDGPU_GEM_CREATE_EXT_COHERENT); 1057 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; 1058 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1059 unsigned int mtype_local, mtype; 1060 uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); 1061 bool snoop = false; 1062 bool is_local; 1063 1064 dma_resv_assert_held(bo->tbo.base.resv); 1065 1066 switch (gc_ip_version) { 1067 case IP_VERSION(9, 4, 1): 1068 case IP_VERSION(9, 4, 2): 1069 if (is_vram) { 1070 if (bo_adev == adev) { 1071 if (uncached) 1072 mtype = MTYPE_UC; 1073 else if (coherent) 1074 mtype = MTYPE_CC; 1075 else 1076 mtype = MTYPE_RW; 1077 /* FIXME: is this still needed? Or does 1078 * amdgpu_ttm_tt_pde_flags already handle this? 1079 */ 1080 if (gc_ip_version == IP_VERSION(9, 4, 2) && 1081 adev->gmc.xgmi.connected_to_cpu) 1082 snoop = true; 1083 } else { 1084 if (uncached || coherent) 1085 mtype = MTYPE_UC; 1086 else 1087 mtype = MTYPE_NC; 1088 if (amdgpu_xgmi_same_hive(adev, bo_adev)) 1089 snoop = true; 1090 } 1091 } else { 1092 if (uncached || coherent) 1093 mtype = MTYPE_UC; 1094 else 1095 mtype = MTYPE_NC; 1096 /* FIXME: is this still needed? Or does 1097 * amdgpu_ttm_tt_pde_flags already handle this? 1098 */ 1099 snoop = true; 1100 } 1101 break; 1102 case IP_VERSION(9, 4, 3): 1103 case IP_VERSION(9, 4, 4): 1104 case IP_VERSION(9, 5, 0): 1105 /* Only local VRAM BOs or system memory on non-NUMA APUs 1106 * can be assumed to be local in their entirety. Choose 1107 * MTYPE_NC as safe fallback for all system memory BOs on 1108 * NUMA systems. Their MTYPE can be overridden per-page in 1109 * gmc_v9_0_override_vm_pte_flags. 1110 */ 1111 mtype_local = MTYPE_RW; 1112 if (amdgpu_mtype_local == 1) { 1113 drm_info_once(adev_to_drm(adev), "Using MTYPE_NC for local memory\n"); 1114 mtype_local = MTYPE_NC; 1115 } else if (amdgpu_mtype_local == 2) { 1116 drm_info_once(adev_to_drm(adev), "Using MTYPE_CC for local memory\n"); 1117 mtype_local = MTYPE_CC; 1118 } else { 1119 drm_info_once(adev_to_drm(adev), "Using MTYPE_RW for local memory\n"); 1120 } 1121 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1122 num_possible_nodes() <= 1) || 1123 (is_vram && adev == bo_adev && 1124 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id); 1125 snoop = true; 1126 if (uncached) { 1127 mtype = MTYPE_UC; 1128 } else if (ext_coherent) { 1129 mtype = is_local ? MTYPE_CC : MTYPE_UC; 1130 } else if (adev->flags & AMD_IS_APU) { 1131 mtype = is_local ? mtype_local : MTYPE_NC; 1132 } else { 1133 /* dGPU */ 1134 if (is_local) 1135 mtype = mtype_local; 1136 else if (gc_ip_version < IP_VERSION(9, 5, 0) && !is_vram) 1137 mtype = MTYPE_UC; 1138 else 1139 mtype = MTYPE_NC; 1140 } 1141 1142 break; 1143 default: 1144 if (uncached || coherent) 1145 mtype = MTYPE_UC; 1146 else 1147 mtype = MTYPE_NC; 1148 1149 /* FIXME: is this still needed? Or does 1150 * amdgpu_ttm_tt_pde_flags already handle this? 1151 */ 1152 if (!is_vram) 1153 snoop = true; 1154 } 1155 1156 if (mtype != MTYPE_NC) 1157 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype); 1158 1159 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1160 } 1161 1162 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1163 struct amdgpu_vm *vm, 1164 struct amdgpu_bo *bo, 1165 uint32_t vm_flags, 1166 uint64_t *flags) 1167 { 1168 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) 1169 *flags |= AMDGPU_PTE_EXECUTABLE; 1170 else 1171 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1172 1173 switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { 1174 case AMDGPU_VM_MTYPE_DEFAULT: 1175 case AMDGPU_VM_MTYPE_NC: 1176 default: 1177 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_NC); 1178 break; 1179 case AMDGPU_VM_MTYPE_WC: 1180 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_WC); 1181 break; 1182 case AMDGPU_VM_MTYPE_RW: 1183 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_RW); 1184 break; 1185 case AMDGPU_VM_MTYPE_CC: 1186 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC); 1187 break; 1188 case AMDGPU_VM_MTYPE_UC: 1189 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_UC); 1190 break; 1191 } 1192 1193 if (vm_flags & AMDGPU_VM_PAGE_PRT) { 1194 *flags |= AMDGPU_PTE_PRT; 1195 *flags &= ~AMDGPU_PTE_VALID; 1196 } 1197 1198 if ((*flags & AMDGPU_PTE_VALID) && bo) 1199 gmc_v9_0_get_coherence_flags(adev, vm, bo, vm_flags, flags); 1200 } 1201 1202 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1203 struct amdgpu_vm *vm, 1204 uint64_t addr, uint64_t *flags) 1205 { 1206 int local_node, nid; 1207 1208 /* MTYPE_NC is the same default and can be overridden. 1209 * MTYPE_UC will be present if the memory is extended-coherent 1210 * and can also be overridden. 1211 */ 1212 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1213 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC) && 1214 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1215 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC)) { 1216 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n"); 1217 return; 1218 } 1219 1220 if (vm->mem_id >= 0) { 1221 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1222 } else { 1223 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n"); 1224 return; 1225 } 1226 1227 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1228 * page or NUMA nodes. 1229 */ 1230 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1231 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n"); 1232 return; 1233 } 1234 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1235 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1236 vm->mem_id, local_node, nid); 1237 if (nid == local_node) { 1238 uint64_t old_flags = *flags; 1239 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) == 1240 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC)) { 1241 unsigned int mtype_local = MTYPE_RW; 1242 1243 if (amdgpu_mtype_local == 1) 1244 mtype_local = MTYPE_NC; 1245 else if (amdgpu_mtype_local == 2) 1246 mtype_local = MTYPE_CC; 1247 1248 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype_local); 1249 } else { 1250 /* MTYPE_UC case */ 1251 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC); 1252 } 1253 1254 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n", 1255 old_flags, *flags); 1256 } 1257 } 1258 1259 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1260 { 1261 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1262 unsigned int size; 1263 1264 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1265 1266 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1267 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1268 } else { 1269 u32 viewport; 1270 1271 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1272 case IP_VERSION(1, 0, 0): 1273 case IP_VERSION(1, 0, 1): 1274 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1275 size = (REG_GET_FIELD(viewport, 1276 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1277 REG_GET_FIELD(viewport, 1278 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1279 4); 1280 break; 1281 case IP_VERSION(2, 1, 0): 1282 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1283 size = (REG_GET_FIELD(viewport, 1284 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1285 REG_GET_FIELD(viewport, 1286 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1287 4); 1288 break; 1289 default: 1290 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1291 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1292 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1293 4); 1294 break; 1295 } 1296 } 1297 1298 return size; 1299 } 1300 1301 static bool gmc_v9_0_need_reset_on_init(struct amdgpu_device *adev) 1302 { 1303 if (adev->nbio.funcs && adev->nbio.funcs->is_nps_switch_requested && 1304 adev->nbio.funcs->is_nps_switch_requested(adev)) { 1305 adev->gmc.reset_flags |= AMDGPU_GMC_INIT_RESET_NPS; 1306 return true; 1307 } 1308 1309 return false; 1310 } 1311 1312 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1313 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1314 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1315 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1316 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1317 .get_vm_pde = gmc_v9_0_get_vm_pde, 1318 .get_vm_pte = gmc_v9_0_get_vm_pte, 1319 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1320 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1321 .query_mem_partition_mode = &amdgpu_gmc_query_memory_partition, 1322 .request_mem_partition_mode = &amdgpu_gmc_request_memory_partition, 1323 .need_reset_on_init = &gmc_v9_0_need_reset_on_init, 1324 }; 1325 1326 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1327 { 1328 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1329 1330 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes, local system 1331 * memory can use more efficient MTYPEs. 1332 * 1333 * APUs mapping system memory may need different MTYPEs on different 1334 * NUMA nodes. 1335 * 1336 * Only direct-mapped memory allows us to determine the NUMA node from 1337 * the DMA address. 1338 */ 1339 adev->gmc.override_pte = adev->gmc.is_app_apu && 1340 num_possible_nodes() > 1 && 1341 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 1342 adev->ram_is_direct_mapped; 1343 } 1344 1345 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1346 { 1347 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1348 case IP_VERSION(6, 0, 0): 1349 adev->umc.funcs = &umc_v6_0_funcs; 1350 break; 1351 case IP_VERSION(6, 1, 1): 1352 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1353 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1354 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1355 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1356 adev->umc.retire_unit = 1; 1357 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1358 adev->umc.ras = &umc_v6_1_ras; 1359 break; 1360 case IP_VERSION(6, 1, 2): 1361 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1362 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1363 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1364 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1365 adev->umc.retire_unit = 1; 1366 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1367 adev->umc.ras = &umc_v6_1_ras; 1368 break; 1369 case IP_VERSION(6, 7, 0): 1370 adev->umc.max_ras_err_cnt_per_query = 1371 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1372 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1373 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1374 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1375 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1376 if (!adev->gmc.xgmi.connected_to_cpu) 1377 adev->umc.ras = &umc_v6_7_ras; 1378 if (1 & adev->smuio.funcs->get_die_id(adev)) 1379 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1380 else 1381 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1382 break; 1383 case IP_VERSION(12, 0, 0): 1384 case IP_VERSION(12, 5, 0): 1385 adev->umc.max_ras_err_cnt_per_query = 1386 UMC_V12_0_TOTAL_CHANNEL_NUM * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1387 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM; 1388 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM; 1389 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM; 1390 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET; 1391 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1392 adev->umc.ras = &umc_v12_0_ras; 1393 break; 1394 default: 1395 break; 1396 } 1397 } 1398 1399 static void gmc_v9_0_init_mmhub_client_info(struct amdgpu_device *adev) 1400 { 1401 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1402 case IP_VERSION(9, 0, 0): 1403 amdgpu_mmhub_init_client_info(&adev->mmhub, 1404 mmhub_client_ids_vega10, 1405 ARRAY_SIZE(mmhub_client_ids_vega10)); 1406 break; 1407 case IP_VERSION(9, 3, 0): 1408 amdgpu_mmhub_init_client_info(&adev->mmhub, 1409 mmhub_client_ids_vega12, 1410 ARRAY_SIZE(mmhub_client_ids_vega12)); 1411 break; 1412 case IP_VERSION(9, 4, 0): 1413 amdgpu_mmhub_init_client_info(&adev->mmhub, 1414 mmhub_client_ids_vega20, 1415 ARRAY_SIZE(mmhub_client_ids_vega20)); 1416 break; 1417 case IP_VERSION(9, 4, 1): 1418 amdgpu_mmhub_init_client_info(&adev->mmhub, 1419 mmhub_client_ids_arcturus, 1420 ARRAY_SIZE(mmhub_client_ids_arcturus)); 1421 break; 1422 case IP_VERSION(9, 1, 0): 1423 case IP_VERSION(9, 2, 0): 1424 amdgpu_mmhub_init_client_info(&adev->mmhub, 1425 mmhub_client_ids_raven, 1426 ARRAY_SIZE(mmhub_client_ids_raven)); 1427 break; 1428 case IP_VERSION(1, 5, 0): 1429 case IP_VERSION(2, 4, 0): 1430 amdgpu_mmhub_init_client_info(&adev->mmhub, 1431 mmhub_client_ids_renoir, 1432 ARRAY_SIZE(mmhub_client_ids_renoir)); 1433 break; 1434 case IP_VERSION(1, 8, 0): 1435 case IP_VERSION(9, 4, 2): 1436 amdgpu_mmhub_init_client_info(&adev->mmhub, 1437 mmhub_client_ids_aldebaran, 1438 ARRAY_SIZE(mmhub_client_ids_aldebaran)); 1439 break; 1440 default: 1441 break; 1442 } 1443 } 1444 1445 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1446 { 1447 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1448 case IP_VERSION(9, 4, 1): 1449 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1450 break; 1451 case IP_VERSION(9, 4, 2): 1452 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1453 break; 1454 case IP_VERSION(1, 8, 0): 1455 case IP_VERSION(1, 8, 1): 1456 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1457 break; 1458 default: 1459 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1460 break; 1461 } 1462 1463 gmc_v9_0_init_mmhub_client_info(adev); 1464 } 1465 1466 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1467 { 1468 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1469 case IP_VERSION(9, 4, 0): 1470 adev->mmhub.ras = &mmhub_v1_0_ras; 1471 break; 1472 case IP_VERSION(9, 4, 1): 1473 adev->mmhub.ras = &mmhub_v9_4_ras; 1474 break; 1475 case IP_VERSION(9, 4, 2): 1476 adev->mmhub.ras = &mmhub_v1_7_ras; 1477 break; 1478 case IP_VERSION(1, 8, 0): 1479 case IP_VERSION(1, 8, 1): 1480 adev->mmhub.ras = &mmhub_v1_8_ras; 1481 break; 1482 default: 1483 /* mmhub ras is not available */ 1484 break; 1485 } 1486 } 1487 1488 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1489 { 1490 if (amdgpu_is_multi_aid(adev)) 1491 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1492 else 1493 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1494 } 1495 1496 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1497 { 1498 adev->hdp.ras = &hdp_v4_0_ras; 1499 } 1500 1501 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1502 { 1503 struct amdgpu_mca *mca = &adev->mca; 1504 1505 /* is UMC the right IP to check for MCA? Maybe DF? */ 1506 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1507 case IP_VERSION(6, 7, 0): 1508 if (!adev->gmc.xgmi.connected_to_cpu) { 1509 mca->mp0.ras = &mca_v3_0_mp0_ras; 1510 mca->mp1.ras = &mca_v3_0_mp1_ras; 1511 mca->mpio.ras = &mca_v3_0_mpio_ras; 1512 } 1513 break; 1514 default: 1515 break; 1516 } 1517 } 1518 1519 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1520 { 1521 if (!adev->gmc.xgmi.connected_to_cpu) 1522 adev->gmc.xgmi.ras = &xgmi_ras; 1523 } 1524 1525 static void gmc_v9_0_init_nps_details(struct amdgpu_device *adev) 1526 { 1527 enum amdgpu_memory_partition mode; 1528 uint32_t supp_modes; 1529 int i; 1530 1531 adev->gmc.supported_nps_modes = 0; 1532 1533 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 1534 return; 1535 1536 mode = amdgpu_gmc_get_memory_partition(adev, &supp_modes); 1537 1538 /* Mode detected by hardware and supported modes available */ 1539 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && supp_modes) { 1540 while ((i = ffs(supp_modes))) { 1541 if (AMDGPU_ALL_NPS_MASK & BIT(i)) 1542 adev->gmc.supported_nps_modes |= BIT(i); 1543 supp_modes &= supp_modes - 1; 1544 } 1545 } else { 1546 /*TODO: Check PSP version also which supports NPS switch. Otherwise keep 1547 * supported modes as 0. 1548 */ 1549 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1550 case IP_VERSION(9, 4, 3): 1551 case IP_VERSION(9, 4, 4): 1552 adev->gmc.supported_nps_modes = 1553 BIT(AMDGPU_NPS1_PARTITION_MODE) | 1554 BIT(AMDGPU_NPS4_PARTITION_MODE); 1555 break; 1556 default: 1557 break; 1558 } 1559 } 1560 } 1561 1562 static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block) 1563 { 1564 struct amdgpu_device *adev = ip_block->adev; 1565 1566 /* 1567 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1568 * in their IP discovery tables 1569 */ 1570 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) || 1571 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 1572 amdgpu_is_multi_aid(adev)) 1573 adev->gmc.xgmi.supported = true; 1574 1575 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) { 1576 adev->gmc.xgmi.supported = true; 1577 adev->gmc.xgmi.connected_to_cpu = 1578 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1579 } 1580 1581 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 1582 enum amdgpu_pkg_type pkg_type = 1583 adev->smuio.funcs->get_pkg_type(adev); 1584 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1585 * and the APU, can be in used two possible modes: 1586 * - carveout mode 1587 * - native APU mode 1588 * "is_app_apu" can be used to identify the APU in the native 1589 * mode. 1590 */ 1591 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1592 !pci_resource_len(adev->pdev, 0)); 1593 } 1594 1595 gmc_v9_0_set_gmc_funcs(adev); 1596 gmc_v9_0_set_irq_funcs(adev); 1597 gmc_v9_0_set_umc_funcs(adev); 1598 gmc_v9_0_set_mmhub_funcs(adev); 1599 gmc_v9_0_set_mmhub_ras_funcs(adev); 1600 gmc_v9_0_set_gfxhub_funcs(adev); 1601 gmc_v9_0_set_hdp_ras_funcs(adev); 1602 gmc_v9_0_set_mca_ras_funcs(adev); 1603 gmc_v9_0_set_xgmi_ras_funcs(adev); 1604 1605 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1606 adev->gmc.shared_aperture_end = 1607 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1608 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1609 adev->gmc.private_aperture_end = 1610 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1611 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1612 1613 return 0; 1614 } 1615 1616 static int gmc_v9_0_late_init(struct amdgpu_ip_block *ip_block) 1617 { 1618 struct amdgpu_device *adev = ip_block->adev; 1619 int r; 1620 1621 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1622 if (r) 1623 return r; 1624 1625 /* 1626 * Workaround performance drop issue with VBIOS enables partial 1627 * writes, while disables HBM ECC for vega10. 1628 */ 1629 if (!amdgpu_sriov_vf(adev) && 1630 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) { 1631 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1632 if (adev->df.funcs && 1633 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1634 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1635 } 1636 } 1637 1638 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1639 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB); 1640 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP); 1641 } 1642 1643 r = amdgpu_gmc_ras_late_init(adev); 1644 if (r) 1645 return r; 1646 1647 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1648 } 1649 1650 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1651 struct amdgpu_gmc *mc) 1652 { 1653 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1654 1655 amdgpu_gmc_set_agp_default(adev, mc); 1656 1657 /* add the xgmi offset of the physical node */ 1658 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1659 if (amdgpu_gmc_is_pdb0_enabled(adev)) { 1660 amdgpu_gmc_sysvm_location(adev, mc); 1661 } else { 1662 amdgpu_gmc_vram_location(adev, mc, base); 1663 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 1664 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 1665 amdgpu_gmc_agp_location(adev, mc); 1666 } 1667 /* base offset of vram pages */ 1668 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1669 1670 /* XXX: add the xgmi offset of the physical node? */ 1671 adev->vm_manager.vram_base_offset += 1672 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1673 } 1674 1675 /** 1676 * gmc_v9_0_mc_init - initialize the memory controller driver params 1677 * 1678 * @adev: amdgpu_device pointer 1679 * 1680 * Look up the amount of vram, vram width, and decide how to place 1681 * vram and gart within the GPU's physical address space. 1682 * Returns 0 for success. 1683 */ 1684 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1685 { 1686 int r; 1687 1688 /* size in MB on si */ 1689 if (!adev->gmc.is_app_apu) { 1690 adev->gmc.mc_vram_size = 1691 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1692 } else { 1693 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1694 adev->gmc.mc_vram_size = 0; 1695 } 1696 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1697 1698 if (!(adev->flags & AMD_IS_APU) && 1699 !adev->gmc.xgmi.connected_to_cpu) { 1700 r = amdgpu_device_resize_fb_bar(adev); 1701 if (r) 1702 return r; 1703 } 1704 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1705 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1706 1707 #ifdef CONFIG_X86_64 1708 /* 1709 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1710 * interface can use VRAM through here as it appears system reserved 1711 * memory in host address space. 1712 * 1713 * For APUs, VRAM is just the stolen system memory and can be accessed 1714 * directly. 1715 * 1716 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1717 */ 1718 1719 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1720 if ((!amdgpu_sriov_vf(adev) && 1721 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1722 (adev->gmc.xgmi.supported && 1723 adev->gmc.xgmi.connected_to_cpu)) { 1724 adev->gmc.aper_base = 1725 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1726 adev->gmc.xgmi.physical_node_id * 1727 adev->gmc.xgmi.node_segment_size; 1728 adev->gmc.aper_size = adev->gmc.real_vram_size; 1729 } 1730 1731 #endif 1732 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1733 1734 /* set the gart size */ 1735 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1736 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1737 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1738 case IP_VERSION(9, 3, 0): 1739 amdgpu_gmc_set_gart_size(adev, SZ_1G); 1740 break; 1741 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1742 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1743 case IP_VERSION(9, 4, 0): 1744 case IP_VERSION(9, 4, 1): 1745 case IP_VERSION(9, 4, 2): 1746 case IP_VERSION(9, 4, 3): 1747 case IP_VERSION(9, 4, 4): 1748 case IP_VERSION(9, 5, 0): 1749 default: 1750 amdgpu_gmc_set_gart_size(adev, SZ_512M); 1751 break; 1752 } 1753 1754 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1755 1756 return 0; 1757 } 1758 1759 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1760 { 1761 int r; 1762 1763 if (adev->gart.bo) { 1764 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1765 return 0; 1766 } 1767 1768 if (amdgpu_gmc_is_pdb0_enabled(adev)) { 1769 adev->gmc.vmid0_page_table_depth = 1; 1770 adev->gmc.vmid0_page_table_block_size = 12; 1771 } else { 1772 adev->gmc.vmid0_page_table_depth = 0; 1773 adev->gmc.vmid0_page_table_block_size = 0; 1774 } 1775 1776 /* Initialize common gart structure */ 1777 r = amdgpu_gart_init(adev); 1778 if (r) 1779 return r; 1780 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1781 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC) | 1782 AMDGPU_PTE_EXECUTABLE; 1783 1784 if (!adev->gmc.real_vram_size) { 1785 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1786 r = amdgpu_gart_table_ram_alloc(adev); 1787 if (r) 1788 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1789 } else { 1790 r = amdgpu_gart_table_vram_alloc(adev); 1791 if (r) 1792 return r; 1793 1794 if (amdgpu_gmc_is_pdb0_enabled(adev)) 1795 r = amdgpu_gmc_pdb0_alloc(adev); 1796 } 1797 1798 return r; 1799 } 1800 1801 /** 1802 * gmc_v9_0_save_registers - saves regs 1803 * 1804 * @adev: amdgpu_device pointer 1805 * 1806 * This saves potential register values that should be 1807 * restored upon resume 1808 */ 1809 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1810 { 1811 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1812 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) 1813 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1814 } 1815 1816 static void gmc_v9_0_init_vram_info(struct amdgpu_device *adev) 1817 { 1818 static const u32 regBIF_BIOS_SCRATCH_4 = 0x50; 1819 int dev_var = adev->pdev->device & 0xF; 1820 u32 vram_info; 1821 1822 if (adev->gmc.is_app_apu) { 1823 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1824 adev->gmc.vram_width = 128 * 64; 1825 } else if (adev->flags & AMD_IS_APU) { 1826 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 1827 adev->gmc.vram_width = 64 * 64; 1828 } else if (amdgpu_is_multi_aid(adev)) { 1829 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1830 adev->gmc.vram_width = 128 * 64; 1831 1832 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 1833 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; 1834 1835 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) && 1836 adev->rev_id == 0x3) 1837 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; 1838 1839 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 1840 (dev_var == 0x5)) 1841 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; 1842 1843 if (!(adev->flags & AMD_IS_APU) && !amdgpu_sriov_vf(adev)) { 1844 vram_info = RREG32(regBIF_BIOS_SCRATCH_4); 1845 adev->gmc.vram_vendor = vram_info & 0xF; 1846 } 1847 } 1848 } 1849 1850 static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) 1851 { 1852 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 1853 struct amdgpu_device *adev = ip_block->adev; 1854 unsigned long inst_mask = adev->aid_mask; 1855 1856 adev->gfxhub.funcs->init(adev); 1857 1858 adev->mmhub.funcs->init(adev); 1859 1860 spin_lock_init(&adev->gmc.invalidate_lock); 1861 1862 if (!adev->bios) { 1863 gmc_v9_0_init_vram_info(adev); 1864 } else { 1865 r = amdgpu_gmc_get_vram_info(adev, 1866 &vram_width, &vram_type, &vram_vendor); 1867 if (amdgpu_sriov_vf(adev)) 1868 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 1869 * and DF related registers is not readable, seems hardcord is the 1870 * only way to set the correct vram_width 1871 */ 1872 adev->gmc.vram_width = 2048; 1873 else if (amdgpu_emu_mode != 1) 1874 adev->gmc.vram_width = vram_width; 1875 1876 if (!adev->gmc.vram_width) { 1877 int chansize, numchan; 1878 1879 /* hbm memory channel size */ 1880 if (adev->flags & AMD_IS_APU) 1881 chansize = 64; 1882 else 1883 chansize = 128; 1884 if (adev->df.funcs && 1885 adev->df.funcs->get_hbm_channel_number) { 1886 numchan = adev->df.funcs->get_hbm_channel_number(adev); 1887 adev->gmc.vram_width = numchan * chansize; 1888 } 1889 } 1890 1891 adev->gmc.vram_type = vram_type; 1892 adev->gmc.vram_vendor = vram_vendor; 1893 } 1894 1895 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1896 case IP_VERSION(9, 1, 0): 1897 case IP_VERSION(9, 2, 2): 1898 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1899 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1900 1901 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 1902 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1903 } else { 1904 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 1905 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 1906 adev->gmc.translate_further = 1907 adev->vm_manager.num_level > 1; 1908 } 1909 break; 1910 case IP_VERSION(9, 0, 1): 1911 case IP_VERSION(9, 2, 1): 1912 case IP_VERSION(9, 4, 0): 1913 case IP_VERSION(9, 3, 0): 1914 case IP_VERSION(9, 4, 2): 1915 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1916 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1917 1918 /* 1919 * To fulfill 4-level page support, 1920 * vm size is 256TB (48bit), maximum size of Vega10, 1921 * block size 512 (9bit) 1922 */ 1923 1924 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1925 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 1926 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1927 break; 1928 case IP_VERSION(9, 4, 1): 1929 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1930 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 1931 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 1932 1933 /* Keep the vm size same with Vega20 */ 1934 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1935 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1936 break; 1937 case IP_VERSION(9, 4, 3): 1938 case IP_VERSION(9, 4, 4): 1939 case IP_VERSION(9, 5, 0): 1940 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 1941 NUM_XCC(adev->gfx.xcc_mask)); 1942 1943 inst_mask <<= AMDGPU_MMHUB0(0); 1944 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 1945 1946 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 1947 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 1948 break; 1949 default: 1950 break; 1951 } 1952 1953 /* This interrupt is VMC page fault.*/ 1954 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 1955 &adev->gmc.vm_fault); 1956 if (r) 1957 return r; 1958 1959 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) { 1960 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 1961 &adev->gmc.vm_fault); 1962 if (r) 1963 return r; 1964 } 1965 1966 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 1967 &adev->gmc.vm_fault); 1968 1969 if (r) 1970 return r; 1971 1972 if (!amdgpu_sriov_vf(adev) && 1973 !adev->gmc.xgmi.connected_to_cpu && 1974 !adev->gmc.is_app_apu) { 1975 /* interrupt sent to DF. */ 1976 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 1977 &adev->gmc.ecc_irq); 1978 if (r) 1979 return r; 1980 } 1981 1982 /* Set the internal MC address mask 1983 * This is the max address of the GPU's 1984 * internal address space. 1985 */ 1986 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 1987 adev->gmc.pte_addr_mask = 0x0000FFFFFFFFF000ULL; /* 48 bit PA */ 1988 1989 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= 1990 IP_VERSION(9, 4, 2) ? 1991 48 : 1992 44; 1993 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 1994 if (r) { 1995 drm_warn(adev_to_drm(adev), "No suitable DMA available.\n"); 1996 return r; 1997 } 1998 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 1999 2000 r = gmc_v9_0_mc_init(adev); 2001 if (r) 2002 return r; 2003 2004 if (amdgpu_is_multi_aid(adev)) { 2005 r = amdgpu_gmc_init_mem_ranges(adev); 2006 if (r) 2007 return r; 2008 } 2009 2010 /* Memory manager */ 2011 r = amdgpu_bo_init(adev); 2012 if (r) 2013 return r; 2014 2015 r = gmc_v9_0_gart_init(adev); 2016 if (r) 2017 return r; 2018 2019 gmc_v9_0_init_nps_details(adev); 2020 /* 2021 * number of VMs 2022 * VMID 0 is reserved for System 2023 * amdgpu graphics/compute will use VMIDs 1..n-1 2024 * amdkfd will use VMIDs n..15 2025 * 2026 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2027 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2028 * for video processing. 2029 * 2030 * If kernel queues are disabled, allow KFD to use all vmids. 2031 */ 2032 if (adev->gfx.disable_kq && 2033 adev->jpeg.disable_kq && 2034 adev->vcn.disable_kq && 2035 adev->sdma.no_user_submission) 2036 adev->vm_manager.first_kfd_vmid = 1; 2037 else 2038 adev->vm_manager.first_kfd_vmid = 2039 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 2040 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 2041 amdgpu_is_multi_aid(adev)) ? 2042 3 : 2043 8; 2044 2045 amdgpu_vm_manager_init(adev); 2046 2047 gmc_v9_0_save_registers(adev); 2048 2049 r = amdgpu_gmc_ras_sw_init(adev); 2050 if (r) 2051 return r; 2052 2053 if (amdgpu_is_multi_aid(adev)) 2054 amdgpu_gmc_sysfs_init(adev); 2055 2056 return 0; 2057 } 2058 2059 static int gmc_v9_0_sw_fini(struct amdgpu_ip_block *ip_block) 2060 { 2061 struct amdgpu_device *adev = ip_block->adev; 2062 2063 if (amdgpu_is_multi_aid(adev)) 2064 amdgpu_gmc_sysfs_fini(adev); 2065 2066 amdgpu_gmc_ras_fini(adev); 2067 amdgpu_gem_force_release(adev); 2068 amdgpu_vm_manager_fini(adev); 2069 if (!adev->gmc.real_vram_size) { 2070 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2071 amdgpu_gart_table_ram_free(adev); 2072 } else { 2073 amdgpu_gart_table_vram_free(adev); 2074 } 2075 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2076 amdgpu_bo_fini(adev); 2077 2078 adev->gmc.num_mem_partitions = 0; 2079 kfree(adev->gmc.mem_partitions); 2080 2081 return 0; 2082 } 2083 2084 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2085 { 2086 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 2087 case IP_VERSION(9, 0, 0): 2088 if (amdgpu_sriov_vf(adev)) 2089 break; 2090 fallthrough; 2091 case IP_VERSION(9, 4, 0): 2092 soc15_program_register_sequence(adev, 2093 golden_settings_mmhub_1_0_0, 2094 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2095 soc15_program_register_sequence(adev, 2096 golden_settings_athub_1_0_0, 2097 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2098 break; 2099 case IP_VERSION(9, 1, 0): 2100 case IP_VERSION(9, 2, 0): 2101 /* TODO for renoir */ 2102 soc15_program_register_sequence(adev, 2103 golden_settings_athub_1_0_0, 2104 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2105 break; 2106 default: 2107 break; 2108 } 2109 } 2110 2111 /** 2112 * gmc_v9_0_restore_registers - restores regs 2113 * 2114 * @adev: amdgpu_device pointer 2115 * 2116 * This restores register values, saved at suspend. 2117 */ 2118 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2119 { 2120 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 2121 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) { 2122 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2123 WARN_ON(adev->gmc.sdpif_register != 2124 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2125 } 2126 } 2127 2128 /** 2129 * gmc_v9_0_gart_enable - gart enable 2130 * 2131 * @adev: amdgpu_device pointer 2132 */ 2133 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2134 { 2135 int r; 2136 2137 if (amdgpu_gmc_is_pdb0_enabled(adev)) 2138 amdgpu_gmc_init_pdb0(adev); 2139 2140 if (adev->gart.bo == NULL) { 2141 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2142 return -EINVAL; 2143 } 2144 2145 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2146 2147 if (!adev->in_s0ix) { 2148 r = adev->gfxhub.funcs->gart_enable(adev); 2149 if (r) 2150 return r; 2151 } 2152 2153 r = adev->mmhub.funcs->gart_enable(adev); 2154 if (r) 2155 return r; 2156 2157 drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled.\n", 2158 (unsigned int)(adev->gmc.gart_size >> 20)); 2159 if (adev->gmc.pdb0_bo) 2160 drm_info(adev_to_drm(adev), "PDB0 located at 0x%016llX\n", 2161 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2162 drm_info(adev_to_drm(adev), "PTB located at 0x%016llX\n", 2163 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2164 2165 return 0; 2166 } 2167 2168 static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block) 2169 { 2170 struct amdgpu_device *adev = ip_block->adev; 2171 bool value; 2172 int i, r; 2173 2174 adev->gmc.flush_pasid_uses_kiq = true; 2175 2176 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush 2177 * (type 2), which flushes both. Due to a race condition with 2178 * concurrent memory accesses using the same TLB cache line, we still 2179 * need a second TLB flush after this. 2180 */ 2181 adev->gmc.flush_tlb_needs_extra_type_2 = 2182 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) && 2183 adev->gmc.xgmi.num_physical_nodes; 2184 2185 /* The sequence of these two function calls matters.*/ 2186 gmc_v9_0_init_golden_registers(adev); 2187 2188 if (adev->mode_info.num_crtc) { 2189 /* Lockout access through VGA aperture*/ 2190 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2191 /* disable VGA render */ 2192 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2193 } 2194 2195 if (adev->mmhub.funcs->update_power_gating) 2196 adev->mmhub.funcs->update_power_gating(adev, true); 2197 2198 adev->hdp.funcs->init_registers(adev); 2199 2200 /* After HDP is initialized, flush HDP.*/ 2201 amdgpu_device_flush_hdp(adev, NULL); 2202 2203 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2204 value = false; 2205 else 2206 value = true; 2207 2208 if (!amdgpu_sriov_vf(adev)) { 2209 if (!adev->in_s0ix) 2210 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2211 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2212 } 2213 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2214 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2215 continue; 2216 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2217 } 2218 2219 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2220 adev->umc.funcs->init_registers(adev); 2221 2222 r = gmc_v9_0_gart_enable(adev); 2223 if (r) 2224 return r; 2225 2226 if (amdgpu_emu_mode == 1) 2227 return amdgpu_gmc_vram_checking(adev); 2228 2229 return 0; 2230 } 2231 2232 /** 2233 * gmc_v9_0_gart_disable - gart disable 2234 * 2235 * @adev: amdgpu_device pointer 2236 * 2237 * This disables all VM page table. 2238 */ 2239 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2240 { 2241 if (!adev->in_s0ix) 2242 adev->gfxhub.funcs->gart_disable(adev); 2243 adev->mmhub.funcs->gart_disable(adev); 2244 } 2245 2246 static int gmc_v9_0_hw_fini(struct amdgpu_ip_block *ip_block) 2247 { 2248 struct amdgpu_device *adev = ip_block->adev; 2249 2250 gmc_v9_0_gart_disable(adev); 2251 2252 if (amdgpu_sriov_vf(adev)) { 2253 /* full access mode, so don't touch any GMC register */ 2254 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2255 return 0; 2256 } 2257 2258 /* 2259 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2260 * a correct cached state for GMC. Otherwise, the "gate" again 2261 * operation on S3 resuming will fail due to wrong cached state. 2262 */ 2263 if (adev->mmhub.funcs->update_power_gating) 2264 adev->mmhub.funcs->update_power_gating(adev, false); 2265 2266 /* 2267 * For minimal init, late_init is not called, hence VM fault/RAS irqs 2268 * are not enabled. 2269 */ 2270 if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { 2271 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2272 2273 if (adev->gmc.ecc_irq.funcs && 2274 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2275 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 2276 } 2277 2278 return 0; 2279 } 2280 2281 static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block) 2282 { 2283 return gmc_v9_0_hw_fini(ip_block); 2284 } 2285 2286 static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block) 2287 { 2288 struct amdgpu_device *adev = ip_block->adev; 2289 int r; 2290 2291 /* If a reset is done for NPS mode switch, read the memory range 2292 * information again. 2293 */ 2294 if (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS) { 2295 amdgpu_gmc_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 2296 adev->gmc.reset_flags &= ~AMDGPU_GMC_INIT_RESET_NPS; 2297 } 2298 2299 r = gmc_v9_0_hw_init(ip_block); 2300 if (r) 2301 return r; 2302 2303 amdgpu_vmid_reset_all(ip_block->adev); 2304 2305 return 0; 2306 } 2307 2308 static bool gmc_v9_0_is_idle(struct amdgpu_ip_block *ip_block) 2309 { 2310 /* MC is always ready in GMC v9.*/ 2311 return true; 2312 } 2313 2314 static int gmc_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 2315 { 2316 /* There is no need to wait for MC idle in GMC v9.*/ 2317 return 0; 2318 } 2319 2320 static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block) 2321 { 2322 /* XXX for emulation.*/ 2323 return 0; 2324 } 2325 2326 static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2327 enum amd_clockgating_state state) 2328 { 2329 struct amdgpu_device *adev = ip_block->adev; 2330 2331 adev->mmhub.funcs->set_clockgating(adev, state); 2332 2333 athub_v1_0_set_clockgating(adev, state); 2334 2335 return 0; 2336 } 2337 2338 static void gmc_v9_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2339 { 2340 struct amdgpu_device *adev = ip_block->adev; 2341 2342 adev->mmhub.funcs->get_clockgating(adev, flags); 2343 2344 athub_v1_0_get_clockgating(adev, flags); 2345 } 2346 2347 static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 2348 enum amd_powergating_state state) 2349 { 2350 return 0; 2351 } 2352 2353 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2354 .name = "gmc_v9_0", 2355 .early_init = gmc_v9_0_early_init, 2356 .late_init = gmc_v9_0_late_init, 2357 .sw_init = gmc_v9_0_sw_init, 2358 .sw_fini = gmc_v9_0_sw_fini, 2359 .hw_init = gmc_v9_0_hw_init, 2360 .hw_fini = gmc_v9_0_hw_fini, 2361 .suspend = gmc_v9_0_suspend, 2362 .resume = gmc_v9_0_resume, 2363 .is_idle = gmc_v9_0_is_idle, 2364 .wait_for_idle = gmc_v9_0_wait_for_idle, 2365 .soft_reset = gmc_v9_0_soft_reset, 2366 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2367 .set_powergating_state = gmc_v9_0_set_powergating_state, 2368 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2369 }; 2370 2371 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = { 2372 .type = AMD_IP_BLOCK_TYPE_GMC, 2373 .major = 9, 2374 .minor = 0, 2375 .rev = 0, 2376 .funcs = &gmc_v9_0_ip_funcs, 2377 }; 2378