1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "amdgpu.h" 25 #include "gmc_v9_0.h" 26 27 #include "vega10/soc15ip.h" 28 #include "vega10/HDP/hdp_4_0_offset.h" 29 #include "vega10/HDP/hdp_4_0_sh_mask.h" 30 #include "vega10/GC/gc_9_0_sh_mask.h" 31 #include "vega10/vega10_enum.h" 32 33 #include "soc15_common.h" 34 35 #include "nbio_v6_1.h" 36 #include "gfxhub_v1_0.h" 37 #include "mmhub_v1_0.h" 38 39 #define mmDF_CS_AON0_DramBaseAddress0 0x0044 40 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0 41 //DF_CS_AON0_DramBaseAddress0 42 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 43 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 44 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4 45 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8 46 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc 47 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L 48 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L 49 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L 50 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L 51 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L 52 53 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/ 54 #define AMDGPU_NUM_OF_VMIDS 8 55 56 static const u32 golden_settings_vega10_hdp[] = 57 { 58 0xf64, 0x0fffffff, 0x00000000, 59 0xf65, 0x0fffffff, 0x00000000, 60 0xf66, 0x0fffffff, 0x00000000, 61 0xf67, 0x0fffffff, 0x00000000, 62 0xf68, 0x0fffffff, 0x00000000, 63 0xf6a, 0x0fffffff, 0x00000000, 64 0xf6b, 0x0fffffff, 0x00000000, 65 0xf6c, 0x0fffffff, 0x00000000, 66 0xf6d, 0x0fffffff, 0x00000000, 67 0xf6e, 0x0fffffff, 0x00000000, 68 }; 69 70 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 71 struct amdgpu_irq_src *src, 72 unsigned type, 73 enum amdgpu_interrupt_state state) 74 { 75 struct amdgpu_vmhub *hub; 76 u32 tmp, reg, bits, i; 77 78 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 79 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 80 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 81 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 82 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 83 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 84 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 85 86 switch (state) { 87 case AMDGPU_IRQ_STATE_DISABLE: 88 /* MM HUB */ 89 hub = &adev->vmhub[AMDGPU_MMHUB]; 90 for (i = 0; i< 16; i++) { 91 reg = hub->vm_context0_cntl + i; 92 tmp = RREG32(reg); 93 tmp &= ~bits; 94 WREG32(reg, tmp); 95 } 96 97 /* GFX HUB */ 98 hub = &adev->vmhub[AMDGPU_GFXHUB]; 99 for (i = 0; i < 16; i++) { 100 reg = hub->vm_context0_cntl + i; 101 tmp = RREG32(reg); 102 tmp &= ~bits; 103 WREG32(reg, tmp); 104 } 105 break; 106 case AMDGPU_IRQ_STATE_ENABLE: 107 /* MM HUB */ 108 hub = &adev->vmhub[AMDGPU_MMHUB]; 109 for (i = 0; i< 16; i++) { 110 reg = hub->vm_context0_cntl + i; 111 tmp = RREG32(reg); 112 tmp |= bits; 113 WREG32(reg, tmp); 114 } 115 116 /* GFX HUB */ 117 hub = &adev->vmhub[AMDGPU_GFXHUB]; 118 for (i = 0; i < 16; i++) { 119 reg = hub->vm_context0_cntl + i; 120 tmp = RREG32(reg); 121 tmp |= bits; 122 WREG32(reg, tmp); 123 } 124 break; 125 default: 126 break; 127 } 128 129 return 0; 130 } 131 132 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 133 struct amdgpu_irq_src *source, 134 struct amdgpu_iv_entry *entry) 135 { 136 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src]; 137 uint32_t status = 0; 138 u64 addr; 139 140 addr = (u64)entry->src_data[0] << 12; 141 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 142 143 if (!amdgpu_sriov_vf(adev)) { 144 status = RREG32(hub->vm_l2_pro_fault_status); 145 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 146 } 147 148 if (printk_ratelimit()) { 149 dev_err(adev->dev, 150 "[%s] VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u)\n", 151 entry->vm_id_src ? "mmhub" : "gfxhub", 152 entry->src_id, entry->ring_id, entry->vm_id, 153 entry->pas_id); 154 dev_err(adev->dev, " at page 0x%016llx from %d\n", 155 addr, entry->client_id); 156 if (!amdgpu_sriov_vf(adev)) 157 dev_err(adev->dev, 158 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 159 status); 160 } 161 162 return 0; 163 } 164 165 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 166 .set = gmc_v9_0_vm_fault_interrupt_state, 167 .process = gmc_v9_0_process_interrupt, 168 }; 169 170 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 171 { 172 adev->mc.vm_fault.num_types = 1; 173 adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 174 } 175 176 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id) 177 { 178 u32 req = 0; 179 180 /* invalidate using legacy mode on vm_id*/ 181 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 182 PER_VMID_INVALIDATE_REQ, 1 << vm_id); 183 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0); 184 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 185 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 186 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 187 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 188 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 189 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 190 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 191 192 return req; 193 } 194 195 /* 196 * GART 197 * VMID 0 is the physical GPU addresses as used by the kernel. 198 * VMIDs 1-15 are used for userspace clients and are handled 199 * by the amdgpu vm/hsa code. 200 */ 201 202 /** 203 * gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback 204 * 205 * @adev: amdgpu_device pointer 206 * @vmid: vm instance to flush 207 * 208 * Flush the TLB for the requested page table. 209 */ 210 static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 211 uint32_t vmid) 212 { 213 /* Use register 17 for GART */ 214 const unsigned eng = 17; 215 unsigned i, j; 216 217 /* flush hdp cache */ 218 nbio_v6_1_hdp_flush(adev); 219 220 spin_lock(&adev->mc.invalidate_lock); 221 222 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { 223 struct amdgpu_vmhub *hub = &adev->vmhub[i]; 224 u32 tmp = gmc_v9_0_get_invalidate_req(vmid); 225 226 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp); 227 228 /* Busy wait for ACK.*/ 229 for (j = 0; j < 100; j++) { 230 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 231 tmp &= 1 << vmid; 232 if (tmp) 233 break; 234 cpu_relax(); 235 } 236 if (j < 100) 237 continue; 238 239 /* Wait for ACK with a delay.*/ 240 for (j = 0; j < adev->usec_timeout; j++) { 241 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng); 242 tmp &= 1 << vmid; 243 if (tmp) 244 break; 245 udelay(1); 246 } 247 if (j < adev->usec_timeout) 248 continue; 249 250 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 251 } 252 253 spin_unlock(&adev->mc.invalidate_lock); 254 } 255 256 /** 257 * gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO 258 * 259 * @adev: amdgpu_device pointer 260 * @cpu_pt_addr: cpu address of the page table 261 * @gpu_page_idx: entry in the page table to update 262 * @addr: dst addr to write into pte/pde 263 * @flags: access flags 264 * 265 * Update the page tables using the CPU. 266 */ 267 static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev, 268 void *cpu_pt_addr, 269 uint32_t gpu_page_idx, 270 uint64_t addr, 271 uint64_t flags) 272 { 273 void __iomem *ptr = (void *)cpu_pt_addr; 274 uint64_t value; 275 276 /* 277 * PTE format on VEGA 10: 278 * 63:59 reserved 279 * 58:57 mtype 280 * 56 F 281 * 55 L 282 * 54 P 283 * 53 SW 284 * 52 T 285 * 50:48 reserved 286 * 47:12 4k physical page base address 287 * 11:7 fragment 288 * 6 write 289 * 5 read 290 * 4 exe 291 * 3 Z 292 * 2 snooped 293 * 1 system 294 * 0 valid 295 * 296 * PDE format on VEGA 10: 297 * 63:59 block fragment size 298 * 58:55 reserved 299 * 54 P 300 * 53:48 reserved 301 * 47:6 physical base address of PD or PTE 302 * 5:3 reserved 303 * 2 C 304 * 1 system 305 * 0 valid 306 */ 307 308 /* 309 * The following is for PTE only. GART does not have PDEs. 310 */ 311 value = addr & 0x0000FFFFFFFFF000ULL; 312 value |= flags; 313 writeq(value, ptr + (gpu_page_idx * 8)); 314 return 0; 315 } 316 317 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, 318 uint32_t flags) 319 320 { 321 uint64_t pte_flag = 0; 322 323 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 324 pte_flag |= AMDGPU_PTE_EXECUTABLE; 325 if (flags & AMDGPU_VM_PAGE_READABLE) 326 pte_flag |= AMDGPU_PTE_READABLE; 327 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 328 pte_flag |= AMDGPU_PTE_WRITEABLE; 329 330 switch (flags & AMDGPU_VM_MTYPE_MASK) { 331 case AMDGPU_VM_MTYPE_DEFAULT: 332 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 333 break; 334 case AMDGPU_VM_MTYPE_NC: 335 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 336 break; 337 case AMDGPU_VM_MTYPE_WC: 338 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC); 339 break; 340 case AMDGPU_VM_MTYPE_CC: 341 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC); 342 break; 343 case AMDGPU_VM_MTYPE_UC: 344 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC); 345 break; 346 default: 347 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC); 348 break; 349 } 350 351 if (flags & AMDGPU_VM_PAGE_PRT) 352 pte_flag |= AMDGPU_PTE_PRT; 353 354 return pte_flag; 355 } 356 357 static u64 gmc_v9_0_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr) 358 { 359 return adev->vm_manager.vram_base_offset + mc_addr - adev->mc.vram_start; 360 } 361 362 static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = { 363 .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb, 364 .set_pte_pde = gmc_v9_0_gart_set_pte_pde, 365 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags, 366 .adjust_mc_addr = gmc_v9_0_adjust_mc_addr, 367 .get_invalidate_req = gmc_v9_0_get_invalidate_req, 368 }; 369 370 static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev) 371 { 372 if (adev->gart.gart_funcs == NULL) 373 adev->gart.gart_funcs = &gmc_v9_0_gart_funcs; 374 } 375 376 static int gmc_v9_0_early_init(void *handle) 377 { 378 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 379 380 gmc_v9_0_set_gart_funcs(adev); 381 gmc_v9_0_set_irq_funcs(adev); 382 383 return 0; 384 } 385 386 static int gmc_v9_0_late_init(void *handle) 387 { 388 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 389 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 390 } 391 392 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 393 struct amdgpu_mc *mc) 394 { 395 u64 base = 0; 396 if (!amdgpu_sriov_vf(adev)) 397 base = mmhub_v1_0_get_fb_location(adev); 398 amdgpu_vram_location(adev, &adev->mc, base); 399 adev->mc.gtt_base_align = 0; 400 amdgpu_gtt_location(adev, mc); 401 } 402 403 /** 404 * gmc_v9_0_mc_init - initialize the memory controller driver params 405 * 406 * @adev: amdgpu_device pointer 407 * 408 * Look up the amount of vram, vram width, and decide how to place 409 * vram and gart within the GPU's physical address space. 410 * Returns 0 for success. 411 */ 412 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 413 { 414 u32 tmp; 415 int chansize, numchan; 416 417 /* hbm memory channel size */ 418 chansize = 128; 419 420 tmp = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_CS_AON0_DramBaseAddress0)); 421 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK; 422 tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; 423 switch (tmp) { 424 case 0: 425 default: 426 numchan = 1; 427 break; 428 case 1: 429 numchan = 2; 430 break; 431 case 2: 432 numchan = 0; 433 break; 434 case 3: 435 numchan = 4; 436 break; 437 case 4: 438 numchan = 0; 439 break; 440 case 5: 441 numchan = 8; 442 break; 443 case 6: 444 numchan = 0; 445 break; 446 case 7: 447 numchan = 16; 448 break; 449 case 8: 450 numchan = 2; 451 break; 452 } 453 adev->mc.vram_width = numchan * chansize; 454 455 /* Could aper size report 0 ? */ 456 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 457 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 458 /* size in MB on si */ 459 adev->mc.mc_vram_size = 460 nbio_v6_1_get_memsize(adev) * 1024ULL * 1024ULL; 461 adev->mc.real_vram_size = adev->mc.mc_vram_size; 462 adev->mc.visible_vram_size = adev->mc.aper_size; 463 464 /* In case the PCI BAR is larger than the actual amount of vram */ 465 if (adev->mc.visible_vram_size > adev->mc.real_vram_size) 466 adev->mc.visible_vram_size = adev->mc.real_vram_size; 467 468 /* unless the user had overridden it, set the gart 469 * size equal to the 1024 or vram, whichever is larger. 470 */ 471 if (amdgpu_gart_size == -1) 472 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); 473 else 474 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; 475 476 gmc_v9_0_vram_gtt_location(adev, &adev->mc); 477 478 return 0; 479 } 480 481 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 482 { 483 int r; 484 485 if (adev->gart.robj) { 486 WARN(1, "VEGA10 PCIE GART already initialized\n"); 487 return 0; 488 } 489 /* Initialize common gart structure */ 490 r = amdgpu_gart_init(adev); 491 if (r) 492 return r; 493 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 494 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) | 495 AMDGPU_PTE_EXECUTABLE; 496 return amdgpu_gart_table_vram_alloc(adev); 497 } 498 499 /* 500 * vm 501 * VMID 0 is the physical GPU addresses as used by the kernel. 502 * VMIDs 1-15 are used for userspace clients and are handled 503 * by the amdgpu vm/hsa code. 504 */ 505 /** 506 * gmc_v9_0_vm_init - vm init callback 507 * 508 * @adev: amdgpu_device pointer 509 * 510 * Inits vega10 specific vm parameters (number of VMs, base of vram for 511 * VMIDs 1-15) (vega10). 512 * Returns 0 for success. 513 */ 514 static int gmc_v9_0_vm_init(struct amdgpu_device *adev) 515 { 516 /* 517 * number of VMs 518 * VMID 0 is reserved for System 519 * amdgpu graphics/compute will use VMIDs 1-7 520 * amdkfd will use VMIDs 8-15 521 */ 522 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS; 523 524 /* TODO: fix num_level for APU when updating vm size and block size */ 525 if (adev->flags & AMD_IS_APU) 526 adev->vm_manager.num_level = 1; 527 else 528 adev->vm_manager.num_level = 3; 529 amdgpu_vm_manager_init(adev); 530 531 /* base offset of vram pages */ 532 /*XXX This value is not zero for APU*/ 533 adev->vm_manager.vram_base_offset = 0; 534 535 return 0; 536 } 537 538 /** 539 * gmc_v9_0_vm_fini - vm fini callback 540 * 541 * @adev: amdgpu_device pointer 542 * 543 * Tear down any asic specific VM setup. 544 */ 545 static void gmc_v9_0_vm_fini(struct amdgpu_device *adev) 546 { 547 return; 548 } 549 550 static int gmc_v9_0_sw_init(void *handle) 551 { 552 int r; 553 int dma_bits; 554 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 555 556 spin_lock_init(&adev->mc.invalidate_lock); 557 558 if (adev->flags & AMD_IS_APU) { 559 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 560 amdgpu_vm_adjust_size(adev, 64); 561 } else { 562 /* XXX Don't know how to get VRAM type yet. */ 563 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; 564 /* 565 * To fulfill 4-level page support, 566 * vm size is 256TB (48bit), maximum size of Vega10, 567 * block size 512 (9bit) 568 */ 569 adev->vm_manager.vm_size = 1U << 18; 570 adev->vm_manager.block_size = 9; 571 DRM_INFO("vm size is %llu GB, block size is %u-bit\n", 572 adev->vm_manager.vm_size, 573 adev->vm_manager.block_size); 574 } 575 576 /* This interrupt is VMC page fault.*/ 577 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, 578 &adev->mc.vm_fault); 579 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0, 580 &adev->mc.vm_fault); 581 582 if (r) 583 return r; 584 585 adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; 586 587 /* Set the internal MC address mask 588 * This is the max address of the GPU's 589 * internal address space. 590 */ 591 adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 592 593 /* set DMA mask + need_dma32 flags. 594 * PCIE - can handle 44-bits. 595 * IGP - can handle 44-bits 596 * PCI - dma32 for legacy pci gart, 44 bits on vega10 597 */ 598 adev->need_dma32 = false; 599 dma_bits = adev->need_dma32 ? 32 : 44; 600 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 601 if (r) { 602 adev->need_dma32 = true; 603 dma_bits = 32; 604 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 605 } 606 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 607 if (r) { 608 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 609 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); 610 } 611 612 r = gmc_v9_0_mc_init(adev); 613 if (r) 614 return r; 615 616 /* Memory manager */ 617 r = amdgpu_bo_init(adev); 618 if (r) 619 return r; 620 621 r = gmc_v9_0_gart_init(adev); 622 if (r) 623 return r; 624 625 if (!adev->vm_manager.enabled) { 626 r = gmc_v9_0_vm_init(adev); 627 if (r) { 628 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 629 return r; 630 } 631 adev->vm_manager.enabled = true; 632 } 633 return r; 634 } 635 636 /** 637 * gmc_v8_0_gart_fini - vm fini callback 638 * 639 * @adev: amdgpu_device pointer 640 * 641 * Tears down the driver GART/VM setup (CIK). 642 */ 643 static void gmc_v9_0_gart_fini(struct amdgpu_device *adev) 644 { 645 amdgpu_gart_table_vram_free(adev); 646 amdgpu_gart_fini(adev); 647 } 648 649 static int gmc_v9_0_sw_fini(void *handle) 650 { 651 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 652 653 if (adev->vm_manager.enabled) { 654 amdgpu_vm_manager_fini(adev); 655 gmc_v9_0_vm_fini(adev); 656 adev->vm_manager.enabled = false; 657 } 658 gmc_v9_0_gart_fini(adev); 659 amdgpu_gem_force_release(adev); 660 amdgpu_bo_fini(adev); 661 662 return 0; 663 } 664 665 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 666 { 667 switch (adev->asic_type) { 668 case CHIP_VEGA10: 669 break; 670 default: 671 break; 672 } 673 } 674 675 /** 676 * gmc_v9_0_gart_enable - gart enable 677 * 678 * @adev: amdgpu_device pointer 679 */ 680 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 681 { 682 int r; 683 bool value; 684 u32 tmp; 685 686 amdgpu_program_register_sequence(adev, 687 golden_settings_vega10_hdp, 688 (const u32)ARRAY_SIZE(golden_settings_vega10_hdp)); 689 690 if (adev->gart.robj == NULL) { 691 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 692 return -EINVAL; 693 } 694 r = amdgpu_gart_table_vram_pin(adev); 695 if (r) 696 return r; 697 698 /* After HDP is initialized, flush HDP.*/ 699 nbio_v6_1_hdp_flush(adev); 700 701 r = gfxhub_v1_0_gart_enable(adev); 702 if (r) 703 return r; 704 705 r = mmhub_v1_0_gart_enable(adev); 706 if (r) 707 return r; 708 709 tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL)); 710 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK; 711 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MISC_CNTL), tmp); 712 713 tmp = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL)); 714 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_HOST_PATH_CNTL), tmp); 715 716 717 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 718 value = false; 719 else 720 value = true; 721 722 gfxhub_v1_0_set_fault_enable_default(adev, value); 723 mmhub_v1_0_set_fault_enable_default(adev, value); 724 725 gmc_v9_0_gart_flush_gpu_tlb(adev, 0); 726 727 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 728 (unsigned)(adev->mc.gtt_size >> 20), 729 (unsigned long long)adev->gart.table_addr); 730 adev->gart.ready = true; 731 return 0; 732 } 733 734 static int gmc_v9_0_hw_init(void *handle) 735 { 736 int r; 737 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 738 739 /* The sequence of these two function calls matters.*/ 740 gmc_v9_0_init_golden_registers(adev); 741 742 r = gmc_v9_0_gart_enable(adev); 743 744 return r; 745 } 746 747 /** 748 * gmc_v9_0_gart_disable - gart disable 749 * 750 * @adev: amdgpu_device pointer 751 * 752 * This disables all VM page table. 753 */ 754 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 755 { 756 gfxhub_v1_0_gart_disable(adev); 757 mmhub_v1_0_gart_disable(adev); 758 amdgpu_gart_table_vram_unpin(adev); 759 } 760 761 static int gmc_v9_0_hw_fini(void *handle) 762 { 763 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 764 765 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 766 gmc_v9_0_gart_disable(adev); 767 768 return 0; 769 } 770 771 static int gmc_v9_0_suspend(void *handle) 772 { 773 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 774 775 if (adev->vm_manager.enabled) { 776 gmc_v9_0_vm_fini(adev); 777 adev->vm_manager.enabled = false; 778 } 779 gmc_v9_0_hw_fini(adev); 780 781 return 0; 782 } 783 784 static int gmc_v9_0_resume(void *handle) 785 { 786 int r; 787 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 788 789 r = gmc_v9_0_hw_init(adev); 790 if (r) 791 return r; 792 793 if (!adev->vm_manager.enabled) { 794 r = gmc_v9_0_vm_init(adev); 795 if (r) { 796 dev_err(adev->dev, 797 "vm manager initialization failed (%d).\n", r); 798 return r; 799 } 800 adev->vm_manager.enabled = true; 801 } 802 803 return r; 804 } 805 806 static bool gmc_v9_0_is_idle(void *handle) 807 { 808 /* MC is always ready in GMC v9.*/ 809 return true; 810 } 811 812 static int gmc_v9_0_wait_for_idle(void *handle) 813 { 814 /* There is no need to wait for MC idle in GMC v9.*/ 815 return 0; 816 } 817 818 static int gmc_v9_0_soft_reset(void *handle) 819 { 820 /* XXX for emulation.*/ 821 return 0; 822 } 823 824 static int gmc_v9_0_set_clockgating_state(void *handle, 825 enum amd_clockgating_state state) 826 { 827 return 0; 828 } 829 830 static int gmc_v9_0_set_powergating_state(void *handle, 831 enum amd_powergating_state state) 832 { 833 return 0; 834 } 835 836 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 837 .name = "gmc_v9_0", 838 .early_init = gmc_v9_0_early_init, 839 .late_init = gmc_v9_0_late_init, 840 .sw_init = gmc_v9_0_sw_init, 841 .sw_fini = gmc_v9_0_sw_fini, 842 .hw_init = gmc_v9_0_hw_init, 843 .hw_fini = gmc_v9_0_hw_fini, 844 .suspend = gmc_v9_0_suspend, 845 .resume = gmc_v9_0_resume, 846 .is_idle = gmc_v9_0_is_idle, 847 .wait_for_idle = gmc_v9_0_wait_for_idle, 848 .soft_reset = gmc_v9_0_soft_reset, 849 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 850 .set_powergating_state = gmc_v9_0_set_powergating_state, 851 }; 852 853 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = 854 { 855 .type = AMD_IP_BLOCK_TYPE_GMC, 856 .major = 9, 857 .minor = 0, 858 .rev = 0, 859 .funcs = &gmc_v9_0_ip_funcs, 860 }; 861