1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "umc_v12_0.h" 60 #include "hdp_v4_0.h" 61 #include "mca_v3_0.h" 62 63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 64 65 #include "amdgpu_ras.h" 66 #include "amdgpu_xgmi.h" 67 68 #include "amdgpu_reset.h" 69 70 /* add these here since we already include dce12 headers and these are for DCN */ 71 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 72 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 75 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 76 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 77 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 78 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 79 80 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 81 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 82 83 #define MAX_MEM_RANGES 8 84 85 static const char * const gfxhub_client_ids[] = { 86 "CB", 87 "DB", 88 "IA", 89 "WD", 90 "CPF", 91 "CPC", 92 "CPG", 93 "RLC", 94 "TCP", 95 "SQC (inst)", 96 "SQC (data)", 97 "SQG", 98 "PA", 99 }; 100 101 static const char *mmhub_client_ids_raven[][2] = { 102 [0][0] = "MP1", 103 [1][0] = "MP0", 104 [2][0] = "VCN", 105 [3][0] = "VCNU", 106 [4][0] = "HDP", 107 [5][0] = "DCE", 108 [13][0] = "UTCL2", 109 [19][0] = "TLS", 110 [26][0] = "OSS", 111 [27][0] = "SDMA0", 112 [0][1] = "MP1", 113 [1][1] = "MP0", 114 [2][1] = "VCN", 115 [3][1] = "VCNU", 116 [4][1] = "HDP", 117 [5][1] = "XDP", 118 [6][1] = "DBGU0", 119 [7][1] = "DCE", 120 [8][1] = "DCEDWB0", 121 [9][1] = "DCEDWB1", 122 [26][1] = "OSS", 123 [27][1] = "SDMA0", 124 }; 125 126 static const char *mmhub_client_ids_renoir[][2] = { 127 [0][0] = "MP1", 128 [1][0] = "MP0", 129 [2][0] = "HDP", 130 [4][0] = "DCEDMC", 131 [5][0] = "DCEVGA", 132 [13][0] = "UTCL2", 133 [19][0] = "TLS", 134 [26][0] = "OSS", 135 [27][0] = "SDMA0", 136 [28][0] = "VCN", 137 [29][0] = "VCNU", 138 [30][0] = "JPEG", 139 [0][1] = "MP1", 140 [1][1] = "MP0", 141 [2][1] = "HDP", 142 [3][1] = "XDP", 143 [6][1] = "DBGU0", 144 [7][1] = "DCEDMC", 145 [8][1] = "DCEVGA", 146 [9][1] = "DCEDWB", 147 [26][1] = "OSS", 148 [27][1] = "SDMA0", 149 [28][1] = "VCN", 150 [29][1] = "VCNU", 151 [30][1] = "JPEG", 152 }; 153 154 static const char *mmhub_client_ids_vega10[][2] = { 155 [0][0] = "MP0", 156 [1][0] = "UVD", 157 [2][0] = "UVDU", 158 [3][0] = "HDP", 159 [13][0] = "UTCL2", 160 [14][0] = "OSS", 161 [15][0] = "SDMA1", 162 [32+0][0] = "VCE0", 163 [32+1][0] = "VCE0U", 164 [32+2][0] = "XDMA", 165 [32+3][0] = "DCE", 166 [32+4][0] = "MP1", 167 [32+14][0] = "SDMA0", 168 [0][1] = "MP0", 169 [1][1] = "UVD", 170 [2][1] = "UVDU", 171 [3][1] = "DBGU0", 172 [4][1] = "HDP", 173 [5][1] = "XDP", 174 [14][1] = "OSS", 175 [15][1] = "SDMA0", 176 [32+0][1] = "VCE0", 177 [32+1][1] = "VCE0U", 178 [32+2][1] = "XDMA", 179 [32+3][1] = "DCE", 180 [32+4][1] = "DCEDWB", 181 [32+5][1] = "MP1", 182 [32+6][1] = "DBGU1", 183 [32+14][1] = "SDMA1", 184 }; 185 186 static const char *mmhub_client_ids_vega12[][2] = { 187 [0][0] = "MP0", 188 [1][0] = "VCE0", 189 [2][0] = "VCE0U", 190 [3][0] = "HDP", 191 [13][0] = "UTCL2", 192 [14][0] = "OSS", 193 [15][0] = "SDMA1", 194 [32+0][0] = "DCE", 195 [32+1][0] = "XDMA", 196 [32+2][0] = "UVD", 197 [32+3][0] = "UVDU", 198 [32+4][0] = "MP1", 199 [32+15][0] = "SDMA0", 200 [0][1] = "MP0", 201 [1][1] = "VCE0", 202 [2][1] = "VCE0U", 203 [3][1] = "DBGU0", 204 [4][1] = "HDP", 205 [5][1] = "XDP", 206 [14][1] = "OSS", 207 [15][1] = "SDMA0", 208 [32+0][1] = "DCE", 209 [32+1][1] = "DCEDWB", 210 [32+2][1] = "XDMA", 211 [32+3][1] = "UVD", 212 [32+4][1] = "UVDU", 213 [32+5][1] = "MP1", 214 [32+6][1] = "DBGU1", 215 [32+15][1] = "SDMA1", 216 }; 217 218 static const char *mmhub_client_ids_vega20[][2] = { 219 [0][0] = "XDMA", 220 [1][0] = "DCE", 221 [2][0] = "VCE0", 222 [3][0] = "VCE0U", 223 [4][0] = "UVD", 224 [5][0] = "UVD1U", 225 [13][0] = "OSS", 226 [14][0] = "HDP", 227 [15][0] = "SDMA0", 228 [32+0][0] = "UVD", 229 [32+1][0] = "UVDU", 230 [32+2][0] = "MP1", 231 [32+3][0] = "MP0", 232 [32+12][0] = "UTCL2", 233 [32+14][0] = "SDMA1", 234 [0][1] = "XDMA", 235 [1][1] = "DCE", 236 [2][1] = "DCEDWB", 237 [3][1] = "VCE0", 238 [4][1] = "VCE0U", 239 [5][1] = "UVD1", 240 [6][1] = "UVD1U", 241 [7][1] = "DBGU0", 242 [8][1] = "XDP", 243 [13][1] = "OSS", 244 [14][1] = "HDP", 245 [15][1] = "SDMA0", 246 [32+0][1] = "UVD", 247 [32+1][1] = "UVDU", 248 [32+2][1] = "DBGU1", 249 [32+3][1] = "MP1", 250 [32+4][1] = "MP0", 251 [32+14][1] = "SDMA1", 252 }; 253 254 static const char *mmhub_client_ids_arcturus[][2] = { 255 [0][0] = "DBGU1", 256 [1][0] = "XDP", 257 [2][0] = "MP1", 258 [14][0] = "HDP", 259 [171][0] = "JPEG", 260 [172][0] = "VCN", 261 [173][0] = "VCNU", 262 [203][0] = "JPEG1", 263 [204][0] = "VCN1", 264 [205][0] = "VCN1U", 265 [256][0] = "SDMA0", 266 [257][0] = "SDMA1", 267 [258][0] = "SDMA2", 268 [259][0] = "SDMA3", 269 [260][0] = "SDMA4", 270 [261][0] = "SDMA5", 271 [262][0] = "SDMA6", 272 [263][0] = "SDMA7", 273 [384][0] = "OSS", 274 [0][1] = "DBGU1", 275 [1][1] = "XDP", 276 [2][1] = "MP1", 277 [14][1] = "HDP", 278 [171][1] = "JPEG", 279 [172][1] = "VCN", 280 [173][1] = "VCNU", 281 [203][1] = "JPEG1", 282 [204][1] = "VCN1", 283 [205][1] = "VCN1U", 284 [256][1] = "SDMA0", 285 [257][1] = "SDMA1", 286 [258][1] = "SDMA2", 287 [259][1] = "SDMA3", 288 [260][1] = "SDMA4", 289 [261][1] = "SDMA5", 290 [262][1] = "SDMA6", 291 [263][1] = "SDMA7", 292 [384][1] = "OSS", 293 }; 294 295 static const char *mmhub_client_ids_aldebaran[][2] = { 296 [2][0] = "MP1", 297 [3][0] = "MP0", 298 [32+1][0] = "DBGU_IO0", 299 [32+2][0] = "DBGU_IO2", 300 [32+4][0] = "MPIO", 301 [96+11][0] = "JPEG0", 302 [96+12][0] = "VCN0", 303 [96+13][0] = "VCNU0", 304 [128+11][0] = "JPEG1", 305 [128+12][0] = "VCN1", 306 [128+13][0] = "VCNU1", 307 [160+1][0] = "XDP", 308 [160+14][0] = "HDP", 309 [256+0][0] = "SDMA0", 310 [256+1][0] = "SDMA1", 311 [256+2][0] = "SDMA2", 312 [256+3][0] = "SDMA3", 313 [256+4][0] = "SDMA4", 314 [384+0][0] = "OSS", 315 [2][1] = "MP1", 316 [3][1] = "MP0", 317 [32+1][1] = "DBGU_IO0", 318 [32+2][1] = "DBGU_IO2", 319 [32+4][1] = "MPIO", 320 [96+11][1] = "JPEG0", 321 [96+12][1] = "VCN0", 322 [96+13][1] = "VCNU0", 323 [128+11][1] = "JPEG1", 324 [128+12][1] = "VCN1", 325 [128+13][1] = "VCNU1", 326 [160+1][1] = "XDP", 327 [160+14][1] = "HDP", 328 [256+0][1] = "SDMA0", 329 [256+1][1] = "SDMA1", 330 [256+2][1] = "SDMA2", 331 [256+3][1] = "SDMA3", 332 [256+4][1] = "SDMA4", 333 [384+0][1] = "OSS", 334 }; 335 336 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { 337 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 338 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 339 }; 340 341 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { 342 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 343 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 344 }; 345 346 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 347 (0x000143c0 + 0x00000000), 348 (0x000143c0 + 0x00000800), 349 (0x000143c0 + 0x00001000), 350 (0x000143c0 + 0x00001800), 351 (0x000543c0 + 0x00000000), 352 (0x000543c0 + 0x00000800), 353 (0x000543c0 + 0x00001000), 354 (0x000543c0 + 0x00001800), 355 (0x000943c0 + 0x00000000), 356 (0x000943c0 + 0x00000800), 357 (0x000943c0 + 0x00001000), 358 (0x000943c0 + 0x00001800), 359 (0x000d43c0 + 0x00000000), 360 (0x000d43c0 + 0x00000800), 361 (0x000d43c0 + 0x00001000), 362 (0x000d43c0 + 0x00001800), 363 (0x001143c0 + 0x00000000), 364 (0x001143c0 + 0x00000800), 365 (0x001143c0 + 0x00001000), 366 (0x001143c0 + 0x00001800), 367 (0x001543c0 + 0x00000000), 368 (0x001543c0 + 0x00000800), 369 (0x001543c0 + 0x00001000), 370 (0x001543c0 + 0x00001800), 371 (0x001943c0 + 0x00000000), 372 (0x001943c0 + 0x00000800), 373 (0x001943c0 + 0x00001000), 374 (0x001943c0 + 0x00001800), 375 (0x001d43c0 + 0x00000000), 376 (0x001d43c0 + 0x00000800), 377 (0x001d43c0 + 0x00001000), 378 (0x001d43c0 + 0x00001800), 379 }; 380 381 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 382 (0x000143e0 + 0x00000000), 383 (0x000143e0 + 0x00000800), 384 (0x000143e0 + 0x00001000), 385 (0x000143e0 + 0x00001800), 386 (0x000543e0 + 0x00000000), 387 (0x000543e0 + 0x00000800), 388 (0x000543e0 + 0x00001000), 389 (0x000543e0 + 0x00001800), 390 (0x000943e0 + 0x00000000), 391 (0x000943e0 + 0x00000800), 392 (0x000943e0 + 0x00001000), 393 (0x000943e0 + 0x00001800), 394 (0x000d43e0 + 0x00000000), 395 (0x000d43e0 + 0x00000800), 396 (0x000d43e0 + 0x00001000), 397 (0x000d43e0 + 0x00001800), 398 (0x001143e0 + 0x00000000), 399 (0x001143e0 + 0x00000800), 400 (0x001143e0 + 0x00001000), 401 (0x001143e0 + 0x00001800), 402 (0x001543e0 + 0x00000000), 403 (0x001543e0 + 0x00000800), 404 (0x001543e0 + 0x00001000), 405 (0x001543e0 + 0x00001800), 406 (0x001943e0 + 0x00000000), 407 (0x001943e0 + 0x00000800), 408 (0x001943e0 + 0x00001000), 409 (0x001943e0 + 0x00001800), 410 (0x001d43e0 + 0x00000000), 411 (0x001d43e0 + 0x00000800), 412 (0x001d43e0 + 0x00001000), 413 (0x001d43e0 + 0x00001800), 414 }; 415 416 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 417 struct amdgpu_irq_src *src, 418 unsigned int type, 419 enum amdgpu_interrupt_state state) 420 { 421 u32 bits, i, tmp, reg; 422 423 /* Devices newer then VEGA10/12 shall have these programming 424 * sequences performed by PSP BL 425 */ 426 if (adev->asic_type >= CHIP_VEGA20) 427 return 0; 428 429 bits = 0x7f; 430 431 switch (state) { 432 case AMDGPU_IRQ_STATE_DISABLE: 433 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 434 reg = ecc_umc_mcumc_ctrl_addrs[i]; 435 tmp = RREG32(reg); 436 tmp &= ~bits; 437 WREG32(reg, tmp); 438 } 439 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 440 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 441 tmp = RREG32(reg); 442 tmp &= ~bits; 443 WREG32(reg, tmp); 444 } 445 break; 446 case AMDGPU_IRQ_STATE_ENABLE: 447 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 448 reg = ecc_umc_mcumc_ctrl_addrs[i]; 449 tmp = RREG32(reg); 450 tmp |= bits; 451 WREG32(reg, tmp); 452 } 453 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 454 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 455 tmp = RREG32(reg); 456 tmp |= bits; 457 WREG32(reg, tmp); 458 } 459 break; 460 default: 461 break; 462 } 463 464 return 0; 465 } 466 467 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 468 struct amdgpu_irq_src *src, 469 unsigned int type, 470 enum amdgpu_interrupt_state state) 471 { 472 struct amdgpu_vmhub *hub; 473 u32 tmp, reg, bits, i, j; 474 475 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 479 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 480 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 481 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 482 483 switch (state) { 484 case AMDGPU_IRQ_STATE_DISABLE: 485 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 486 hub = &adev->vmhub[j]; 487 for (i = 0; i < 16; i++) { 488 reg = hub->vm_context0_cntl + i; 489 490 /* This works because this interrupt is only 491 * enabled at init/resume and disabled in 492 * fini/suspend, so the overall state doesn't 493 * change over the course of suspend/resume. 494 */ 495 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 496 continue; 497 498 if (j >= AMDGPU_MMHUB0(0)) 499 tmp = RREG32_SOC15_IP(MMHUB, reg); 500 else 501 tmp = RREG32_SOC15_IP(GC, reg); 502 503 tmp &= ~bits; 504 505 if (j >= AMDGPU_MMHUB0(0)) 506 WREG32_SOC15_IP(MMHUB, reg, tmp); 507 else 508 WREG32_SOC15_IP(GC, reg, tmp); 509 } 510 } 511 break; 512 case AMDGPU_IRQ_STATE_ENABLE: 513 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 514 hub = &adev->vmhub[j]; 515 for (i = 0; i < 16; i++) { 516 reg = hub->vm_context0_cntl + i; 517 518 /* This works because this interrupt is only 519 * enabled at init/resume and disabled in 520 * fini/suspend, so the overall state doesn't 521 * change over the course of suspend/resume. 522 */ 523 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 524 continue; 525 526 if (j >= AMDGPU_MMHUB0(0)) 527 tmp = RREG32_SOC15_IP(MMHUB, reg); 528 else 529 tmp = RREG32_SOC15_IP(GC, reg); 530 531 tmp |= bits; 532 533 if (j >= AMDGPU_MMHUB0(0)) 534 WREG32_SOC15_IP(MMHUB, reg, tmp); 535 else 536 WREG32_SOC15_IP(GC, reg, tmp); 537 } 538 } 539 break; 540 default: 541 break; 542 } 543 544 return 0; 545 } 546 547 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 548 struct amdgpu_irq_src *source, 549 struct amdgpu_iv_entry *entry) 550 { 551 bool retry_fault = !!(entry->src_data[1] & 0x80); 552 bool write_fault = !!(entry->src_data[1] & 0x20); 553 uint32_t status = 0, cid = 0, rw = 0; 554 struct amdgpu_task_info task_info; 555 struct amdgpu_vmhub *hub; 556 const char *mmhub_cid; 557 const char *hub_name; 558 u64 addr; 559 uint32_t cam_index = 0; 560 int ret, xcc_id = 0; 561 uint32_t node_id; 562 563 node_id = entry->node_id; 564 565 addr = (u64)entry->src_data[0] << 12; 566 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 567 568 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 569 hub_name = "mmhub0"; 570 hub = &adev->vmhub[AMDGPU_MMHUB0(node_id / 4)]; 571 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 572 hub_name = "mmhub1"; 573 hub = &adev->vmhub[AMDGPU_MMHUB1(0)]; 574 } else { 575 hub_name = "gfxhub0"; 576 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 577 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 578 node_id); 579 if (xcc_id < 0) 580 xcc_id = 0; 581 } 582 hub = &adev->vmhub[xcc_id]; 583 } 584 585 if (retry_fault) { 586 if (adev->irq.retry_cam_enabled) { 587 /* Delegate it to a different ring if the hardware hasn't 588 * already done it. 589 */ 590 if (entry->ih == &adev->irq.ih) { 591 amdgpu_irq_delegate(adev, entry, 8); 592 return 1; 593 } 594 595 cam_index = entry->src_data[2] & 0x3ff; 596 597 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 598 addr, write_fault); 599 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 600 if (ret) 601 return 1; 602 } else { 603 /* Process it onyl if it's the first fault for this address */ 604 if (entry->ih != &adev->irq.ih_soft && 605 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 606 entry->timestamp)) 607 return 1; 608 609 /* Delegate it to a different ring if the hardware hasn't 610 * already done it. 611 */ 612 if (entry->ih == &adev->irq.ih) { 613 amdgpu_irq_delegate(adev, entry, 8); 614 return 1; 615 } 616 617 /* Try to handle the recoverable page faults by filling page 618 * tables 619 */ 620 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 621 addr, write_fault)) 622 return 1; 623 } 624 } 625 626 if (!printk_ratelimit()) 627 return 0; 628 629 630 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 631 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 632 633 dev_err(adev->dev, 634 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n", 635 hub_name, retry_fault ? "retry" : "no-retry", 636 entry->src_id, entry->ring_id, entry->vmid, 637 entry->pasid, task_info.process_name, task_info.tgid, 638 task_info.task_name, task_info.pid); 639 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 640 addr, entry->client_id, 641 soc15_ih_clientid_name[entry->client_id]); 642 643 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 644 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 645 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 646 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 647 648 if (amdgpu_sriov_vf(adev)) 649 return 0; 650 651 /* 652 * Issue a dummy read to wait for the status register to 653 * be updated to avoid reading an incorrect value due to 654 * the new fast GRBM interface. 655 */ 656 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 657 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 658 RREG32(hub->vm_l2_pro_fault_status); 659 660 status = RREG32(hub->vm_l2_pro_fault_status); 661 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 662 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 663 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 664 665 dev_err(adev->dev, 666 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 667 status); 668 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 669 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 670 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 671 gfxhub_client_ids[cid], 672 cid); 673 } else { 674 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 675 case IP_VERSION(9, 0, 0): 676 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 677 break; 678 case IP_VERSION(9, 3, 0): 679 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 680 break; 681 case IP_VERSION(9, 4, 0): 682 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 683 break; 684 case IP_VERSION(9, 4, 1): 685 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 686 break; 687 case IP_VERSION(9, 1, 0): 688 case IP_VERSION(9, 2, 0): 689 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 690 break; 691 case IP_VERSION(1, 5, 0): 692 case IP_VERSION(2, 4, 0): 693 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 694 break; 695 case IP_VERSION(1, 8, 0): 696 case IP_VERSION(9, 4, 2): 697 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 698 break; 699 default: 700 mmhub_cid = NULL; 701 break; 702 } 703 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 704 mmhub_cid ? mmhub_cid : "unknown", cid); 705 } 706 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 707 REG_GET_FIELD(status, 708 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 709 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 710 REG_GET_FIELD(status, 711 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 712 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 713 REG_GET_FIELD(status, 714 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 715 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 716 REG_GET_FIELD(status, 717 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 718 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 719 return 0; 720 } 721 722 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 723 .set = gmc_v9_0_vm_fault_interrupt_state, 724 .process = gmc_v9_0_process_interrupt, 725 }; 726 727 728 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 729 .set = gmc_v9_0_ecc_interrupt_state, 730 .process = amdgpu_umc_process_ecc_irq, 731 }; 732 733 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 734 { 735 adev->gmc.vm_fault.num_types = 1; 736 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 737 738 if (!amdgpu_sriov_vf(adev) && 739 !adev->gmc.xgmi.connected_to_cpu && 740 !adev->gmc.is_app_apu) { 741 adev->gmc.ecc_irq.num_types = 1; 742 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 743 } 744 } 745 746 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 747 uint32_t flush_type) 748 { 749 u32 req = 0; 750 751 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 752 PER_VMID_INVALIDATE_REQ, 1 << vmid); 753 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 754 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 755 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 756 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 757 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 758 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 759 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 760 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 761 762 return req; 763 } 764 765 /** 766 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 767 * 768 * @adev: amdgpu_device pointer 769 * @vmhub: vmhub type 770 * 771 */ 772 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 773 uint32_t vmhub) 774 { 775 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 776 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 777 return false; 778 779 return ((vmhub == AMDGPU_MMHUB0(0) || 780 vmhub == AMDGPU_MMHUB1(0)) && 781 (!amdgpu_sriov_vf(adev)) && 782 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 783 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 784 } 785 786 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 787 uint8_t vmid, uint16_t *p_pasid) 788 { 789 uint32_t value; 790 791 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 792 + vmid); 793 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 794 795 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 796 } 797 798 /* 799 * GART 800 * VMID 0 is the physical GPU addresses as used by the kernel. 801 * VMIDs 1-15 are used for userspace clients and are handled 802 * by the amdgpu vm/hsa code. 803 */ 804 805 /** 806 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 807 * 808 * @adev: amdgpu_device pointer 809 * @vmid: vm instance to flush 810 * @vmhub: which hub to flush 811 * @flush_type: the flush type 812 * 813 * Flush the TLB for the requested page table using certain type. 814 */ 815 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 816 uint32_t vmhub, uint32_t flush_type) 817 { 818 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 819 const unsigned int eng = 17; 820 u32 j, inv_req, inv_req2, tmp; 821 struct amdgpu_vmhub *hub; 822 823 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 824 825 hub = &adev->vmhub[vmhub]; 826 if (adev->gmc.xgmi.num_physical_nodes && 827 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0)) { 828 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 829 * heavy-weight TLB flush (type 2), which flushes 830 * both. Due to a race condition with concurrent 831 * memory accesses using the same TLB cache line, we 832 * still need a second TLB flush after this. 833 */ 834 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2); 835 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); 836 } else if (flush_type == 2 && 837 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 838 adev->rev_id == 0) { 839 inv_req = gmc_v9_0_get_invalidate_req(vmid, 0); 840 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type); 841 } else { 842 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 843 inv_req2 = 0; 844 } 845 846 /* This is necessary for a HW workaround under SRIOV as well 847 * as GFXOFF under bare metal 848 */ 849 if (adev->gfx.kiq[0].ring.sched.ready && 850 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 851 down_read_trylock(&adev->reset_domain->sem)) { 852 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 853 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 854 855 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 856 1 << vmid); 857 up_read(&adev->reset_domain->sem); 858 return; 859 } 860 861 spin_lock(&adev->gmc.invalidate_lock); 862 863 /* 864 * It may lose gpuvm invalidate acknowldege state across power-gating 865 * off cycle, add semaphore acquire before invalidation and semaphore 866 * release after invalidation to avoid entering power gated state 867 * to WA the Issue 868 */ 869 870 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 871 if (use_semaphore) { 872 for (j = 0; j < adev->usec_timeout; j++) { 873 /* a read return value of 1 means semaphore acquire */ 874 if (vmhub >= AMDGPU_MMHUB0(0)) 875 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 876 else 877 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng); 878 if (tmp & 0x1) 879 break; 880 udelay(1); 881 } 882 883 if (j >= adev->usec_timeout) 884 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 885 } 886 887 do { 888 if (vmhub >= AMDGPU_MMHUB0(0)) 889 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 890 else 891 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 892 893 /* 894 * Issue a dummy read to wait for the ACK register to 895 * be cleared to avoid a false ACK due to the new fast 896 * GRBM interface. 897 */ 898 if ((vmhub == AMDGPU_GFXHUB(0)) && 899 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 900 RREG32_NO_KIQ(hub->vm_inv_eng0_req + 901 hub->eng_distance * eng); 902 903 for (j = 0; j < adev->usec_timeout; j++) { 904 if (vmhub >= AMDGPU_MMHUB0(0)) 905 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 906 else 907 tmp = RREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_ack + hub->eng_distance * eng); 908 if (tmp & (1 << vmid)) 909 break; 910 udelay(1); 911 } 912 913 inv_req = inv_req2; 914 inv_req2 = 0; 915 } while (inv_req); 916 917 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 918 if (use_semaphore) { 919 /* 920 * add semaphore release after invalidation, 921 * write with 0 means semaphore release 922 */ 923 if (vmhub >= AMDGPU_MMHUB0(0)) 924 WREG32_SOC15_IP_NO_KIQ(MMHUB, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 925 else 926 WREG32_SOC15_IP_NO_KIQ(GC, hub->vm_inv_eng0_sem + hub->eng_distance * eng, 0); 927 } 928 929 spin_unlock(&adev->gmc.invalidate_lock); 930 931 if (j < adev->usec_timeout) 932 return; 933 934 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 935 } 936 937 /** 938 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 939 * 940 * @adev: amdgpu_device pointer 941 * @pasid: pasid to be flush 942 * @flush_type: the flush type 943 * @all_hub: flush all hubs 944 * @inst: is used to select which instance of KIQ to use for the invalidation 945 * 946 * Flush the TLB for the requested pasid. 947 */ 948 static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 949 uint16_t pasid, uint32_t flush_type, 950 bool all_hub, uint32_t inst) 951 { 952 int vmid, i; 953 signed long r; 954 uint32_t seq; 955 uint16_t queried_pasid; 956 bool ret; 957 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; 958 struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring; 959 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 960 961 if (amdgpu_in_reset(adev)) 962 return -EIO; 963 964 if (ring->sched.ready && down_read_trylock(&adev->reset_domain->sem)) { 965 /* Vega20+XGMI caches PTEs in TC and TLB. Add a 966 * heavy-weight TLB flush (type 2), which flushes 967 * both. Due to a race condition with concurrent 968 * memory accesses using the same TLB cache line, we 969 * still need a second TLB flush after this. 970 */ 971 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes && 972 amdgpu_ip_version(adev, GC_HWIP, 0) == 973 IP_VERSION(9, 4, 0)); 974 /* 2 dwords flush + 8 dwords fence */ 975 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8; 976 977 if (vega20_xgmi_wa) 978 ndw += kiq->pmf->invalidate_tlbs_size; 979 980 spin_lock(&adev->gfx.kiq[inst].ring_lock); 981 /* 2 dwords flush + 8 dwords fence */ 982 amdgpu_ring_alloc(ring, ndw); 983 if (vega20_xgmi_wa) 984 kiq->pmf->kiq_invalidate_tlbs(ring, 985 pasid, 2, all_hub); 986 987 if (flush_type == 2 && 988 amdgpu_ip_version(adev, GC_HWIP, 0) == 989 IP_VERSION(9, 4, 3) && 990 adev->rev_id == 0) 991 kiq->pmf->kiq_invalidate_tlbs(ring, 992 pasid, 0, all_hub); 993 994 kiq->pmf->kiq_invalidate_tlbs(ring, 995 pasid, flush_type, all_hub); 996 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 997 if (r) { 998 amdgpu_ring_undo(ring); 999 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 1000 up_read(&adev->reset_domain->sem); 1001 return -ETIME; 1002 } 1003 1004 amdgpu_ring_commit(ring); 1005 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 1006 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout); 1007 if (r < 1) { 1008 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 1009 up_read(&adev->reset_domain->sem); 1010 return -ETIME; 1011 } 1012 up_read(&adev->reset_domain->sem); 1013 return 0; 1014 } 1015 1016 for (vmid = 1; vmid < 16; vmid++) { 1017 1018 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 1019 &queried_pasid); 1020 if (ret && queried_pasid == pasid) { 1021 if (all_hub) { 1022 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) 1023 gmc_v9_0_flush_gpu_tlb(adev, vmid, 1024 i, flush_type); 1025 } else { 1026 gmc_v9_0_flush_gpu_tlb(adev, vmid, 1027 AMDGPU_GFXHUB(0), flush_type); 1028 } 1029 break; 1030 } 1031 } 1032 1033 return 0; 1034 1035 } 1036 1037 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 1038 unsigned int vmid, uint64_t pd_addr) 1039 { 1040 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 1041 struct amdgpu_device *adev = ring->adev; 1042 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 1043 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 1044 unsigned int eng = ring->vm_inv_eng; 1045 1046 /* 1047 * It may lose gpuvm invalidate acknowldege state across power-gating 1048 * off cycle, add semaphore acquire before invalidation and semaphore 1049 * release after invalidation to avoid entering power gated state 1050 * to WA the Issue 1051 */ 1052 1053 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1054 if (use_semaphore) 1055 /* a read return value of 1 means semaphore acuqire */ 1056 amdgpu_ring_emit_reg_wait(ring, 1057 hub->vm_inv_eng0_sem + 1058 hub->eng_distance * eng, 0x1, 0x1); 1059 1060 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1061 (hub->ctx_addr_distance * vmid), 1062 lower_32_bits(pd_addr)); 1063 1064 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1065 (hub->ctx_addr_distance * vmid), 1066 upper_32_bits(pd_addr)); 1067 1068 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 1069 hub->eng_distance * eng, 1070 hub->vm_inv_eng0_ack + 1071 hub->eng_distance * eng, 1072 req, 1 << vmid); 1073 1074 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1075 if (use_semaphore) 1076 /* 1077 * add semaphore release after invalidation, 1078 * write with 0 means semaphore release 1079 */ 1080 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1081 hub->eng_distance * eng, 0); 1082 1083 return pd_addr; 1084 } 1085 1086 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 1087 unsigned int pasid) 1088 { 1089 struct amdgpu_device *adev = ring->adev; 1090 uint32_t reg; 1091 1092 /* Do nothing because there's no lut register for mmhub1. */ 1093 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 1094 return; 1095 1096 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 1097 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1098 else 1099 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1100 1101 amdgpu_ring_emit_wreg(ring, reg, pasid); 1102 } 1103 1104 /* 1105 * PTE format on VEGA 10: 1106 * 63:59 reserved 1107 * 58:57 mtype 1108 * 56 F 1109 * 55 L 1110 * 54 P 1111 * 53 SW 1112 * 52 T 1113 * 50:48 reserved 1114 * 47:12 4k physical page base address 1115 * 11:7 fragment 1116 * 6 write 1117 * 5 read 1118 * 4 exe 1119 * 3 Z 1120 * 2 snooped 1121 * 1 system 1122 * 0 valid 1123 * 1124 * PDE format on VEGA 10: 1125 * 63:59 block fragment size 1126 * 58:55 reserved 1127 * 54 P 1128 * 53:48 reserved 1129 * 47:6 physical base address of PD or PTE 1130 * 5:3 reserved 1131 * 2 C 1132 * 1 system 1133 * 0 valid 1134 */ 1135 1136 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1137 1138 { 1139 switch (flags) { 1140 case AMDGPU_VM_MTYPE_DEFAULT: 1141 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1142 case AMDGPU_VM_MTYPE_NC: 1143 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1144 case AMDGPU_VM_MTYPE_WC: 1145 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC); 1146 case AMDGPU_VM_MTYPE_RW: 1147 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW); 1148 case AMDGPU_VM_MTYPE_CC: 1149 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC); 1150 case AMDGPU_VM_MTYPE_UC: 1151 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC); 1152 default: 1153 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC); 1154 } 1155 } 1156 1157 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1158 uint64_t *addr, uint64_t *flags) 1159 { 1160 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1161 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1162 BUG_ON(*addr & 0xFFFF00000000003FULL); 1163 1164 if (!adev->gmc.translate_further) 1165 return; 1166 1167 if (level == AMDGPU_VM_PDB1) { 1168 /* Set the block fragment size */ 1169 if (!(*flags & AMDGPU_PDE_PTE)) 1170 *flags |= AMDGPU_PDE_BFS(0x9); 1171 1172 } else if (level == AMDGPU_VM_PDB0) { 1173 if (*flags & AMDGPU_PDE_PTE) { 1174 *flags &= ~AMDGPU_PDE_PTE; 1175 if (!(*flags & AMDGPU_PTE_VALID)) 1176 *addr |= 1 << PAGE_SHIFT; 1177 } else { 1178 *flags |= AMDGPU_PTE_TF; 1179 } 1180 } 1181 } 1182 1183 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1184 struct amdgpu_bo *bo, 1185 struct amdgpu_bo_va_mapping *mapping, 1186 uint64_t *flags) 1187 { 1188 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1189 bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM; 1190 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | AMDGPU_GEM_CREATE_EXT_COHERENT); 1191 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; 1192 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1193 struct amdgpu_vm *vm = mapping->bo_va->base.vm; 1194 unsigned int mtype_local, mtype; 1195 bool snoop = false; 1196 bool is_local; 1197 1198 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1199 case IP_VERSION(9, 4, 1): 1200 case IP_VERSION(9, 4, 2): 1201 if (is_vram) { 1202 if (bo_adev == adev) { 1203 if (uncached) 1204 mtype = MTYPE_UC; 1205 else if (coherent) 1206 mtype = MTYPE_CC; 1207 else 1208 mtype = MTYPE_RW; 1209 /* FIXME: is this still needed? Or does 1210 * amdgpu_ttm_tt_pde_flags already handle this? 1211 */ 1212 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 1213 IP_VERSION(9, 4, 2) || 1214 amdgpu_ip_version(adev, GC_HWIP, 0) == 1215 IP_VERSION(9, 4, 3)) && 1216 adev->gmc.xgmi.connected_to_cpu) 1217 snoop = true; 1218 } else { 1219 if (uncached || coherent) 1220 mtype = MTYPE_UC; 1221 else 1222 mtype = MTYPE_NC; 1223 if (mapping->bo_va->is_xgmi) 1224 snoop = true; 1225 } 1226 } else { 1227 if (uncached || coherent) 1228 mtype = MTYPE_UC; 1229 else 1230 mtype = MTYPE_NC; 1231 /* FIXME: is this still needed? Or does 1232 * amdgpu_ttm_tt_pde_flags already handle this? 1233 */ 1234 snoop = true; 1235 } 1236 break; 1237 case IP_VERSION(9, 4, 3): 1238 /* Only local VRAM BOs or system memory on non-NUMA APUs 1239 * can be assumed to be local in their entirety. Choose 1240 * MTYPE_NC as safe fallback for all system memory BOs on 1241 * NUMA systems. Their MTYPE can be overridden per-page in 1242 * gmc_v9_0_override_vm_pte_flags. 1243 */ 1244 mtype_local = MTYPE_RW; 1245 if (amdgpu_mtype_local == 1) { 1246 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); 1247 mtype_local = MTYPE_NC; 1248 } else if (amdgpu_mtype_local == 2) { 1249 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n"); 1250 mtype_local = MTYPE_CC; 1251 } else { 1252 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); 1253 } 1254 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1255 num_possible_nodes() <= 1) || 1256 (is_vram && adev == bo_adev && 1257 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id); 1258 snoop = true; 1259 if (uncached) { 1260 mtype = MTYPE_UC; 1261 } else if (ext_coherent) { 1262 mtype = is_local ? MTYPE_CC : MTYPE_UC; 1263 } else if (adev->flags & AMD_IS_APU) { 1264 mtype = is_local ? mtype_local : MTYPE_NC; 1265 } else { 1266 /* dGPU */ 1267 if (is_local) 1268 mtype = mtype_local; 1269 else if (is_vram) 1270 mtype = MTYPE_NC; 1271 else 1272 mtype = MTYPE_UC; 1273 } 1274 1275 break; 1276 default: 1277 if (uncached || coherent) 1278 mtype = MTYPE_UC; 1279 else 1280 mtype = MTYPE_NC; 1281 1282 /* FIXME: is this still needed? Or does 1283 * amdgpu_ttm_tt_pde_flags already handle this? 1284 */ 1285 if (!is_vram) 1286 snoop = true; 1287 } 1288 1289 if (mtype != MTYPE_NC) 1290 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1291 AMDGPU_PTE_MTYPE_VG10(mtype); 1292 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1293 } 1294 1295 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1296 struct amdgpu_bo_va_mapping *mapping, 1297 uint64_t *flags) 1298 { 1299 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1300 1301 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1302 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1303 1304 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1305 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1306 1307 if (mapping->flags & AMDGPU_PTE_PRT) { 1308 *flags |= AMDGPU_PTE_PRT; 1309 *flags &= ~AMDGPU_PTE_VALID; 1310 } 1311 1312 if (bo && bo->tbo.resource) 1313 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo, 1314 mapping, flags); 1315 } 1316 1317 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1318 struct amdgpu_vm *vm, 1319 uint64_t addr, uint64_t *flags) 1320 { 1321 int local_node, nid; 1322 1323 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system 1324 * memory can use more efficient MTYPEs. 1325 */ 1326 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) 1327 return; 1328 1329 /* Only direct-mapped memory allows us to determine the NUMA node from 1330 * the DMA address. 1331 */ 1332 if (!adev->ram_is_direct_mapped) { 1333 dev_dbg(adev->dev, "RAM is not direct mapped\n"); 1334 return; 1335 } 1336 1337 /* Only override mappings with MTYPE_NC, which is the safe default for 1338 * cacheable memory. 1339 */ 1340 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1341 AMDGPU_PTE_MTYPE_VG10(MTYPE_NC)) { 1342 dev_dbg(adev->dev, "MTYPE is not NC\n"); 1343 return; 1344 } 1345 1346 /* FIXME: Only supported on native mode for now. For carve-out, the 1347 * NUMA affinity of the GPU/VM needs to come from the PCI info because 1348 * memory partitions are not associated with different NUMA nodes. 1349 */ 1350 if (adev->gmc.is_app_apu && vm->mem_id >= 0) { 1351 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1352 } else { 1353 dev_dbg(adev->dev, "Only native mode APU is supported.\n"); 1354 return; 1355 } 1356 1357 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1358 * page or NUMA nodes. 1359 */ 1360 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1361 dev_dbg(adev->dev, "Page is not RAM.\n"); 1362 return; 1363 } 1364 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1365 dev_dbg(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1366 vm->mem_id, local_node, nid); 1367 if (nid == local_node) { 1368 uint64_t old_flags = *flags; 1369 unsigned int mtype_local = MTYPE_RW; 1370 1371 if (amdgpu_mtype_local == 1) 1372 mtype_local = MTYPE_NC; 1373 else if (amdgpu_mtype_local == 2) 1374 mtype_local = MTYPE_CC; 1375 1376 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) | 1377 AMDGPU_PTE_MTYPE_VG10(mtype_local); 1378 dev_dbg(adev->dev, "flags updated from %llx to %llx\n", 1379 old_flags, *flags); 1380 } 1381 } 1382 1383 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1384 { 1385 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1386 unsigned int size; 1387 1388 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1389 1390 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1391 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1392 } else { 1393 u32 viewport; 1394 1395 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1396 case IP_VERSION(1, 0, 0): 1397 case IP_VERSION(1, 0, 1): 1398 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1399 size = (REG_GET_FIELD(viewport, 1400 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1401 REG_GET_FIELD(viewport, 1402 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1403 4); 1404 break; 1405 case IP_VERSION(2, 1, 0): 1406 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1407 size = (REG_GET_FIELD(viewport, 1408 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1409 REG_GET_FIELD(viewport, 1410 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1411 4); 1412 break; 1413 default: 1414 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1415 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1416 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1417 4); 1418 break; 1419 } 1420 } 1421 1422 return size; 1423 } 1424 1425 static enum amdgpu_memory_partition 1426 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes) 1427 { 1428 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE; 1429 1430 if (adev->nbio.funcs->get_memory_partition_mode) 1431 mode = adev->nbio.funcs->get_memory_partition_mode(adev, 1432 supp_modes); 1433 1434 return mode; 1435 } 1436 1437 static enum amdgpu_memory_partition 1438 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev) 1439 { 1440 if (amdgpu_sriov_vf(adev)) 1441 return AMDGPU_NPS1_PARTITION_MODE; 1442 1443 return gmc_v9_0_get_memory_partition(adev, NULL); 1444 } 1445 1446 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1447 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1448 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1449 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1450 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1451 .map_mtype = gmc_v9_0_map_mtype, 1452 .get_vm_pde = gmc_v9_0_get_vm_pde, 1453 .get_vm_pte = gmc_v9_0_get_vm_pte, 1454 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1455 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1456 .query_mem_partition_mode = &gmc_v9_0_query_memory_partition, 1457 }; 1458 1459 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1460 { 1461 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1462 } 1463 1464 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1465 { 1466 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1467 case IP_VERSION(6, 0, 0): 1468 adev->umc.funcs = &umc_v6_0_funcs; 1469 break; 1470 case IP_VERSION(6, 1, 1): 1471 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1472 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1473 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1474 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1475 adev->umc.retire_unit = 1; 1476 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1477 adev->umc.ras = &umc_v6_1_ras; 1478 break; 1479 case IP_VERSION(6, 1, 2): 1480 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1481 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1482 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1483 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1484 adev->umc.retire_unit = 1; 1485 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1486 adev->umc.ras = &umc_v6_1_ras; 1487 break; 1488 case IP_VERSION(6, 7, 0): 1489 adev->umc.max_ras_err_cnt_per_query = 1490 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1491 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1492 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1493 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1494 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1495 if (!adev->gmc.xgmi.connected_to_cpu) 1496 adev->umc.ras = &umc_v6_7_ras; 1497 if (1 & adev->smuio.funcs->get_die_id(adev)) 1498 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1499 else 1500 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1501 break; 1502 case IP_VERSION(12, 0, 0): 1503 adev->umc.max_ras_err_cnt_per_query = UMC_V12_0_TOTAL_CHANNEL_NUM(adev); 1504 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM; 1505 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM; 1506 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM; 1507 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET; 1508 adev->umc.active_mask = adev->aid_mask; 1509 adev->umc.channel_idx_tbl = &umc_v12_0_channel_idx_tbl[0][0][0]; 1510 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1511 adev->umc.ras = &umc_v12_0_ras; 1512 break; 1513 default: 1514 break; 1515 } 1516 } 1517 1518 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1519 { 1520 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1521 case IP_VERSION(9, 4, 1): 1522 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1523 break; 1524 case IP_VERSION(9, 4, 2): 1525 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1526 break; 1527 case IP_VERSION(1, 8, 0): 1528 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1529 break; 1530 default: 1531 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1532 break; 1533 } 1534 } 1535 1536 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1537 { 1538 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1539 case IP_VERSION(9, 4, 0): 1540 adev->mmhub.ras = &mmhub_v1_0_ras; 1541 break; 1542 case IP_VERSION(9, 4, 1): 1543 adev->mmhub.ras = &mmhub_v9_4_ras; 1544 break; 1545 case IP_VERSION(9, 4, 2): 1546 adev->mmhub.ras = &mmhub_v1_7_ras; 1547 break; 1548 case IP_VERSION(1, 8, 0): 1549 adev->mmhub.ras = &mmhub_v1_8_ras; 1550 break; 1551 default: 1552 /* mmhub ras is not available */ 1553 break; 1554 } 1555 } 1556 1557 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1558 { 1559 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 1560 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1561 else 1562 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1563 } 1564 1565 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1566 { 1567 adev->hdp.ras = &hdp_v4_0_ras; 1568 } 1569 1570 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1571 { 1572 struct amdgpu_mca *mca = &adev->mca; 1573 1574 /* is UMC the right IP to check for MCA? Maybe DF? */ 1575 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1576 case IP_VERSION(6, 7, 0): 1577 if (!adev->gmc.xgmi.connected_to_cpu) { 1578 mca->mp0.ras = &mca_v3_0_mp0_ras; 1579 mca->mp1.ras = &mca_v3_0_mp1_ras; 1580 mca->mpio.ras = &mca_v3_0_mpio_ras; 1581 } 1582 break; 1583 default: 1584 break; 1585 } 1586 } 1587 1588 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1589 { 1590 if (!adev->gmc.xgmi.connected_to_cpu) 1591 adev->gmc.xgmi.ras = &xgmi_ras; 1592 } 1593 1594 static int gmc_v9_0_early_init(void *handle) 1595 { 1596 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1597 1598 /* 1599 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1600 * in their IP discovery tables 1601 */ 1602 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) || 1603 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 1604 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 1605 adev->gmc.xgmi.supported = true; 1606 1607 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) { 1608 adev->gmc.xgmi.supported = true; 1609 adev->gmc.xgmi.connected_to_cpu = 1610 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1611 } 1612 1613 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 1614 enum amdgpu_pkg_type pkg_type = 1615 adev->smuio.funcs->get_pkg_type(adev); 1616 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1617 * and the APU, can be in used two possible modes: 1618 * - carveout mode 1619 * - native APU mode 1620 * "is_app_apu" can be used to identify the APU in the native 1621 * mode. 1622 */ 1623 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1624 !pci_resource_len(adev->pdev, 0)); 1625 } 1626 1627 gmc_v9_0_set_gmc_funcs(adev); 1628 gmc_v9_0_set_irq_funcs(adev); 1629 gmc_v9_0_set_umc_funcs(adev); 1630 gmc_v9_0_set_mmhub_funcs(adev); 1631 gmc_v9_0_set_mmhub_ras_funcs(adev); 1632 gmc_v9_0_set_gfxhub_funcs(adev); 1633 gmc_v9_0_set_hdp_ras_funcs(adev); 1634 gmc_v9_0_set_mca_ras_funcs(adev); 1635 gmc_v9_0_set_xgmi_ras_funcs(adev); 1636 1637 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1638 adev->gmc.shared_aperture_end = 1639 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1640 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1641 adev->gmc.private_aperture_end = 1642 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1643 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1644 1645 return 0; 1646 } 1647 1648 static int gmc_v9_0_late_init(void *handle) 1649 { 1650 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1651 int r; 1652 1653 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1654 if (r) 1655 return r; 1656 1657 /* 1658 * Workaround performance drop issue with VBIOS enables partial 1659 * writes, while disables HBM ECC for vega10. 1660 */ 1661 if (!amdgpu_sriov_vf(adev) && 1662 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) { 1663 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1664 if (adev->df.funcs && 1665 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1666 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1667 } 1668 } 1669 1670 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1671 if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops && 1672 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) 1673 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1674 1675 if (adev->hdp.ras && adev->hdp.ras->ras_block.hw_ops && 1676 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count) 1677 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1678 } 1679 1680 r = amdgpu_gmc_ras_late_init(adev); 1681 if (r) 1682 return r; 1683 1684 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1685 } 1686 1687 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1688 struct amdgpu_gmc *mc) 1689 { 1690 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1691 1692 /* add the xgmi offset of the physical node */ 1693 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1694 if (adev->gmc.xgmi.connected_to_cpu) { 1695 amdgpu_gmc_sysvm_location(adev, mc); 1696 } else { 1697 amdgpu_gmc_vram_location(adev, mc, base); 1698 amdgpu_gmc_gart_location(adev, mc); 1699 amdgpu_gmc_agp_location(adev, mc); 1700 } 1701 /* base offset of vram pages */ 1702 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1703 1704 /* XXX: add the xgmi offset of the physical node? */ 1705 adev->vm_manager.vram_base_offset += 1706 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1707 } 1708 1709 /** 1710 * gmc_v9_0_mc_init - initialize the memory controller driver params 1711 * 1712 * @adev: amdgpu_device pointer 1713 * 1714 * Look up the amount of vram, vram width, and decide how to place 1715 * vram and gart within the GPU's physical address space. 1716 * Returns 0 for success. 1717 */ 1718 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1719 { 1720 int r; 1721 1722 /* size in MB on si */ 1723 if (!adev->gmc.is_app_apu) { 1724 adev->gmc.mc_vram_size = 1725 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1726 } else { 1727 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1728 adev->gmc.mc_vram_size = 0; 1729 } 1730 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1731 1732 if (!(adev->flags & AMD_IS_APU) && 1733 !adev->gmc.xgmi.connected_to_cpu) { 1734 r = amdgpu_device_resize_fb_bar(adev); 1735 if (r) 1736 return r; 1737 } 1738 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1739 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1740 1741 #ifdef CONFIG_X86_64 1742 /* 1743 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1744 * interface can use VRAM through here as it appears system reserved 1745 * memory in host address space. 1746 * 1747 * For APUs, VRAM is just the stolen system memory and can be accessed 1748 * directly. 1749 * 1750 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1751 */ 1752 1753 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1754 if ((!amdgpu_sriov_vf(adev) && 1755 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1756 (adev->gmc.xgmi.supported && 1757 adev->gmc.xgmi.connected_to_cpu)) { 1758 adev->gmc.aper_base = 1759 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1760 adev->gmc.xgmi.physical_node_id * 1761 adev->gmc.xgmi.node_segment_size; 1762 adev->gmc.aper_size = adev->gmc.real_vram_size; 1763 } 1764 1765 #endif 1766 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1767 1768 /* set the gart size */ 1769 if (amdgpu_gart_size == -1) { 1770 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1771 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1772 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1773 case IP_VERSION(9, 4, 0): 1774 case IP_VERSION(9, 4, 1): 1775 case IP_VERSION(9, 4, 2): 1776 case IP_VERSION(9, 4, 3): 1777 default: 1778 adev->gmc.gart_size = 512ULL << 20; 1779 break; 1780 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1781 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1782 case IP_VERSION(9, 3, 0): 1783 adev->gmc.gart_size = 1024ULL << 20; 1784 break; 1785 } 1786 } else { 1787 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1788 } 1789 1790 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1791 1792 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1793 1794 return 0; 1795 } 1796 1797 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1798 { 1799 int r; 1800 1801 if (adev->gart.bo) { 1802 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1803 return 0; 1804 } 1805 1806 if (adev->gmc.xgmi.connected_to_cpu) { 1807 adev->gmc.vmid0_page_table_depth = 1; 1808 adev->gmc.vmid0_page_table_block_size = 12; 1809 } else { 1810 adev->gmc.vmid0_page_table_depth = 0; 1811 adev->gmc.vmid0_page_table_block_size = 0; 1812 } 1813 1814 /* Initialize common gart structure */ 1815 r = amdgpu_gart_init(adev); 1816 if (r) 1817 return r; 1818 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1819 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) | 1820 AMDGPU_PTE_EXECUTABLE; 1821 1822 if (!adev->gmc.real_vram_size) { 1823 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1824 r = amdgpu_gart_table_ram_alloc(adev); 1825 if (r) 1826 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1827 } else { 1828 r = amdgpu_gart_table_vram_alloc(adev); 1829 if (r) 1830 return r; 1831 1832 if (adev->gmc.xgmi.connected_to_cpu) 1833 r = amdgpu_gmc_pdb0_alloc(adev); 1834 } 1835 1836 return r; 1837 } 1838 1839 /** 1840 * gmc_v9_0_save_registers - saves regs 1841 * 1842 * @adev: amdgpu_device pointer 1843 * 1844 * This saves potential register values that should be 1845 * restored upon resume 1846 */ 1847 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1848 { 1849 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1850 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) 1851 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1852 } 1853 1854 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev) 1855 { 1856 enum amdgpu_memory_partition mode; 1857 u32 supp_modes; 1858 bool valid; 1859 1860 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes); 1861 1862 /* Mode detected by hardware not present in supported modes */ 1863 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && 1864 !(BIT(mode - 1) & supp_modes)) 1865 return false; 1866 1867 switch (mode) { 1868 case UNKNOWN_MEMORY_PARTITION_MODE: 1869 case AMDGPU_NPS1_PARTITION_MODE: 1870 valid = (adev->gmc.num_mem_partitions == 1); 1871 break; 1872 case AMDGPU_NPS2_PARTITION_MODE: 1873 valid = (adev->gmc.num_mem_partitions == 2); 1874 break; 1875 case AMDGPU_NPS4_PARTITION_MODE: 1876 valid = (adev->gmc.num_mem_partitions == 3 || 1877 adev->gmc.num_mem_partitions == 4); 1878 break; 1879 default: 1880 valid = false; 1881 } 1882 1883 return valid; 1884 } 1885 1886 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid) 1887 { 1888 int i; 1889 1890 /* Check if node with id 'nid' is present in 'node_ids' array */ 1891 for (i = 0; i < num_ids; ++i) 1892 if (node_ids[i] == nid) 1893 return true; 1894 1895 return false; 1896 } 1897 1898 static void 1899 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev, 1900 struct amdgpu_mem_partition_info *mem_ranges) 1901 { 1902 int num_ranges = 0, ret, mem_groups; 1903 struct amdgpu_numa_info numa_info; 1904 int node_ids[MAX_MEM_RANGES]; 1905 int num_xcc, xcc_id; 1906 uint32_t xcc_mask; 1907 1908 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1909 xcc_mask = (1U << num_xcc) - 1; 1910 mem_groups = hweight32(adev->aid_mask); 1911 1912 for_each_inst(xcc_id, xcc_mask) { 1913 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 1914 if (ret) 1915 continue; 1916 1917 if (numa_info.nid == NUMA_NO_NODE) { 1918 mem_ranges[0].size = numa_info.size; 1919 mem_ranges[0].numa.node = numa_info.nid; 1920 num_ranges = 1; 1921 break; 1922 } 1923 1924 if (gmc_v9_0_is_node_present(node_ids, num_ranges, 1925 numa_info.nid)) 1926 continue; 1927 1928 node_ids[num_ranges] = numa_info.nid; 1929 mem_ranges[num_ranges].numa.node = numa_info.nid; 1930 mem_ranges[num_ranges].size = numa_info.size; 1931 ++num_ranges; 1932 } 1933 1934 adev->gmc.num_mem_partitions = num_ranges; 1935 1936 /* If there is only partition, don't use entire size */ 1937 if (adev->gmc.num_mem_partitions == 1) { 1938 mem_ranges[0].size = mem_ranges[0].size * (mem_groups - 1); 1939 do_div(mem_ranges[0].size, mem_groups); 1940 } 1941 } 1942 1943 static void 1944 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, 1945 struct amdgpu_mem_partition_info *mem_ranges) 1946 { 1947 enum amdgpu_memory_partition mode; 1948 u32 start_addr = 0, size; 1949 int i; 1950 1951 mode = gmc_v9_0_query_memory_partition(adev); 1952 1953 switch (mode) { 1954 case UNKNOWN_MEMORY_PARTITION_MODE: 1955 case AMDGPU_NPS1_PARTITION_MODE: 1956 adev->gmc.num_mem_partitions = 1; 1957 break; 1958 case AMDGPU_NPS2_PARTITION_MODE: 1959 adev->gmc.num_mem_partitions = 2; 1960 break; 1961 case AMDGPU_NPS4_PARTITION_MODE: 1962 if (adev->flags & AMD_IS_APU) 1963 adev->gmc.num_mem_partitions = 3; 1964 else 1965 adev->gmc.num_mem_partitions = 4; 1966 break; 1967 default: 1968 adev->gmc.num_mem_partitions = 1; 1969 break; 1970 } 1971 1972 size = adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT; 1973 size /= adev->gmc.num_mem_partitions; 1974 1975 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 1976 mem_ranges[i].range.fpfn = start_addr; 1977 mem_ranges[i].size = ((u64)size << AMDGPU_GPU_PAGE_SHIFT); 1978 mem_ranges[i].range.lpfn = start_addr + size - 1; 1979 start_addr += size; 1980 } 1981 1982 /* Adjust the last one */ 1983 mem_ranges[adev->gmc.num_mem_partitions - 1].range.lpfn = 1984 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; 1985 mem_ranges[adev->gmc.num_mem_partitions - 1].size = 1986 adev->gmc.real_vram_size - 1987 ((u64)mem_ranges[adev->gmc.num_mem_partitions - 1].range.fpfn 1988 << AMDGPU_GPU_PAGE_SHIFT); 1989 } 1990 1991 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev) 1992 { 1993 bool valid; 1994 1995 adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES, 1996 sizeof(struct amdgpu_mem_partition_info), 1997 GFP_KERNEL); 1998 if (!adev->gmc.mem_partitions) 1999 return -ENOMEM; 2000 2001 /* TODO : Get the range from PSP/Discovery for dGPU */ 2002 if (adev->gmc.is_app_apu) 2003 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); 2004 else 2005 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 2006 2007 if (amdgpu_sriov_vf(adev)) 2008 valid = true; 2009 else 2010 valid = gmc_v9_0_validate_partition_info(adev); 2011 if (!valid) { 2012 /* TODO: handle invalid case */ 2013 dev_WARN(adev->dev, 2014 "Mem ranges not matching with hardware config"); 2015 } 2016 2017 return 0; 2018 } 2019 2020 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 2021 { 2022 static const u32 regBIF_BIOS_SCRATCH_4 = 0x50; 2023 u32 vram_info; 2024 2025 if (!amdgpu_sriov_vf(adev)) { 2026 vram_info = RREG32(regBIF_BIOS_SCRATCH_4); 2027 adev->gmc.vram_vendor = vram_info & 0xF; 2028 } 2029 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 2030 adev->gmc.vram_width = 128 * 64; 2031 } 2032 2033 static int gmc_v9_0_sw_init(void *handle) 2034 { 2035 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 2036 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2037 unsigned long inst_mask = adev->aid_mask; 2038 2039 adev->gfxhub.funcs->init(adev); 2040 2041 adev->mmhub.funcs->init(adev); 2042 2043 spin_lock_init(&adev->gmc.invalidate_lock); 2044 2045 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 2046 gmc_v9_4_3_init_vram_info(adev); 2047 } else if (!adev->bios) { 2048 if (adev->flags & AMD_IS_APU) { 2049 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 2050 adev->gmc.vram_width = 64 * 64; 2051 } else { 2052 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 2053 adev->gmc.vram_width = 128 * 64; 2054 } 2055 } else { 2056 r = amdgpu_atomfirmware_get_vram_info(adev, 2057 &vram_width, &vram_type, &vram_vendor); 2058 if (amdgpu_sriov_vf(adev)) 2059 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 2060 * and DF related registers is not readable, seems hardcord is the 2061 * only way to set the correct vram_width 2062 */ 2063 adev->gmc.vram_width = 2048; 2064 else if (amdgpu_emu_mode != 1) 2065 adev->gmc.vram_width = vram_width; 2066 2067 if (!adev->gmc.vram_width) { 2068 int chansize, numchan; 2069 2070 /* hbm memory channel size */ 2071 if (adev->flags & AMD_IS_APU) 2072 chansize = 64; 2073 else 2074 chansize = 128; 2075 if (adev->df.funcs && 2076 adev->df.funcs->get_hbm_channel_number) { 2077 numchan = adev->df.funcs->get_hbm_channel_number(adev); 2078 adev->gmc.vram_width = numchan * chansize; 2079 } 2080 } 2081 2082 adev->gmc.vram_type = vram_type; 2083 adev->gmc.vram_vendor = vram_vendor; 2084 } 2085 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2086 case IP_VERSION(9, 1, 0): 2087 case IP_VERSION(9, 2, 2): 2088 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2089 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2090 2091 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 2092 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2093 } else { 2094 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 2095 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 2096 adev->gmc.translate_further = 2097 adev->vm_manager.num_level > 1; 2098 } 2099 break; 2100 case IP_VERSION(9, 0, 1): 2101 case IP_VERSION(9, 2, 1): 2102 case IP_VERSION(9, 4, 0): 2103 case IP_VERSION(9, 3, 0): 2104 case IP_VERSION(9, 4, 2): 2105 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2106 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2107 2108 /* 2109 * To fulfill 4-level page support, 2110 * vm size is 256TB (48bit), maximum size of Vega10, 2111 * block size 512 (9bit) 2112 */ 2113 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */ 2114 if (amdgpu_sriov_vf(adev)) 2115 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47); 2116 else 2117 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2118 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 2119 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2120 break; 2121 case IP_VERSION(9, 4, 1): 2122 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2123 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2124 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 2125 2126 /* Keep the vm size same with Vega20 */ 2127 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2128 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2129 break; 2130 case IP_VERSION(9, 4, 3): 2131 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 2132 NUM_XCC(adev->gfx.xcc_mask)); 2133 2134 inst_mask <<= AMDGPU_MMHUB0(0); 2135 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 2136 2137 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2138 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2139 break; 2140 default: 2141 break; 2142 } 2143 2144 /* This interrupt is VMC page fault.*/ 2145 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 2146 &adev->gmc.vm_fault); 2147 if (r) 2148 return r; 2149 2150 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) { 2151 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 2152 &adev->gmc.vm_fault); 2153 if (r) 2154 return r; 2155 } 2156 2157 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 2158 &adev->gmc.vm_fault); 2159 2160 if (r) 2161 return r; 2162 2163 if (!amdgpu_sriov_vf(adev) && 2164 !adev->gmc.xgmi.connected_to_cpu && 2165 !adev->gmc.is_app_apu) { 2166 /* interrupt sent to DF. */ 2167 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 2168 &adev->gmc.ecc_irq); 2169 if (r) 2170 return r; 2171 } 2172 2173 /* Set the internal MC address mask 2174 * This is the max address of the GPU's 2175 * internal address space. 2176 */ 2177 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 2178 2179 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= 2180 IP_VERSION(9, 4, 2) ? 2181 48 : 2182 44; 2183 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 2184 if (r) { 2185 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 2186 return r; 2187 } 2188 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 2189 2190 r = gmc_v9_0_mc_init(adev); 2191 if (r) 2192 return r; 2193 2194 amdgpu_gmc_get_vbios_allocations(adev); 2195 2196 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 2197 r = gmc_v9_0_init_mem_ranges(adev); 2198 if (r) 2199 return r; 2200 } 2201 2202 /* Memory manager */ 2203 r = amdgpu_bo_init(adev); 2204 if (r) 2205 return r; 2206 2207 r = gmc_v9_0_gart_init(adev); 2208 if (r) 2209 return r; 2210 2211 /* 2212 * number of VMs 2213 * VMID 0 is reserved for System 2214 * amdgpu graphics/compute will use VMIDs 1..n-1 2215 * amdkfd will use VMIDs n..15 2216 * 2217 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2218 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2219 * for video processing. 2220 */ 2221 adev->vm_manager.first_kfd_vmid = 2222 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 2223 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 2224 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) ? 2225 3 : 2226 8; 2227 2228 amdgpu_vm_manager_init(adev); 2229 2230 gmc_v9_0_save_registers(adev); 2231 2232 r = amdgpu_gmc_ras_sw_init(adev); 2233 if (r) 2234 return r; 2235 2236 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 2237 amdgpu_gmc_sysfs_init(adev); 2238 2239 return 0; 2240 } 2241 2242 static int gmc_v9_0_sw_fini(void *handle) 2243 { 2244 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2245 2246 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) 2247 amdgpu_gmc_sysfs_fini(adev); 2248 adev->gmc.num_mem_partitions = 0; 2249 kfree(adev->gmc.mem_partitions); 2250 2251 amdgpu_gmc_ras_fini(adev); 2252 amdgpu_gem_force_release(adev); 2253 amdgpu_vm_manager_fini(adev); 2254 if (!adev->gmc.real_vram_size) { 2255 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2256 amdgpu_gart_table_ram_free(adev); 2257 } else { 2258 amdgpu_gart_table_vram_free(adev); 2259 } 2260 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2261 amdgpu_bo_fini(adev); 2262 2263 return 0; 2264 } 2265 2266 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2267 { 2268 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 2269 case IP_VERSION(9, 0, 0): 2270 if (amdgpu_sriov_vf(adev)) 2271 break; 2272 fallthrough; 2273 case IP_VERSION(9, 4, 0): 2274 soc15_program_register_sequence(adev, 2275 golden_settings_mmhub_1_0_0, 2276 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2277 soc15_program_register_sequence(adev, 2278 golden_settings_athub_1_0_0, 2279 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2280 break; 2281 case IP_VERSION(9, 1, 0): 2282 case IP_VERSION(9, 2, 0): 2283 /* TODO for renoir */ 2284 soc15_program_register_sequence(adev, 2285 golden_settings_athub_1_0_0, 2286 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2287 break; 2288 default: 2289 break; 2290 } 2291 } 2292 2293 /** 2294 * gmc_v9_0_restore_registers - restores regs 2295 * 2296 * @adev: amdgpu_device pointer 2297 * 2298 * This restores register values, saved at suspend. 2299 */ 2300 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2301 { 2302 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 2303 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) { 2304 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2305 WARN_ON(adev->gmc.sdpif_register != 2306 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2307 } 2308 } 2309 2310 /** 2311 * gmc_v9_0_gart_enable - gart enable 2312 * 2313 * @adev: amdgpu_device pointer 2314 */ 2315 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2316 { 2317 int r; 2318 2319 if (adev->gmc.xgmi.connected_to_cpu) 2320 amdgpu_gmc_init_pdb0(adev); 2321 2322 if (adev->gart.bo == NULL) { 2323 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2324 return -EINVAL; 2325 } 2326 2327 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2328 2329 if (!adev->in_s0ix) { 2330 r = adev->gfxhub.funcs->gart_enable(adev); 2331 if (r) 2332 return r; 2333 } 2334 2335 r = adev->mmhub.funcs->gart_enable(adev); 2336 if (r) 2337 return r; 2338 2339 DRM_INFO("PCIE GART of %uM enabled.\n", 2340 (unsigned int)(adev->gmc.gart_size >> 20)); 2341 if (adev->gmc.pdb0_bo) 2342 DRM_INFO("PDB0 located at 0x%016llX\n", 2343 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2344 DRM_INFO("PTB located at 0x%016llX\n", 2345 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2346 2347 return 0; 2348 } 2349 2350 static int gmc_v9_0_hw_init(void *handle) 2351 { 2352 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2353 bool value; 2354 int i, r; 2355 2356 /* The sequence of these two function calls matters.*/ 2357 gmc_v9_0_init_golden_registers(adev); 2358 2359 if (adev->mode_info.num_crtc) { 2360 /* Lockout access through VGA aperture*/ 2361 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2362 /* disable VGA render */ 2363 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2364 } 2365 2366 if (adev->mmhub.funcs->update_power_gating) 2367 adev->mmhub.funcs->update_power_gating(adev, true); 2368 2369 adev->hdp.funcs->init_registers(adev); 2370 2371 /* After HDP is initialized, flush HDP.*/ 2372 adev->hdp.funcs->flush_hdp(adev, NULL); 2373 2374 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2375 value = false; 2376 else 2377 value = true; 2378 2379 if (!amdgpu_sriov_vf(adev)) { 2380 if (!adev->in_s0ix) 2381 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2382 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2383 } 2384 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2385 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2386 continue; 2387 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2388 } 2389 2390 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2391 adev->umc.funcs->init_registers(adev); 2392 2393 r = gmc_v9_0_gart_enable(adev); 2394 if (r) 2395 return r; 2396 2397 if (amdgpu_emu_mode == 1) 2398 return amdgpu_gmc_vram_checking(adev); 2399 else 2400 return r; 2401 } 2402 2403 /** 2404 * gmc_v9_0_gart_disable - gart disable 2405 * 2406 * @adev: amdgpu_device pointer 2407 * 2408 * This disables all VM page table. 2409 */ 2410 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2411 { 2412 if (!adev->in_s0ix) 2413 adev->gfxhub.funcs->gart_disable(adev); 2414 adev->mmhub.funcs->gart_disable(adev); 2415 } 2416 2417 static int gmc_v9_0_hw_fini(void *handle) 2418 { 2419 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2420 2421 gmc_v9_0_gart_disable(adev); 2422 2423 if (amdgpu_sriov_vf(adev)) { 2424 /* full access mode, so don't touch any GMC register */ 2425 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2426 return 0; 2427 } 2428 2429 /* 2430 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2431 * a correct cached state for GMC. Otherwise, the "gate" again 2432 * operation on S3 resuming will fail due to wrong cached state. 2433 */ 2434 if (adev->mmhub.funcs->update_power_gating) 2435 adev->mmhub.funcs->update_power_gating(adev, false); 2436 2437 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2438 2439 return 0; 2440 } 2441 2442 static int gmc_v9_0_suspend(void *handle) 2443 { 2444 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2445 2446 return gmc_v9_0_hw_fini(adev); 2447 } 2448 2449 static int gmc_v9_0_resume(void *handle) 2450 { 2451 int r; 2452 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2453 2454 r = gmc_v9_0_hw_init(adev); 2455 if (r) 2456 return r; 2457 2458 amdgpu_vmid_reset_all(adev); 2459 2460 return 0; 2461 } 2462 2463 static bool gmc_v9_0_is_idle(void *handle) 2464 { 2465 /* MC is always ready in GMC v9.*/ 2466 return true; 2467 } 2468 2469 static int gmc_v9_0_wait_for_idle(void *handle) 2470 { 2471 /* There is no need to wait for MC idle in GMC v9.*/ 2472 return 0; 2473 } 2474 2475 static int gmc_v9_0_soft_reset(void *handle) 2476 { 2477 /* XXX for emulation.*/ 2478 return 0; 2479 } 2480 2481 static int gmc_v9_0_set_clockgating_state(void *handle, 2482 enum amd_clockgating_state state) 2483 { 2484 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2485 2486 adev->mmhub.funcs->set_clockgating(adev, state); 2487 2488 athub_v1_0_set_clockgating(adev, state); 2489 2490 return 0; 2491 } 2492 2493 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 2494 { 2495 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2496 2497 adev->mmhub.funcs->get_clockgating(adev, flags); 2498 2499 athub_v1_0_get_clockgating(adev, flags); 2500 } 2501 2502 static int gmc_v9_0_set_powergating_state(void *handle, 2503 enum amd_powergating_state state) 2504 { 2505 return 0; 2506 } 2507 2508 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2509 .name = "gmc_v9_0", 2510 .early_init = gmc_v9_0_early_init, 2511 .late_init = gmc_v9_0_late_init, 2512 .sw_init = gmc_v9_0_sw_init, 2513 .sw_fini = gmc_v9_0_sw_fini, 2514 .hw_init = gmc_v9_0_hw_init, 2515 .hw_fini = gmc_v9_0_hw_fini, 2516 .suspend = gmc_v9_0_suspend, 2517 .resume = gmc_v9_0_resume, 2518 .is_idle = gmc_v9_0_is_idle, 2519 .wait_for_idle = gmc_v9_0_wait_for_idle, 2520 .soft_reset = gmc_v9_0_soft_reset, 2521 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2522 .set_powergating_state = gmc_v9_0_set_powergating_state, 2523 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2524 }; 2525 2526 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = { 2527 .type = AMD_IP_BLOCK_TYPE_GMC, 2528 .major = 9, 2529 .minor = 0, 2530 .rev = 0, 2531 .funcs = &gmc_v9_0_ip_funcs, 2532 }; 2533