1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "umc_v12_0.h" 60 #include "hdp_v4_0.h" 61 #include "mca_v3_0.h" 62 63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 64 65 #include "amdgpu_ras.h" 66 #include "amdgpu_xgmi.h" 67 68 /* add these here since we already include dce12 headers and these are for DCN */ 69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 77 78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 80 81 #define MAX_MEM_RANGES 8 82 83 static const char * const gfxhub_client_ids[] = { 84 "CB", 85 "DB", 86 "IA", 87 "WD", 88 "CPF", 89 "CPC", 90 "CPG", 91 "RLC", 92 "TCP", 93 "SQC (inst)", 94 "SQC (data)", 95 "SQG", 96 "PA", 97 }; 98 99 static const char *mmhub_client_ids_raven[][2] = { 100 [0][0] = "MP1", 101 [1][0] = "MP0", 102 [2][0] = "VCN", 103 [3][0] = "VCNU", 104 [4][0] = "HDP", 105 [5][0] = "DCE", 106 [13][0] = "UTCL2", 107 [19][0] = "TLS", 108 [26][0] = "OSS", 109 [27][0] = "SDMA0", 110 [0][1] = "MP1", 111 [1][1] = "MP0", 112 [2][1] = "VCN", 113 [3][1] = "VCNU", 114 [4][1] = "HDP", 115 [5][1] = "XDP", 116 [6][1] = "DBGU0", 117 [7][1] = "DCE", 118 [8][1] = "DCEDWB0", 119 [9][1] = "DCEDWB1", 120 [26][1] = "OSS", 121 [27][1] = "SDMA0", 122 }; 123 124 static const char *mmhub_client_ids_renoir[][2] = { 125 [0][0] = "MP1", 126 [1][0] = "MP0", 127 [2][0] = "HDP", 128 [4][0] = "DCEDMC", 129 [5][0] = "DCEVGA", 130 [13][0] = "UTCL2", 131 [19][0] = "TLS", 132 [26][0] = "OSS", 133 [27][0] = "SDMA0", 134 [28][0] = "VCN", 135 [29][0] = "VCNU", 136 [30][0] = "JPEG", 137 [0][1] = "MP1", 138 [1][1] = "MP0", 139 [2][1] = "HDP", 140 [3][1] = "XDP", 141 [6][1] = "DBGU0", 142 [7][1] = "DCEDMC", 143 [8][1] = "DCEVGA", 144 [9][1] = "DCEDWB", 145 [26][1] = "OSS", 146 [27][1] = "SDMA0", 147 [28][1] = "VCN", 148 [29][1] = "VCNU", 149 [30][1] = "JPEG", 150 }; 151 152 static const char *mmhub_client_ids_vega10[][2] = { 153 [0][0] = "MP0", 154 [1][0] = "UVD", 155 [2][0] = "UVDU", 156 [3][0] = "HDP", 157 [13][0] = "UTCL2", 158 [14][0] = "OSS", 159 [15][0] = "SDMA1", 160 [32+0][0] = "VCE0", 161 [32+1][0] = "VCE0U", 162 [32+2][0] = "XDMA", 163 [32+3][0] = "DCE", 164 [32+4][0] = "MP1", 165 [32+14][0] = "SDMA0", 166 [0][1] = "MP0", 167 [1][1] = "UVD", 168 [2][1] = "UVDU", 169 [3][1] = "DBGU0", 170 [4][1] = "HDP", 171 [5][1] = "XDP", 172 [14][1] = "OSS", 173 [15][1] = "SDMA0", 174 [32+0][1] = "VCE0", 175 [32+1][1] = "VCE0U", 176 [32+2][1] = "XDMA", 177 [32+3][1] = "DCE", 178 [32+4][1] = "DCEDWB", 179 [32+5][1] = "MP1", 180 [32+6][1] = "DBGU1", 181 [32+14][1] = "SDMA1", 182 }; 183 184 static const char *mmhub_client_ids_vega12[][2] = { 185 [0][0] = "MP0", 186 [1][0] = "VCE0", 187 [2][0] = "VCE0U", 188 [3][0] = "HDP", 189 [13][0] = "UTCL2", 190 [14][0] = "OSS", 191 [15][0] = "SDMA1", 192 [32+0][0] = "DCE", 193 [32+1][0] = "XDMA", 194 [32+2][0] = "UVD", 195 [32+3][0] = "UVDU", 196 [32+4][0] = "MP1", 197 [32+15][0] = "SDMA0", 198 [0][1] = "MP0", 199 [1][1] = "VCE0", 200 [2][1] = "VCE0U", 201 [3][1] = "DBGU0", 202 [4][1] = "HDP", 203 [5][1] = "XDP", 204 [14][1] = "OSS", 205 [15][1] = "SDMA0", 206 [32+0][1] = "DCE", 207 [32+1][1] = "DCEDWB", 208 [32+2][1] = "XDMA", 209 [32+3][1] = "UVD", 210 [32+4][1] = "UVDU", 211 [32+5][1] = "MP1", 212 [32+6][1] = "DBGU1", 213 [32+15][1] = "SDMA1", 214 }; 215 216 static const char *mmhub_client_ids_vega20[][2] = { 217 [0][0] = "XDMA", 218 [1][0] = "DCE", 219 [2][0] = "VCE0", 220 [3][0] = "VCE0U", 221 [4][0] = "UVD", 222 [5][0] = "UVD1U", 223 [13][0] = "OSS", 224 [14][0] = "HDP", 225 [15][0] = "SDMA0", 226 [32+0][0] = "UVD", 227 [32+1][0] = "UVDU", 228 [32+2][0] = "MP1", 229 [32+3][0] = "MP0", 230 [32+12][0] = "UTCL2", 231 [32+14][0] = "SDMA1", 232 [0][1] = "XDMA", 233 [1][1] = "DCE", 234 [2][1] = "DCEDWB", 235 [3][1] = "VCE0", 236 [4][1] = "VCE0U", 237 [5][1] = "UVD1", 238 [6][1] = "UVD1U", 239 [7][1] = "DBGU0", 240 [8][1] = "XDP", 241 [13][1] = "OSS", 242 [14][1] = "HDP", 243 [15][1] = "SDMA0", 244 [32+0][1] = "UVD", 245 [32+1][1] = "UVDU", 246 [32+2][1] = "DBGU1", 247 [32+3][1] = "MP1", 248 [32+4][1] = "MP0", 249 [32+14][1] = "SDMA1", 250 }; 251 252 static const char *mmhub_client_ids_arcturus[][2] = { 253 [0][0] = "DBGU1", 254 [1][0] = "XDP", 255 [2][0] = "MP1", 256 [14][0] = "HDP", 257 [171][0] = "JPEG", 258 [172][0] = "VCN", 259 [173][0] = "VCNU", 260 [203][0] = "JPEG1", 261 [204][0] = "VCN1", 262 [205][0] = "VCN1U", 263 [256][0] = "SDMA0", 264 [257][0] = "SDMA1", 265 [258][0] = "SDMA2", 266 [259][0] = "SDMA3", 267 [260][0] = "SDMA4", 268 [261][0] = "SDMA5", 269 [262][0] = "SDMA6", 270 [263][0] = "SDMA7", 271 [384][0] = "OSS", 272 [0][1] = "DBGU1", 273 [1][1] = "XDP", 274 [2][1] = "MP1", 275 [14][1] = "HDP", 276 [171][1] = "JPEG", 277 [172][1] = "VCN", 278 [173][1] = "VCNU", 279 [203][1] = "JPEG1", 280 [204][1] = "VCN1", 281 [205][1] = "VCN1U", 282 [256][1] = "SDMA0", 283 [257][1] = "SDMA1", 284 [258][1] = "SDMA2", 285 [259][1] = "SDMA3", 286 [260][1] = "SDMA4", 287 [261][1] = "SDMA5", 288 [262][1] = "SDMA6", 289 [263][1] = "SDMA7", 290 [384][1] = "OSS", 291 }; 292 293 static const char *mmhub_client_ids_aldebaran[][2] = { 294 [2][0] = "MP1", 295 [3][0] = "MP0", 296 [32+1][0] = "DBGU_IO0", 297 [32+2][0] = "DBGU_IO2", 298 [32+4][0] = "MPIO", 299 [96+11][0] = "JPEG0", 300 [96+12][0] = "VCN0", 301 [96+13][0] = "VCNU0", 302 [128+11][0] = "JPEG1", 303 [128+12][0] = "VCN1", 304 [128+13][0] = "VCNU1", 305 [160+1][0] = "XDP", 306 [160+14][0] = "HDP", 307 [256+0][0] = "SDMA0", 308 [256+1][0] = "SDMA1", 309 [256+2][0] = "SDMA2", 310 [256+3][0] = "SDMA3", 311 [256+4][0] = "SDMA4", 312 [384+0][0] = "OSS", 313 [2][1] = "MP1", 314 [3][1] = "MP0", 315 [32+1][1] = "DBGU_IO0", 316 [32+2][1] = "DBGU_IO2", 317 [32+4][1] = "MPIO", 318 [96+11][1] = "JPEG0", 319 [96+12][1] = "VCN0", 320 [96+13][1] = "VCNU0", 321 [128+11][1] = "JPEG1", 322 [128+12][1] = "VCN1", 323 [128+13][1] = "VCNU1", 324 [160+1][1] = "XDP", 325 [160+14][1] = "HDP", 326 [256+0][1] = "SDMA0", 327 [256+1][1] = "SDMA1", 328 [256+2][1] = "SDMA2", 329 [256+3][1] = "SDMA3", 330 [256+4][1] = "SDMA4", 331 [384+0][1] = "OSS", 332 }; 333 334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { 335 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 336 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 337 }; 338 339 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { 340 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 341 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 342 }; 343 344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 345 (0x000143c0 + 0x00000000), 346 (0x000143c0 + 0x00000800), 347 (0x000143c0 + 0x00001000), 348 (0x000143c0 + 0x00001800), 349 (0x000543c0 + 0x00000000), 350 (0x000543c0 + 0x00000800), 351 (0x000543c0 + 0x00001000), 352 (0x000543c0 + 0x00001800), 353 (0x000943c0 + 0x00000000), 354 (0x000943c0 + 0x00000800), 355 (0x000943c0 + 0x00001000), 356 (0x000943c0 + 0x00001800), 357 (0x000d43c0 + 0x00000000), 358 (0x000d43c0 + 0x00000800), 359 (0x000d43c0 + 0x00001000), 360 (0x000d43c0 + 0x00001800), 361 (0x001143c0 + 0x00000000), 362 (0x001143c0 + 0x00000800), 363 (0x001143c0 + 0x00001000), 364 (0x001143c0 + 0x00001800), 365 (0x001543c0 + 0x00000000), 366 (0x001543c0 + 0x00000800), 367 (0x001543c0 + 0x00001000), 368 (0x001543c0 + 0x00001800), 369 (0x001943c0 + 0x00000000), 370 (0x001943c0 + 0x00000800), 371 (0x001943c0 + 0x00001000), 372 (0x001943c0 + 0x00001800), 373 (0x001d43c0 + 0x00000000), 374 (0x001d43c0 + 0x00000800), 375 (0x001d43c0 + 0x00001000), 376 (0x001d43c0 + 0x00001800), 377 }; 378 379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 380 (0x000143e0 + 0x00000000), 381 (0x000143e0 + 0x00000800), 382 (0x000143e0 + 0x00001000), 383 (0x000143e0 + 0x00001800), 384 (0x000543e0 + 0x00000000), 385 (0x000543e0 + 0x00000800), 386 (0x000543e0 + 0x00001000), 387 (0x000543e0 + 0x00001800), 388 (0x000943e0 + 0x00000000), 389 (0x000943e0 + 0x00000800), 390 (0x000943e0 + 0x00001000), 391 (0x000943e0 + 0x00001800), 392 (0x000d43e0 + 0x00000000), 393 (0x000d43e0 + 0x00000800), 394 (0x000d43e0 + 0x00001000), 395 (0x000d43e0 + 0x00001800), 396 (0x001143e0 + 0x00000000), 397 (0x001143e0 + 0x00000800), 398 (0x001143e0 + 0x00001000), 399 (0x001143e0 + 0x00001800), 400 (0x001543e0 + 0x00000000), 401 (0x001543e0 + 0x00000800), 402 (0x001543e0 + 0x00001000), 403 (0x001543e0 + 0x00001800), 404 (0x001943e0 + 0x00000000), 405 (0x001943e0 + 0x00000800), 406 (0x001943e0 + 0x00001000), 407 (0x001943e0 + 0x00001800), 408 (0x001d43e0 + 0x00000000), 409 (0x001d43e0 + 0x00000800), 410 (0x001d43e0 + 0x00001000), 411 (0x001d43e0 + 0x00001800), 412 }; 413 414 static inline bool gmc_v9_0_is_multi_chiplet(struct amdgpu_device *adev) 415 { 416 return !!adev->aid_mask; 417 } 418 419 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 420 struct amdgpu_irq_src *src, 421 unsigned int type, 422 enum amdgpu_interrupt_state state) 423 { 424 u32 bits, i, tmp, reg; 425 426 /* Devices newer then VEGA10/12 shall have these programming 427 * sequences performed by PSP BL 428 */ 429 if (adev->asic_type >= CHIP_VEGA20) 430 return 0; 431 432 bits = 0x7f; 433 434 switch (state) { 435 case AMDGPU_IRQ_STATE_DISABLE: 436 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 437 reg = ecc_umc_mcumc_ctrl_addrs[i]; 438 tmp = RREG32(reg); 439 tmp &= ~bits; 440 WREG32(reg, tmp); 441 } 442 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 443 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 444 tmp = RREG32(reg); 445 tmp &= ~bits; 446 WREG32(reg, tmp); 447 } 448 break; 449 case AMDGPU_IRQ_STATE_ENABLE: 450 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 451 reg = ecc_umc_mcumc_ctrl_addrs[i]; 452 tmp = RREG32(reg); 453 tmp |= bits; 454 WREG32(reg, tmp); 455 } 456 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 457 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 458 tmp = RREG32(reg); 459 tmp |= bits; 460 WREG32(reg, tmp); 461 } 462 break; 463 default: 464 break; 465 } 466 467 return 0; 468 } 469 470 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 471 struct amdgpu_irq_src *src, 472 unsigned int type, 473 enum amdgpu_interrupt_state state) 474 { 475 struct amdgpu_vmhub *hub; 476 u32 tmp, reg, bits, i, j; 477 478 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 479 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 480 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 481 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 482 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 483 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 484 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 485 486 switch (state) { 487 case AMDGPU_IRQ_STATE_DISABLE: 488 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 489 hub = &adev->vmhub[j]; 490 for (i = 0; i < 16; i++) { 491 reg = hub->vm_context0_cntl + i; 492 493 /* This works because this interrupt is only 494 * enabled at init/resume and disabled in 495 * fini/suspend, so the overall state doesn't 496 * change over the course of suspend/resume. 497 */ 498 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 499 continue; 500 501 if (j >= AMDGPU_MMHUB0(0)) 502 tmp = RREG32_SOC15_IP(MMHUB, reg); 503 else 504 tmp = RREG32_XCC(reg, j); 505 506 tmp &= ~bits; 507 508 if (j >= AMDGPU_MMHUB0(0)) 509 WREG32_SOC15_IP(MMHUB, reg, tmp); 510 else 511 WREG32_XCC(reg, tmp, j); 512 } 513 } 514 break; 515 case AMDGPU_IRQ_STATE_ENABLE: 516 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 517 hub = &adev->vmhub[j]; 518 for (i = 0; i < 16; i++) { 519 reg = hub->vm_context0_cntl + i; 520 521 /* This works because this interrupt is only 522 * enabled at init/resume and disabled in 523 * fini/suspend, so the overall state doesn't 524 * change over the course of suspend/resume. 525 */ 526 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 527 continue; 528 529 if (j >= AMDGPU_MMHUB0(0)) 530 tmp = RREG32_SOC15_IP(MMHUB, reg); 531 else 532 tmp = RREG32_XCC(reg, j); 533 534 tmp |= bits; 535 536 if (j >= AMDGPU_MMHUB0(0)) 537 WREG32_SOC15_IP(MMHUB, reg, tmp); 538 else 539 WREG32_XCC(reg, tmp, j); 540 } 541 } 542 break; 543 default: 544 break; 545 } 546 547 return 0; 548 } 549 550 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 551 struct amdgpu_irq_src *source, 552 struct amdgpu_iv_entry *entry) 553 { 554 bool retry_fault = !!(entry->src_data[1] & 0x80); 555 bool write_fault = !!(entry->src_data[1] & 0x20); 556 uint32_t status = 0, cid = 0, rw = 0, fed = 0; 557 struct amdgpu_task_info *task_info; 558 struct amdgpu_vmhub *hub; 559 const char *mmhub_cid; 560 const char *hub_name; 561 unsigned int vmhub; 562 u64 addr; 563 uint32_t cam_index = 0; 564 int ret, xcc_id = 0; 565 uint32_t node_id; 566 567 node_id = entry->node_id; 568 569 addr = (u64)entry->src_data[0] << 12; 570 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 571 572 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 573 hub_name = "mmhub0"; 574 vmhub = AMDGPU_MMHUB0(node_id / 4); 575 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 576 hub_name = "mmhub1"; 577 vmhub = AMDGPU_MMHUB1(0); 578 } else { 579 hub_name = "gfxhub0"; 580 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 581 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 582 node_id); 583 if (xcc_id < 0) 584 xcc_id = 0; 585 } 586 vmhub = xcc_id; 587 } 588 hub = &adev->vmhub[vmhub]; 589 590 if (retry_fault) { 591 if (adev->irq.retry_cam_enabled) { 592 /* Delegate it to a different ring if the hardware hasn't 593 * already done it. 594 */ 595 if (entry->ih == &adev->irq.ih) { 596 amdgpu_irq_delegate(adev, entry, 8); 597 return 1; 598 } 599 600 cam_index = entry->src_data[2] & 0x3ff; 601 602 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 603 addr, entry->timestamp, write_fault); 604 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 605 if (ret) 606 return 1; 607 } else { 608 /* Process it onyl if it's the first fault for this address */ 609 if (entry->ih != &adev->irq.ih_soft && 610 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 611 entry->timestamp)) 612 return 1; 613 614 /* Delegate it to a different ring if the hardware hasn't 615 * already done it. 616 */ 617 if (entry->ih == &adev->irq.ih) { 618 amdgpu_irq_delegate(adev, entry, 8); 619 return 1; 620 } 621 622 /* Try to handle the recoverable page faults by filling page 623 * tables 624 */ 625 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 626 addr, entry->timestamp, write_fault)) 627 return 1; 628 } 629 } 630 631 if (kgd2kfd_vmfault_fast_path(adev, entry, retry_fault)) 632 return 1; 633 634 if (!printk_ratelimit()) 635 return 0; 636 637 dev_err(adev->dev, 638 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name, 639 retry_fault ? "retry" : "no-retry", 640 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 641 642 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 643 if (task_info) { 644 amdgpu_vm_print_task_info(adev, task_info); 645 amdgpu_vm_put_task_info(task_info); 646 } 647 648 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 649 addr, entry->client_id, 650 soc15_ih_clientid_name[entry->client_id]); 651 652 if (gmc_v9_0_is_multi_chiplet(adev)) 653 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 654 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 655 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 656 657 if (amdgpu_sriov_vf(adev)) 658 return 0; 659 660 /* 661 * Issue a dummy read to wait for the status register to 662 * be updated to avoid reading an incorrect value due to 663 * the new fast GRBM interface. 664 */ 665 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 666 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 667 RREG32(hub->vm_l2_pro_fault_status); 668 669 status = RREG32(hub->vm_l2_pro_fault_status); 670 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 671 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 672 fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED); 673 674 /* for fed error, kfd will handle it, return directly */ 675 if (fed && amdgpu_ras_is_poison_mode_supported(adev) && 676 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2))) 677 return 0; 678 679 /* Only print L2 fault status if the status register could be read and 680 * contains useful information 681 */ 682 if (!status) 683 return 0; 684 685 if (!amdgpu_sriov_vf(adev)) 686 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 687 688 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub); 689 690 dev_err(adev->dev, 691 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 692 status); 693 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 694 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 695 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 696 gfxhub_client_ids[cid], 697 cid); 698 } else { 699 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 700 case IP_VERSION(9, 0, 0): 701 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 702 break; 703 case IP_VERSION(9, 3, 0): 704 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 705 break; 706 case IP_VERSION(9, 4, 0): 707 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 708 break; 709 case IP_VERSION(9, 4, 1): 710 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 711 break; 712 case IP_VERSION(9, 1, 0): 713 case IP_VERSION(9, 2, 0): 714 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 715 break; 716 case IP_VERSION(1, 5, 0): 717 case IP_VERSION(2, 4, 0): 718 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 719 break; 720 case IP_VERSION(1, 8, 0): 721 case IP_VERSION(9, 4, 2): 722 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 723 break; 724 default: 725 mmhub_cid = NULL; 726 break; 727 } 728 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 729 mmhub_cid ? mmhub_cid : "unknown", cid); 730 } 731 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 732 REG_GET_FIELD(status, 733 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 734 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 735 REG_GET_FIELD(status, 736 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 737 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 738 REG_GET_FIELD(status, 739 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 740 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 741 REG_GET_FIELD(status, 742 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 743 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 744 return 0; 745 } 746 747 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 748 .set = gmc_v9_0_vm_fault_interrupt_state, 749 .process = gmc_v9_0_process_interrupt, 750 }; 751 752 753 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 754 .set = gmc_v9_0_ecc_interrupt_state, 755 .process = amdgpu_umc_process_ecc_irq, 756 }; 757 758 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 759 { 760 adev->gmc.vm_fault.num_types = 1; 761 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 762 763 if (!amdgpu_sriov_vf(adev) && 764 !adev->gmc.xgmi.connected_to_cpu && 765 !adev->gmc.is_app_apu) { 766 adev->gmc.ecc_irq.num_types = 1; 767 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 768 } 769 } 770 771 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 772 uint32_t flush_type) 773 { 774 u32 req = 0; 775 776 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 777 PER_VMID_INVALIDATE_REQ, 1 << vmid); 778 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 779 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 780 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 781 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 782 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 783 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 784 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 785 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 786 787 return req; 788 } 789 790 /** 791 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 792 * 793 * @adev: amdgpu_device pointer 794 * @vmhub: vmhub type 795 * 796 */ 797 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 798 uint32_t vmhub) 799 { 800 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 801 gmc_v9_0_is_multi_chiplet(adev)) 802 return false; 803 804 return ((vmhub == AMDGPU_MMHUB0(0) || 805 vmhub == AMDGPU_MMHUB1(0)) && 806 (!amdgpu_sriov_vf(adev)) && 807 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 808 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 809 } 810 811 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 812 uint8_t vmid, uint16_t *p_pasid) 813 { 814 uint32_t value; 815 816 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 817 + vmid); 818 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 819 820 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 821 } 822 823 /* 824 * GART 825 * VMID 0 is the physical GPU addresses as used by the kernel. 826 * VMIDs 1-15 are used for userspace clients and are handled 827 * by the amdgpu vm/hsa code. 828 */ 829 830 /** 831 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 832 * 833 * @adev: amdgpu_device pointer 834 * @vmid: vm instance to flush 835 * @vmhub: which hub to flush 836 * @flush_type: the flush type 837 * 838 * Flush the TLB for the requested page table using certain type. 839 */ 840 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 841 uint32_t vmhub, uint32_t flush_type) 842 { 843 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 844 u32 j, inv_req, tmp, sem, req, ack, inst; 845 const unsigned int eng = 17; 846 struct amdgpu_vmhub *hub; 847 848 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 849 850 hub = &adev->vmhub[vmhub]; 851 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 852 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 853 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 854 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 855 856 if (vmhub >= AMDGPU_MMHUB0(0)) 857 inst = 0; 858 else 859 inst = vmhub; 860 861 /* This is necessary for SRIOV as well as for GFXOFF to function 862 * properly under bare metal 863 */ 864 if (adev->gfx.kiq[inst].ring.sched.ready && 865 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 866 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 867 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 868 869 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 870 1 << vmid, inst); 871 return; 872 } 873 874 /* This path is needed before KIQ/MES/GFXOFF are set up */ 875 spin_lock(&adev->gmc.invalidate_lock); 876 877 /* 878 * It may lose gpuvm invalidate acknowldege state across power-gating 879 * off cycle, add semaphore acquire before invalidation and semaphore 880 * release after invalidation to avoid entering power gated state 881 * to WA the Issue 882 */ 883 884 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 885 if (use_semaphore) { 886 for (j = 0; j < adev->usec_timeout; j++) { 887 /* a read return value of 1 means semaphore acquire */ 888 if (vmhub >= AMDGPU_MMHUB0(0)) 889 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst)); 890 else 891 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst)); 892 if (tmp & 0x1) 893 break; 894 udelay(1); 895 } 896 897 if (j >= adev->usec_timeout) 898 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 899 } 900 901 if (vmhub >= AMDGPU_MMHUB0(0)) 902 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst)); 903 else 904 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst)); 905 906 /* 907 * Issue a dummy read to wait for the ACK register to 908 * be cleared to avoid a false ACK due to the new fast 909 * GRBM interface. 910 */ 911 if ((vmhub == AMDGPU_GFXHUB(0)) && 912 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 913 RREG32_NO_KIQ(req); 914 915 for (j = 0; j < adev->usec_timeout; j++) { 916 if (vmhub >= AMDGPU_MMHUB0(0)) 917 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst)); 918 else 919 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst)); 920 if (tmp & (1 << vmid)) 921 break; 922 udelay(1); 923 } 924 925 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 926 if (use_semaphore) { 927 /* 928 * add semaphore release after invalidation, 929 * write with 0 means semaphore release 930 */ 931 if (vmhub >= AMDGPU_MMHUB0(0)) 932 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst)); 933 else 934 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst)); 935 } 936 937 spin_unlock(&adev->gmc.invalidate_lock); 938 939 if (j < adev->usec_timeout) 940 return; 941 942 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 943 } 944 945 /** 946 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 947 * 948 * @adev: amdgpu_device pointer 949 * @pasid: pasid to be flush 950 * @flush_type: the flush type 951 * @all_hub: flush all hubs 952 * @inst: is used to select which instance of KIQ to use for the invalidation 953 * 954 * Flush the TLB for the requested pasid. 955 */ 956 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 957 uint16_t pasid, uint32_t flush_type, 958 bool all_hub, uint32_t inst) 959 { 960 uint16_t queried; 961 int i, vmid; 962 963 for (vmid = 1; vmid < 16; vmid++) { 964 bool valid; 965 966 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 967 &queried); 968 if (!valid || queried != pasid) 969 continue; 970 971 if (all_hub) { 972 for_each_set_bit(i, adev->vmhubs_mask, 973 AMDGPU_MAX_VMHUBS) 974 gmc_v9_0_flush_gpu_tlb(adev, vmid, i, 975 flush_type); 976 } else { 977 gmc_v9_0_flush_gpu_tlb(adev, vmid, 978 AMDGPU_GFXHUB(0), 979 flush_type); 980 } 981 } 982 } 983 984 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 985 unsigned int vmid, uint64_t pd_addr) 986 { 987 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 988 struct amdgpu_device *adev = ring->adev; 989 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 990 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 991 unsigned int eng = ring->vm_inv_eng; 992 993 /* 994 * It may lose gpuvm invalidate acknowldege state across power-gating 995 * off cycle, add semaphore acquire before invalidation and semaphore 996 * release after invalidation to avoid entering power gated state 997 * to WA the Issue 998 */ 999 1000 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1001 if (use_semaphore) 1002 /* a read return value of 1 means semaphore acuqire */ 1003 amdgpu_ring_emit_reg_wait(ring, 1004 hub->vm_inv_eng0_sem + 1005 hub->eng_distance * eng, 0x1, 0x1); 1006 1007 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1008 (hub->ctx_addr_distance * vmid), 1009 lower_32_bits(pd_addr)); 1010 1011 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1012 (hub->ctx_addr_distance * vmid), 1013 upper_32_bits(pd_addr)); 1014 1015 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 1016 hub->eng_distance * eng, 1017 hub->vm_inv_eng0_ack + 1018 hub->eng_distance * eng, 1019 req, 1 << vmid); 1020 1021 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1022 if (use_semaphore) 1023 /* 1024 * add semaphore release after invalidation, 1025 * write with 0 means semaphore release 1026 */ 1027 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1028 hub->eng_distance * eng, 0); 1029 1030 return pd_addr; 1031 } 1032 1033 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 1034 unsigned int pasid) 1035 { 1036 struct amdgpu_device *adev = ring->adev; 1037 uint32_t reg; 1038 1039 /* Do nothing because there's no lut register for mmhub1. */ 1040 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 1041 return; 1042 1043 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 1044 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1045 else 1046 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1047 1048 amdgpu_ring_emit_wreg(ring, reg, pasid); 1049 } 1050 1051 /* 1052 * PTE format on VEGA 10: 1053 * 63:59 reserved 1054 * 58:57 mtype 1055 * 56 F 1056 * 55 L 1057 * 54 P 1058 * 53 SW 1059 * 52 T 1060 * 50:48 reserved 1061 * 47:12 4k physical page base address 1062 * 11:7 fragment 1063 * 6 write 1064 * 5 read 1065 * 4 exe 1066 * 3 Z 1067 * 2 snooped 1068 * 1 system 1069 * 0 valid 1070 * 1071 * PDE format on VEGA 10: 1072 * 63:59 block fragment size 1073 * 58:55 reserved 1074 * 54 P 1075 * 53:48 reserved 1076 * 47:6 physical base address of PD or PTE 1077 * 5:3 reserved 1078 * 2 C 1079 * 1 system 1080 * 0 valid 1081 */ 1082 1083 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1084 1085 { 1086 switch (flags) { 1087 case AMDGPU_VM_MTYPE_DEFAULT: 1088 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1089 case AMDGPU_VM_MTYPE_NC: 1090 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1091 case AMDGPU_VM_MTYPE_WC: 1092 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_WC); 1093 case AMDGPU_VM_MTYPE_RW: 1094 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_RW); 1095 case AMDGPU_VM_MTYPE_CC: 1096 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_CC); 1097 case AMDGPU_VM_MTYPE_UC: 1098 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC); 1099 default: 1100 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1101 } 1102 } 1103 1104 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1105 uint64_t *addr, uint64_t *flags) 1106 { 1107 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1108 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1109 BUG_ON(*addr & 0xFFFF00000000003FULL); 1110 1111 if (!adev->gmc.translate_further) 1112 return; 1113 1114 if (level == AMDGPU_VM_PDB1) { 1115 /* Set the block fragment size */ 1116 if (!(*flags & AMDGPU_PDE_PTE)) 1117 *flags |= AMDGPU_PDE_BFS(0x9); 1118 1119 } else if (level == AMDGPU_VM_PDB0) { 1120 if (*flags & AMDGPU_PDE_PTE) { 1121 *flags &= ~AMDGPU_PDE_PTE; 1122 if (!(*flags & AMDGPU_PTE_VALID)) 1123 *addr |= 1 << PAGE_SHIFT; 1124 } else { 1125 *flags |= AMDGPU_PTE_TF; 1126 } 1127 } 1128 } 1129 1130 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1131 struct amdgpu_bo *bo, 1132 struct amdgpu_bo_va_mapping *mapping, 1133 uint64_t *flags) 1134 { 1135 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1136 bool is_vram = bo->tbo.resource && 1137 bo->tbo.resource->mem_type == TTM_PL_VRAM; 1138 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 1139 AMDGPU_GEM_CREATE_EXT_COHERENT); 1140 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; 1141 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1142 struct amdgpu_vm *vm = mapping->bo_va->base.vm; 1143 unsigned int mtype_local, mtype; 1144 uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); 1145 bool snoop = false; 1146 bool is_local; 1147 1148 dma_resv_assert_held(bo->tbo.base.resv); 1149 1150 switch (gc_ip_version) { 1151 case IP_VERSION(9, 4, 1): 1152 case IP_VERSION(9, 4, 2): 1153 if (is_vram) { 1154 if (bo_adev == adev) { 1155 if (uncached) 1156 mtype = MTYPE_UC; 1157 else if (coherent) 1158 mtype = MTYPE_CC; 1159 else 1160 mtype = MTYPE_RW; 1161 /* FIXME: is this still needed? Or does 1162 * amdgpu_ttm_tt_pde_flags already handle this? 1163 */ 1164 if (gc_ip_version == IP_VERSION(9, 4, 2) && 1165 adev->gmc.xgmi.connected_to_cpu) 1166 snoop = true; 1167 } else { 1168 if (uncached || coherent) 1169 mtype = MTYPE_UC; 1170 else 1171 mtype = MTYPE_NC; 1172 if (mapping->bo_va->is_xgmi) 1173 snoop = true; 1174 } 1175 } else { 1176 if (uncached || coherent) 1177 mtype = MTYPE_UC; 1178 else 1179 mtype = MTYPE_NC; 1180 /* FIXME: is this still needed? Or does 1181 * amdgpu_ttm_tt_pde_flags already handle this? 1182 */ 1183 snoop = true; 1184 } 1185 break; 1186 case IP_VERSION(9, 4, 3): 1187 case IP_VERSION(9, 4, 4): 1188 case IP_VERSION(9, 5, 0): 1189 /* Only local VRAM BOs or system memory on non-NUMA APUs 1190 * can be assumed to be local in their entirety. Choose 1191 * MTYPE_NC as safe fallback for all system memory BOs on 1192 * NUMA systems. Their MTYPE can be overridden per-page in 1193 * gmc_v9_0_override_vm_pte_flags. 1194 */ 1195 mtype_local = MTYPE_RW; 1196 if (amdgpu_mtype_local == 1) { 1197 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); 1198 mtype_local = MTYPE_NC; 1199 } else if (amdgpu_mtype_local == 2) { 1200 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n"); 1201 mtype_local = MTYPE_CC; 1202 } else { 1203 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); 1204 } 1205 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1206 num_possible_nodes() <= 1) || 1207 (is_vram && adev == bo_adev && 1208 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id); 1209 snoop = true; 1210 if (uncached) { 1211 mtype = MTYPE_UC; 1212 } else if (ext_coherent) { 1213 mtype = is_local ? MTYPE_CC : MTYPE_UC; 1214 } else if (adev->flags & AMD_IS_APU) { 1215 mtype = is_local ? mtype_local : MTYPE_NC; 1216 } else { 1217 /* dGPU */ 1218 if (is_local) 1219 mtype = mtype_local; 1220 else if (gc_ip_version < IP_VERSION(9, 5, 0) && !is_vram) 1221 mtype = MTYPE_UC; 1222 else 1223 mtype = MTYPE_NC; 1224 } 1225 1226 break; 1227 default: 1228 if (uncached || coherent) 1229 mtype = MTYPE_UC; 1230 else 1231 mtype = MTYPE_NC; 1232 1233 /* FIXME: is this still needed? Or does 1234 * amdgpu_ttm_tt_pde_flags already handle this? 1235 */ 1236 if (!is_vram) 1237 snoop = true; 1238 } 1239 1240 if (mtype != MTYPE_NC) 1241 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype); 1242 1243 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1244 } 1245 1246 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1247 struct amdgpu_bo_va_mapping *mapping, 1248 uint64_t *flags) 1249 { 1250 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1251 1252 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1253 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1254 1255 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1256 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1257 1258 if (mapping->flags & AMDGPU_PTE_PRT) { 1259 *flags |= AMDGPU_PTE_PRT; 1260 *flags &= ~AMDGPU_PTE_VALID; 1261 } 1262 1263 if ((*flags & AMDGPU_PTE_VALID) && bo) 1264 gmc_v9_0_get_coherence_flags(adev, bo, mapping, flags); 1265 } 1266 1267 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1268 struct amdgpu_vm *vm, 1269 uint64_t addr, uint64_t *flags) 1270 { 1271 int local_node, nid; 1272 1273 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system 1274 * memory can use more efficient MTYPEs. 1275 */ 1276 if (!(adev->flags & AMD_IS_APU) || 1277 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) 1278 return; 1279 1280 /* Only direct-mapped memory allows us to determine the NUMA node from 1281 * the DMA address. 1282 */ 1283 if (!adev->ram_is_direct_mapped) { 1284 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n"); 1285 return; 1286 } 1287 1288 /* MTYPE_NC is the same default and can be overridden. 1289 * MTYPE_UC will be present if the memory is extended-coherent 1290 * and can also be overridden. 1291 */ 1292 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1293 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC) && 1294 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1295 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC)) { 1296 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n"); 1297 return; 1298 } 1299 1300 /* FIXME: Only supported on native mode for now. For carve-out, the 1301 * NUMA affinity of the GPU/VM needs to come from the PCI info because 1302 * memory partitions are not associated with different NUMA nodes. 1303 */ 1304 if (adev->gmc.is_app_apu && vm->mem_id >= 0) { 1305 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1306 } else { 1307 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n"); 1308 return; 1309 } 1310 1311 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1312 * page or NUMA nodes. 1313 */ 1314 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1315 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n"); 1316 return; 1317 } 1318 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1319 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1320 vm->mem_id, local_node, nid); 1321 if (nid == local_node) { 1322 uint64_t old_flags = *flags; 1323 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) == 1324 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC)) { 1325 unsigned int mtype_local = MTYPE_RW; 1326 1327 if (amdgpu_mtype_local == 1) 1328 mtype_local = MTYPE_NC; 1329 else if (amdgpu_mtype_local == 2) 1330 mtype_local = MTYPE_CC; 1331 1332 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype_local); 1333 } else { 1334 /* MTYPE_UC case */ 1335 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC); 1336 } 1337 1338 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n", 1339 old_flags, *flags); 1340 } 1341 } 1342 1343 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1344 { 1345 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1346 unsigned int size; 1347 1348 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1349 1350 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1351 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1352 } else { 1353 u32 viewport; 1354 1355 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1356 case IP_VERSION(1, 0, 0): 1357 case IP_VERSION(1, 0, 1): 1358 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1359 size = (REG_GET_FIELD(viewport, 1360 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1361 REG_GET_FIELD(viewport, 1362 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1363 4); 1364 break; 1365 case IP_VERSION(2, 1, 0): 1366 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1367 size = (REG_GET_FIELD(viewport, 1368 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1369 REG_GET_FIELD(viewport, 1370 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1371 4); 1372 break; 1373 default: 1374 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1375 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1376 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1377 4); 1378 break; 1379 } 1380 } 1381 1382 return size; 1383 } 1384 1385 static enum amdgpu_memory_partition 1386 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes) 1387 { 1388 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE; 1389 1390 if (adev->nbio.funcs->get_memory_partition_mode) 1391 mode = adev->nbio.funcs->get_memory_partition_mode(adev, 1392 supp_modes); 1393 1394 return mode; 1395 } 1396 1397 static enum amdgpu_memory_partition 1398 gmc_v9_0_query_vf_memory_partition(struct amdgpu_device *adev) 1399 { 1400 switch (adev->gmc.num_mem_partitions) { 1401 case 0: 1402 return UNKNOWN_MEMORY_PARTITION_MODE; 1403 case 1: 1404 return AMDGPU_NPS1_PARTITION_MODE; 1405 case 2: 1406 return AMDGPU_NPS2_PARTITION_MODE; 1407 case 4: 1408 return AMDGPU_NPS4_PARTITION_MODE; 1409 default: 1410 return AMDGPU_NPS1_PARTITION_MODE; 1411 } 1412 1413 return AMDGPU_NPS1_PARTITION_MODE; 1414 } 1415 1416 static enum amdgpu_memory_partition 1417 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev) 1418 { 1419 if (amdgpu_sriov_vf(adev)) 1420 return gmc_v9_0_query_vf_memory_partition(adev); 1421 1422 return gmc_v9_0_get_memory_partition(adev, NULL); 1423 } 1424 1425 static bool gmc_v9_0_need_reset_on_init(struct amdgpu_device *adev) 1426 { 1427 if (adev->nbio.funcs && adev->nbio.funcs->is_nps_switch_requested && 1428 adev->nbio.funcs->is_nps_switch_requested(adev)) { 1429 adev->gmc.reset_flags |= AMDGPU_GMC_INIT_RESET_NPS; 1430 return true; 1431 } 1432 1433 return false; 1434 } 1435 1436 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1437 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1438 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1439 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1440 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1441 .map_mtype = gmc_v9_0_map_mtype, 1442 .get_vm_pde = gmc_v9_0_get_vm_pde, 1443 .get_vm_pte = gmc_v9_0_get_vm_pte, 1444 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1445 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1446 .query_mem_partition_mode = &gmc_v9_0_query_memory_partition, 1447 .request_mem_partition_mode = &amdgpu_gmc_request_memory_partition, 1448 .need_reset_on_init = &gmc_v9_0_need_reset_on_init, 1449 }; 1450 1451 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1452 { 1453 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1454 } 1455 1456 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1457 { 1458 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1459 case IP_VERSION(6, 0, 0): 1460 adev->umc.funcs = &umc_v6_0_funcs; 1461 break; 1462 case IP_VERSION(6, 1, 1): 1463 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1464 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1465 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1466 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1467 adev->umc.retire_unit = 1; 1468 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1469 adev->umc.ras = &umc_v6_1_ras; 1470 break; 1471 case IP_VERSION(6, 1, 2): 1472 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1473 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1474 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1475 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1476 adev->umc.retire_unit = 1; 1477 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1478 adev->umc.ras = &umc_v6_1_ras; 1479 break; 1480 case IP_VERSION(6, 7, 0): 1481 adev->umc.max_ras_err_cnt_per_query = 1482 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1483 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1484 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1485 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1486 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1487 if (!adev->gmc.xgmi.connected_to_cpu) 1488 adev->umc.ras = &umc_v6_7_ras; 1489 if (1 & adev->smuio.funcs->get_die_id(adev)) 1490 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1491 else 1492 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1493 break; 1494 case IP_VERSION(12, 0, 0): 1495 case IP_VERSION(12, 5, 0): 1496 adev->umc.max_ras_err_cnt_per_query = 1497 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1498 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM; 1499 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM; 1500 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM; 1501 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET; 1502 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1503 adev->umc.ras = &umc_v12_0_ras; 1504 break; 1505 default: 1506 break; 1507 } 1508 } 1509 1510 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1511 { 1512 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1513 case IP_VERSION(9, 4, 1): 1514 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1515 break; 1516 case IP_VERSION(9, 4, 2): 1517 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1518 break; 1519 case IP_VERSION(1, 8, 0): 1520 case IP_VERSION(1, 8, 1): 1521 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1522 break; 1523 default: 1524 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1525 break; 1526 } 1527 } 1528 1529 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1530 { 1531 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1532 case IP_VERSION(9, 4, 0): 1533 adev->mmhub.ras = &mmhub_v1_0_ras; 1534 break; 1535 case IP_VERSION(9, 4, 1): 1536 adev->mmhub.ras = &mmhub_v9_4_ras; 1537 break; 1538 case IP_VERSION(9, 4, 2): 1539 adev->mmhub.ras = &mmhub_v1_7_ras; 1540 break; 1541 case IP_VERSION(1, 8, 0): 1542 case IP_VERSION(1, 8, 1): 1543 adev->mmhub.ras = &mmhub_v1_8_ras; 1544 break; 1545 default: 1546 /* mmhub ras is not available */ 1547 break; 1548 } 1549 } 1550 1551 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1552 { 1553 if (gmc_v9_0_is_multi_chiplet(adev)) 1554 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1555 else 1556 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1557 } 1558 1559 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1560 { 1561 adev->hdp.ras = &hdp_v4_0_ras; 1562 } 1563 1564 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1565 { 1566 struct amdgpu_mca *mca = &adev->mca; 1567 1568 /* is UMC the right IP to check for MCA? Maybe DF? */ 1569 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1570 case IP_VERSION(6, 7, 0): 1571 if (!adev->gmc.xgmi.connected_to_cpu) { 1572 mca->mp0.ras = &mca_v3_0_mp0_ras; 1573 mca->mp1.ras = &mca_v3_0_mp1_ras; 1574 mca->mpio.ras = &mca_v3_0_mpio_ras; 1575 } 1576 break; 1577 default: 1578 break; 1579 } 1580 } 1581 1582 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1583 { 1584 if (!adev->gmc.xgmi.connected_to_cpu) 1585 adev->gmc.xgmi.ras = &xgmi_ras; 1586 } 1587 1588 static void gmc_v9_0_init_nps_details(struct amdgpu_device *adev) 1589 { 1590 enum amdgpu_memory_partition mode; 1591 uint32_t supp_modes; 1592 int i; 1593 1594 adev->gmc.supported_nps_modes = 0; 1595 1596 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) 1597 return; 1598 1599 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes); 1600 1601 /* Mode detected by hardware and supported modes available */ 1602 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && supp_modes) { 1603 while ((i = ffs(supp_modes))) { 1604 if (AMDGPU_ALL_NPS_MASK & BIT(i)) 1605 adev->gmc.supported_nps_modes |= BIT(i); 1606 supp_modes &= supp_modes - 1; 1607 } 1608 } else { 1609 /*TODO: Check PSP version also which supports NPS switch. Otherwise keep 1610 * supported modes as 0. 1611 */ 1612 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1613 case IP_VERSION(9, 4, 3): 1614 case IP_VERSION(9, 4, 4): 1615 adev->gmc.supported_nps_modes = 1616 BIT(AMDGPU_NPS1_PARTITION_MODE) | 1617 BIT(AMDGPU_NPS4_PARTITION_MODE); 1618 break; 1619 default: 1620 break; 1621 } 1622 } 1623 } 1624 1625 static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block) 1626 { 1627 struct amdgpu_device *adev = ip_block->adev; 1628 1629 /* 1630 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1631 * in their IP discovery tables 1632 */ 1633 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) || 1634 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 1635 gmc_v9_0_is_multi_chiplet(adev)) 1636 adev->gmc.xgmi.supported = true; 1637 1638 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) { 1639 adev->gmc.xgmi.supported = true; 1640 adev->gmc.xgmi.connected_to_cpu = 1641 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1642 } 1643 1644 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { 1645 enum amdgpu_pkg_type pkg_type = 1646 adev->smuio.funcs->get_pkg_type(adev); 1647 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1648 * and the APU, can be in used two possible modes: 1649 * - carveout mode 1650 * - native APU mode 1651 * "is_app_apu" can be used to identify the APU in the native 1652 * mode. 1653 */ 1654 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1655 !pci_resource_len(adev->pdev, 0)); 1656 } 1657 1658 gmc_v9_0_set_gmc_funcs(adev); 1659 gmc_v9_0_set_irq_funcs(adev); 1660 gmc_v9_0_set_umc_funcs(adev); 1661 gmc_v9_0_set_mmhub_funcs(adev); 1662 gmc_v9_0_set_mmhub_ras_funcs(adev); 1663 gmc_v9_0_set_gfxhub_funcs(adev); 1664 gmc_v9_0_set_hdp_ras_funcs(adev); 1665 gmc_v9_0_set_mca_ras_funcs(adev); 1666 gmc_v9_0_set_xgmi_ras_funcs(adev); 1667 1668 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1669 adev->gmc.shared_aperture_end = 1670 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1671 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1672 adev->gmc.private_aperture_end = 1673 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1674 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1675 1676 return 0; 1677 } 1678 1679 static int gmc_v9_0_late_init(struct amdgpu_ip_block *ip_block) 1680 { 1681 struct amdgpu_device *adev = ip_block->adev; 1682 int r; 1683 1684 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1685 if (r) 1686 return r; 1687 1688 /* 1689 * Workaround performance drop issue with VBIOS enables partial 1690 * writes, while disables HBM ECC for vega10. 1691 */ 1692 if (!amdgpu_sriov_vf(adev) && 1693 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) { 1694 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1695 if (adev->df.funcs && 1696 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1697 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1698 } 1699 } 1700 1701 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1702 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB); 1703 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP); 1704 } 1705 1706 r = amdgpu_gmc_ras_late_init(adev); 1707 if (r) 1708 return r; 1709 1710 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1711 } 1712 1713 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1714 struct amdgpu_gmc *mc) 1715 { 1716 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1717 1718 amdgpu_gmc_set_agp_default(adev, mc); 1719 1720 /* add the xgmi offset of the physical node */ 1721 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1722 if (adev->gmc.xgmi.connected_to_cpu) { 1723 amdgpu_gmc_sysvm_location(adev, mc); 1724 } else { 1725 amdgpu_gmc_vram_location(adev, mc, base); 1726 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 1727 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 1728 amdgpu_gmc_agp_location(adev, mc); 1729 } 1730 /* base offset of vram pages */ 1731 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1732 1733 /* XXX: add the xgmi offset of the physical node? */ 1734 adev->vm_manager.vram_base_offset += 1735 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1736 } 1737 1738 /** 1739 * gmc_v9_0_mc_init - initialize the memory controller driver params 1740 * 1741 * @adev: amdgpu_device pointer 1742 * 1743 * Look up the amount of vram, vram width, and decide how to place 1744 * vram and gart within the GPU's physical address space. 1745 * Returns 0 for success. 1746 */ 1747 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1748 { 1749 int r; 1750 1751 /* size in MB on si */ 1752 if (!adev->gmc.is_app_apu) { 1753 adev->gmc.mc_vram_size = 1754 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1755 } else { 1756 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1757 adev->gmc.mc_vram_size = 0; 1758 } 1759 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1760 1761 if (!(adev->flags & AMD_IS_APU) && 1762 !adev->gmc.xgmi.connected_to_cpu) { 1763 r = amdgpu_device_resize_fb_bar(adev); 1764 if (r) 1765 return r; 1766 } 1767 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1768 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1769 1770 #ifdef CONFIG_X86_64 1771 /* 1772 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1773 * interface can use VRAM through here as it appears system reserved 1774 * memory in host address space. 1775 * 1776 * For APUs, VRAM is just the stolen system memory and can be accessed 1777 * directly. 1778 * 1779 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1780 */ 1781 1782 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1783 if ((!amdgpu_sriov_vf(adev) && 1784 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1785 (adev->gmc.xgmi.supported && 1786 adev->gmc.xgmi.connected_to_cpu)) { 1787 adev->gmc.aper_base = 1788 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1789 adev->gmc.xgmi.physical_node_id * 1790 adev->gmc.xgmi.node_segment_size; 1791 adev->gmc.aper_size = adev->gmc.real_vram_size; 1792 } 1793 1794 #endif 1795 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1796 1797 /* set the gart size */ 1798 if (amdgpu_gart_size == -1) { 1799 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1800 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1801 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1802 case IP_VERSION(9, 4, 0): 1803 case IP_VERSION(9, 4, 1): 1804 case IP_VERSION(9, 4, 2): 1805 case IP_VERSION(9, 4, 3): 1806 case IP_VERSION(9, 4, 4): 1807 case IP_VERSION(9, 5, 0): 1808 default: 1809 adev->gmc.gart_size = 512ULL << 20; 1810 break; 1811 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1812 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1813 case IP_VERSION(9, 3, 0): 1814 adev->gmc.gart_size = 1024ULL << 20; 1815 break; 1816 } 1817 } else { 1818 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1819 } 1820 1821 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1822 1823 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1824 1825 return 0; 1826 } 1827 1828 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1829 { 1830 int r; 1831 1832 if (adev->gart.bo) { 1833 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1834 return 0; 1835 } 1836 1837 if (adev->gmc.xgmi.connected_to_cpu) { 1838 adev->gmc.vmid0_page_table_depth = 1; 1839 adev->gmc.vmid0_page_table_block_size = 12; 1840 } else { 1841 adev->gmc.vmid0_page_table_depth = 0; 1842 adev->gmc.vmid0_page_table_block_size = 0; 1843 } 1844 1845 /* Initialize common gart structure */ 1846 r = amdgpu_gart_init(adev); 1847 if (r) 1848 return r; 1849 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1850 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC) | 1851 AMDGPU_PTE_EXECUTABLE; 1852 1853 if (!adev->gmc.real_vram_size) { 1854 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1855 r = amdgpu_gart_table_ram_alloc(adev); 1856 if (r) 1857 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1858 } else { 1859 r = amdgpu_gart_table_vram_alloc(adev); 1860 if (r) 1861 return r; 1862 1863 if (adev->gmc.xgmi.connected_to_cpu) 1864 r = amdgpu_gmc_pdb0_alloc(adev); 1865 } 1866 1867 return r; 1868 } 1869 1870 /** 1871 * gmc_v9_0_save_registers - saves regs 1872 * 1873 * @adev: amdgpu_device pointer 1874 * 1875 * This saves potential register values that should be 1876 * restored upon resume 1877 */ 1878 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1879 { 1880 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1881 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) 1882 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1883 } 1884 1885 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev) 1886 { 1887 enum amdgpu_memory_partition mode; 1888 u32 supp_modes; 1889 bool valid; 1890 1891 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes); 1892 1893 /* Mode detected by hardware not present in supported modes */ 1894 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && 1895 !(BIT(mode - 1) & supp_modes)) 1896 return false; 1897 1898 switch (mode) { 1899 case UNKNOWN_MEMORY_PARTITION_MODE: 1900 case AMDGPU_NPS1_PARTITION_MODE: 1901 valid = (adev->gmc.num_mem_partitions == 1); 1902 break; 1903 case AMDGPU_NPS2_PARTITION_MODE: 1904 valid = (adev->gmc.num_mem_partitions == 2); 1905 break; 1906 case AMDGPU_NPS4_PARTITION_MODE: 1907 valid = (adev->gmc.num_mem_partitions == 3 || 1908 adev->gmc.num_mem_partitions == 4); 1909 break; 1910 default: 1911 valid = false; 1912 } 1913 1914 return valid; 1915 } 1916 1917 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid) 1918 { 1919 int i; 1920 1921 /* Check if node with id 'nid' is present in 'node_ids' array */ 1922 for (i = 0; i < num_ids; ++i) 1923 if (node_ids[i] == nid) 1924 return true; 1925 1926 return false; 1927 } 1928 1929 static void 1930 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev, 1931 struct amdgpu_mem_partition_info *mem_ranges) 1932 { 1933 struct amdgpu_numa_info numa_info; 1934 int node_ids[MAX_MEM_RANGES]; 1935 int num_ranges = 0, ret; 1936 int num_xcc, xcc_id; 1937 uint32_t xcc_mask; 1938 1939 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1940 xcc_mask = (1U << num_xcc) - 1; 1941 1942 for_each_inst(xcc_id, xcc_mask) { 1943 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 1944 if (ret) 1945 continue; 1946 1947 if (numa_info.nid == NUMA_NO_NODE) { 1948 mem_ranges[0].size = numa_info.size; 1949 mem_ranges[0].numa.node = numa_info.nid; 1950 num_ranges = 1; 1951 break; 1952 } 1953 1954 if (gmc_v9_0_is_node_present(node_ids, num_ranges, 1955 numa_info.nid)) 1956 continue; 1957 1958 node_ids[num_ranges] = numa_info.nid; 1959 mem_ranges[num_ranges].numa.node = numa_info.nid; 1960 mem_ranges[num_ranges].size = numa_info.size; 1961 ++num_ranges; 1962 } 1963 1964 adev->gmc.num_mem_partitions = num_ranges; 1965 } 1966 1967 static void 1968 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, 1969 struct amdgpu_mem_partition_info *mem_ranges) 1970 { 1971 enum amdgpu_memory_partition mode; 1972 u32 start_addr = 0, size; 1973 int i, r, l; 1974 1975 mode = gmc_v9_0_query_memory_partition(adev); 1976 1977 switch (mode) { 1978 case UNKNOWN_MEMORY_PARTITION_MODE: 1979 adev->gmc.num_mem_partitions = 0; 1980 break; 1981 case AMDGPU_NPS1_PARTITION_MODE: 1982 adev->gmc.num_mem_partitions = 1; 1983 break; 1984 case AMDGPU_NPS2_PARTITION_MODE: 1985 adev->gmc.num_mem_partitions = 2; 1986 break; 1987 case AMDGPU_NPS4_PARTITION_MODE: 1988 if (adev->flags & AMD_IS_APU) 1989 adev->gmc.num_mem_partitions = 3; 1990 else 1991 adev->gmc.num_mem_partitions = 4; 1992 break; 1993 default: 1994 adev->gmc.num_mem_partitions = 1; 1995 break; 1996 } 1997 1998 /* Use NPS range info, if populated */ 1999 r = amdgpu_gmc_get_nps_memranges(adev, mem_ranges, 2000 &adev->gmc.num_mem_partitions); 2001 if (!r) { 2002 l = 0; 2003 for (i = 1; i < adev->gmc.num_mem_partitions; ++i) { 2004 if (mem_ranges[i].range.lpfn > 2005 mem_ranges[i - 1].range.lpfn) 2006 l = i; 2007 } 2008 2009 } else { 2010 if (!adev->gmc.num_mem_partitions) { 2011 dev_err(adev->dev, 2012 "Not able to detect NPS mode, fall back to NPS1"); 2013 adev->gmc.num_mem_partitions = 1; 2014 } 2015 /* Fallback to sw based calculation */ 2016 size = (adev->gmc.real_vram_size + SZ_16M) >> AMDGPU_GPU_PAGE_SHIFT; 2017 size /= adev->gmc.num_mem_partitions; 2018 2019 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 2020 mem_ranges[i].range.fpfn = start_addr; 2021 mem_ranges[i].size = 2022 ((u64)size << AMDGPU_GPU_PAGE_SHIFT); 2023 mem_ranges[i].range.lpfn = start_addr + size - 1; 2024 start_addr += size; 2025 } 2026 2027 l = adev->gmc.num_mem_partitions - 1; 2028 } 2029 2030 /* Adjust the last one */ 2031 mem_ranges[l].range.lpfn = 2032 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; 2033 mem_ranges[l].size = 2034 adev->gmc.real_vram_size - 2035 ((u64)mem_ranges[l].range.fpfn << AMDGPU_GPU_PAGE_SHIFT); 2036 } 2037 2038 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev) 2039 { 2040 bool valid; 2041 2042 adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES, 2043 sizeof(struct amdgpu_mem_partition_info), 2044 GFP_KERNEL); 2045 if (!adev->gmc.mem_partitions) 2046 return -ENOMEM; 2047 2048 /* TODO : Get the range from PSP/Discovery for dGPU */ 2049 if (adev->gmc.is_app_apu) 2050 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); 2051 else 2052 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 2053 2054 if (amdgpu_sriov_vf(adev)) 2055 valid = true; 2056 else 2057 valid = gmc_v9_0_validate_partition_info(adev); 2058 if (!valid) { 2059 /* TODO: handle invalid case */ 2060 dev_WARN(adev->dev, 2061 "Mem ranges not matching with hardware config"); 2062 } 2063 2064 return 0; 2065 } 2066 2067 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 2068 { 2069 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 2070 adev->gmc.vram_width = 128 * 64; 2071 2072 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 2073 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; 2074 } 2075 2076 static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) 2077 { 2078 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 2079 struct amdgpu_device *adev = ip_block->adev; 2080 unsigned long inst_mask = adev->aid_mask; 2081 2082 adev->gfxhub.funcs->init(adev); 2083 2084 adev->mmhub.funcs->init(adev); 2085 2086 spin_lock_init(&adev->gmc.invalidate_lock); 2087 2088 if (gmc_v9_0_is_multi_chiplet(adev)) { 2089 gmc_v9_4_3_init_vram_info(adev); 2090 } else if (!adev->bios) { 2091 if (adev->flags & AMD_IS_APU) { 2092 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 2093 adev->gmc.vram_width = 64 * 64; 2094 } else { 2095 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 2096 adev->gmc.vram_width = 128 * 64; 2097 } 2098 } else { 2099 r = amdgpu_atomfirmware_get_vram_info(adev, 2100 &vram_width, &vram_type, &vram_vendor); 2101 if (amdgpu_sriov_vf(adev)) 2102 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 2103 * and DF related registers is not readable, seems hardcord is the 2104 * only way to set the correct vram_width 2105 */ 2106 adev->gmc.vram_width = 2048; 2107 else if (amdgpu_emu_mode != 1) 2108 adev->gmc.vram_width = vram_width; 2109 2110 if (!adev->gmc.vram_width) { 2111 int chansize, numchan; 2112 2113 /* hbm memory channel size */ 2114 if (adev->flags & AMD_IS_APU) 2115 chansize = 64; 2116 else 2117 chansize = 128; 2118 if (adev->df.funcs && 2119 adev->df.funcs->get_hbm_channel_number) { 2120 numchan = adev->df.funcs->get_hbm_channel_number(adev); 2121 adev->gmc.vram_width = numchan * chansize; 2122 } 2123 } 2124 2125 adev->gmc.vram_type = vram_type; 2126 adev->gmc.vram_vendor = vram_vendor; 2127 } 2128 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2129 case IP_VERSION(9, 1, 0): 2130 case IP_VERSION(9, 2, 2): 2131 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2132 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2133 2134 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 2135 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2136 } else { 2137 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 2138 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 2139 adev->gmc.translate_further = 2140 adev->vm_manager.num_level > 1; 2141 } 2142 break; 2143 case IP_VERSION(9, 0, 1): 2144 case IP_VERSION(9, 2, 1): 2145 case IP_VERSION(9, 4, 0): 2146 case IP_VERSION(9, 3, 0): 2147 case IP_VERSION(9, 4, 2): 2148 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2149 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2150 2151 /* 2152 * To fulfill 4-level page support, 2153 * vm size is 256TB (48bit), maximum size of Vega10, 2154 * block size 512 (9bit) 2155 */ 2156 2157 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2158 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 2159 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2160 break; 2161 case IP_VERSION(9, 4, 1): 2162 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2163 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2164 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 2165 2166 /* Keep the vm size same with Vega20 */ 2167 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2168 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2169 break; 2170 case IP_VERSION(9, 4, 3): 2171 case IP_VERSION(9, 4, 4): 2172 case IP_VERSION(9, 5, 0): 2173 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 2174 NUM_XCC(adev->gfx.xcc_mask)); 2175 2176 inst_mask <<= AMDGPU_MMHUB0(0); 2177 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 2178 2179 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2180 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2181 break; 2182 default: 2183 break; 2184 } 2185 2186 /* This interrupt is VMC page fault.*/ 2187 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 2188 &adev->gmc.vm_fault); 2189 if (r) 2190 return r; 2191 2192 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) { 2193 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 2194 &adev->gmc.vm_fault); 2195 if (r) 2196 return r; 2197 } 2198 2199 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 2200 &adev->gmc.vm_fault); 2201 2202 if (r) 2203 return r; 2204 2205 if (!amdgpu_sriov_vf(adev) && 2206 !adev->gmc.xgmi.connected_to_cpu && 2207 !adev->gmc.is_app_apu) { 2208 /* interrupt sent to DF. */ 2209 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 2210 &adev->gmc.ecc_irq); 2211 if (r) 2212 return r; 2213 } 2214 2215 /* Set the internal MC address mask 2216 * This is the max address of the GPU's 2217 * internal address space. 2218 */ 2219 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 2220 2221 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= 2222 IP_VERSION(9, 4, 2) ? 2223 48 : 2224 44; 2225 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 2226 if (r) { 2227 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 2228 return r; 2229 } 2230 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 2231 2232 r = gmc_v9_0_mc_init(adev); 2233 if (r) 2234 return r; 2235 2236 amdgpu_gmc_get_vbios_allocations(adev); 2237 2238 if (gmc_v9_0_is_multi_chiplet(adev)) { 2239 r = gmc_v9_0_init_mem_ranges(adev); 2240 if (r) 2241 return r; 2242 } 2243 2244 /* Memory manager */ 2245 r = amdgpu_bo_init(adev); 2246 if (r) 2247 return r; 2248 2249 r = gmc_v9_0_gart_init(adev); 2250 if (r) 2251 return r; 2252 2253 gmc_v9_0_init_nps_details(adev); 2254 /* 2255 * number of VMs 2256 * VMID 0 is reserved for System 2257 * amdgpu graphics/compute will use VMIDs 1..n-1 2258 * amdkfd will use VMIDs n..15 2259 * 2260 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2261 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2262 * for video processing. 2263 */ 2264 adev->vm_manager.first_kfd_vmid = 2265 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 2266 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 2267 gmc_v9_0_is_multi_chiplet(adev)) ? 2268 3 : 2269 8; 2270 2271 amdgpu_vm_manager_init(adev); 2272 2273 gmc_v9_0_save_registers(adev); 2274 2275 r = amdgpu_gmc_ras_sw_init(adev); 2276 if (r) 2277 return r; 2278 2279 if (gmc_v9_0_is_multi_chiplet(adev)) 2280 amdgpu_gmc_sysfs_init(adev); 2281 2282 return 0; 2283 } 2284 2285 static int gmc_v9_0_sw_fini(struct amdgpu_ip_block *ip_block) 2286 { 2287 struct amdgpu_device *adev = ip_block->adev; 2288 2289 if (gmc_v9_0_is_multi_chiplet(adev)) 2290 amdgpu_gmc_sysfs_fini(adev); 2291 2292 amdgpu_gmc_ras_fini(adev); 2293 amdgpu_gem_force_release(adev); 2294 amdgpu_vm_manager_fini(adev); 2295 if (!adev->gmc.real_vram_size) { 2296 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2297 amdgpu_gart_table_ram_free(adev); 2298 } else { 2299 amdgpu_gart_table_vram_free(adev); 2300 } 2301 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2302 amdgpu_bo_fini(adev); 2303 2304 adev->gmc.num_mem_partitions = 0; 2305 kfree(adev->gmc.mem_partitions); 2306 2307 return 0; 2308 } 2309 2310 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2311 { 2312 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 2313 case IP_VERSION(9, 0, 0): 2314 if (amdgpu_sriov_vf(adev)) 2315 break; 2316 fallthrough; 2317 case IP_VERSION(9, 4, 0): 2318 soc15_program_register_sequence(adev, 2319 golden_settings_mmhub_1_0_0, 2320 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2321 soc15_program_register_sequence(adev, 2322 golden_settings_athub_1_0_0, 2323 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2324 break; 2325 case IP_VERSION(9, 1, 0): 2326 case IP_VERSION(9, 2, 0): 2327 /* TODO for renoir */ 2328 soc15_program_register_sequence(adev, 2329 golden_settings_athub_1_0_0, 2330 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2331 break; 2332 default: 2333 break; 2334 } 2335 } 2336 2337 /** 2338 * gmc_v9_0_restore_registers - restores regs 2339 * 2340 * @adev: amdgpu_device pointer 2341 * 2342 * This restores register values, saved at suspend. 2343 */ 2344 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2345 { 2346 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 2347 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) { 2348 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2349 WARN_ON(adev->gmc.sdpif_register != 2350 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2351 } 2352 } 2353 2354 /** 2355 * gmc_v9_0_gart_enable - gart enable 2356 * 2357 * @adev: amdgpu_device pointer 2358 */ 2359 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2360 { 2361 int r; 2362 2363 if (adev->gmc.xgmi.connected_to_cpu) 2364 amdgpu_gmc_init_pdb0(adev); 2365 2366 if (adev->gart.bo == NULL) { 2367 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2368 return -EINVAL; 2369 } 2370 2371 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2372 2373 if (!adev->in_s0ix) { 2374 r = adev->gfxhub.funcs->gart_enable(adev); 2375 if (r) 2376 return r; 2377 } 2378 2379 r = adev->mmhub.funcs->gart_enable(adev); 2380 if (r) 2381 return r; 2382 2383 DRM_INFO("PCIE GART of %uM enabled.\n", 2384 (unsigned int)(adev->gmc.gart_size >> 20)); 2385 if (adev->gmc.pdb0_bo) 2386 DRM_INFO("PDB0 located at 0x%016llX\n", 2387 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2388 DRM_INFO("PTB located at 0x%016llX\n", 2389 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2390 2391 return 0; 2392 } 2393 2394 static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block) 2395 { 2396 struct amdgpu_device *adev = ip_block->adev; 2397 bool value; 2398 int i, r; 2399 2400 adev->gmc.flush_pasid_uses_kiq = true; 2401 2402 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush 2403 * (type 2), which flushes both. Due to a race condition with 2404 * concurrent memory accesses using the same TLB cache line, we still 2405 * need a second TLB flush after this. 2406 */ 2407 adev->gmc.flush_tlb_needs_extra_type_2 = 2408 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) && 2409 adev->gmc.xgmi.num_physical_nodes; 2410 2411 /* The sequence of these two function calls matters.*/ 2412 gmc_v9_0_init_golden_registers(adev); 2413 2414 if (adev->mode_info.num_crtc) { 2415 /* Lockout access through VGA aperture*/ 2416 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2417 /* disable VGA render */ 2418 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2419 } 2420 2421 if (adev->mmhub.funcs->update_power_gating) 2422 adev->mmhub.funcs->update_power_gating(adev, true); 2423 2424 adev->hdp.funcs->init_registers(adev); 2425 2426 /* After HDP is initialized, flush HDP.*/ 2427 amdgpu_device_flush_hdp(adev, NULL); 2428 2429 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2430 value = false; 2431 else 2432 value = true; 2433 2434 if (!amdgpu_sriov_vf(adev)) { 2435 if (!adev->in_s0ix) 2436 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2437 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2438 } 2439 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2440 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2441 continue; 2442 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2443 } 2444 2445 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2446 adev->umc.funcs->init_registers(adev); 2447 2448 r = gmc_v9_0_gart_enable(adev); 2449 if (r) 2450 return r; 2451 2452 if (amdgpu_emu_mode == 1) 2453 return amdgpu_gmc_vram_checking(adev); 2454 2455 return 0; 2456 } 2457 2458 /** 2459 * gmc_v9_0_gart_disable - gart disable 2460 * 2461 * @adev: amdgpu_device pointer 2462 * 2463 * This disables all VM page table. 2464 */ 2465 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2466 { 2467 if (!adev->in_s0ix) 2468 adev->gfxhub.funcs->gart_disable(adev); 2469 adev->mmhub.funcs->gart_disable(adev); 2470 } 2471 2472 static int gmc_v9_0_hw_fini(struct amdgpu_ip_block *ip_block) 2473 { 2474 struct amdgpu_device *adev = ip_block->adev; 2475 2476 gmc_v9_0_gart_disable(adev); 2477 2478 if (amdgpu_sriov_vf(adev)) { 2479 /* full access mode, so don't touch any GMC register */ 2480 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2481 return 0; 2482 } 2483 2484 /* 2485 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2486 * a correct cached state for GMC. Otherwise, the "gate" again 2487 * operation on S3 resuming will fail due to wrong cached state. 2488 */ 2489 if (adev->mmhub.funcs->update_power_gating) 2490 adev->mmhub.funcs->update_power_gating(adev, false); 2491 2492 /* 2493 * For minimal init, late_init is not called, hence VM fault/RAS irqs 2494 * are not enabled. 2495 */ 2496 if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { 2497 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2498 2499 if (adev->gmc.ecc_irq.funcs && 2500 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2501 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 2502 } 2503 2504 return 0; 2505 } 2506 2507 static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block) 2508 { 2509 return gmc_v9_0_hw_fini(ip_block); 2510 } 2511 2512 static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block) 2513 { 2514 struct amdgpu_device *adev = ip_block->adev; 2515 int r; 2516 2517 /* If a reset is done for NPS mode switch, read the memory range 2518 * information again. 2519 */ 2520 if (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS) { 2521 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 2522 adev->gmc.reset_flags &= ~AMDGPU_GMC_INIT_RESET_NPS; 2523 } 2524 2525 r = gmc_v9_0_hw_init(ip_block); 2526 if (r) 2527 return r; 2528 2529 amdgpu_vmid_reset_all(ip_block->adev); 2530 2531 return 0; 2532 } 2533 2534 static bool gmc_v9_0_is_idle(struct amdgpu_ip_block *ip_block) 2535 { 2536 /* MC is always ready in GMC v9.*/ 2537 return true; 2538 } 2539 2540 static int gmc_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 2541 { 2542 /* There is no need to wait for MC idle in GMC v9.*/ 2543 return 0; 2544 } 2545 2546 static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block) 2547 { 2548 /* XXX for emulation.*/ 2549 return 0; 2550 } 2551 2552 static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2553 enum amd_clockgating_state state) 2554 { 2555 struct amdgpu_device *adev = ip_block->adev; 2556 2557 adev->mmhub.funcs->set_clockgating(adev, state); 2558 2559 athub_v1_0_set_clockgating(adev, state); 2560 2561 return 0; 2562 } 2563 2564 static void gmc_v9_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2565 { 2566 struct amdgpu_device *adev = ip_block->adev; 2567 2568 adev->mmhub.funcs->get_clockgating(adev, flags); 2569 2570 athub_v1_0_get_clockgating(adev, flags); 2571 } 2572 2573 static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 2574 enum amd_powergating_state state) 2575 { 2576 return 0; 2577 } 2578 2579 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2580 .name = "gmc_v9_0", 2581 .early_init = gmc_v9_0_early_init, 2582 .late_init = gmc_v9_0_late_init, 2583 .sw_init = gmc_v9_0_sw_init, 2584 .sw_fini = gmc_v9_0_sw_fini, 2585 .hw_init = gmc_v9_0_hw_init, 2586 .hw_fini = gmc_v9_0_hw_fini, 2587 .suspend = gmc_v9_0_suspend, 2588 .resume = gmc_v9_0_resume, 2589 .is_idle = gmc_v9_0_is_idle, 2590 .wait_for_idle = gmc_v9_0_wait_for_idle, 2591 .soft_reset = gmc_v9_0_soft_reset, 2592 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2593 .set_powergating_state = gmc_v9_0_set_powergating_state, 2594 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2595 }; 2596 2597 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = { 2598 .type = AMD_IP_BLOCK_TYPE_GMC, 2599 .major = 9, 2600 .minor = 0, 2601 .rev = 0, 2602 .funcs = &gmc_v9_0_ip_funcs, 2603 }; 2604