1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/pci.h> 26 27 #include <drm/drm_cache.h> 28 29 #include "amdgpu.h" 30 #include "gmc_v9_0.h" 31 #include "amdgpu_atomfirmware.h" 32 #include "amdgpu_gem.h" 33 34 #include "gc/gc_9_0_sh_mask.h" 35 #include "dce/dce_12_0_offset.h" 36 #include "dce/dce_12_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "mmhub/mmhub_1_0_offset.h" 39 #include "athub/athub_1_0_sh_mask.h" 40 #include "athub/athub_1_0_offset.h" 41 #include "oss/osssys_4_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15d.h" 45 #include "soc15_common.h" 46 #include "umc/umc_6_0_sh_mask.h" 47 48 #include "gfxhub_v1_0.h" 49 #include "mmhub_v1_0.h" 50 #include "athub_v1_0.h" 51 #include "gfxhub_v1_1.h" 52 #include "gfxhub_v1_2.h" 53 #include "mmhub_v9_4.h" 54 #include "mmhub_v1_7.h" 55 #include "mmhub_v1_8.h" 56 #include "umc_v6_1.h" 57 #include "umc_v6_0.h" 58 #include "umc_v6_7.h" 59 #include "umc_v12_0.h" 60 #include "hdp_v4_0.h" 61 #include "mca_v3_0.h" 62 63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 64 65 #include "amdgpu_ras.h" 66 #include "amdgpu_xgmi.h" 67 68 /* add these here since we already include dce12 headers and these are for DCN */ 69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL 74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L 75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 77 78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea 79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 80 81 #define MAX_MEM_RANGES 8 82 83 static const char * const gfxhub_client_ids[] = { 84 "CB", 85 "DB", 86 "IA", 87 "WD", 88 "CPF", 89 "CPC", 90 "CPG", 91 "RLC", 92 "TCP", 93 "SQC (inst)", 94 "SQC (data)", 95 "SQG", 96 "PA", 97 }; 98 99 static const char *mmhub_client_ids_raven[][2] = { 100 [0][0] = "MP1", 101 [1][0] = "MP0", 102 [2][0] = "VCN", 103 [3][0] = "VCNU", 104 [4][0] = "HDP", 105 [5][0] = "DCE", 106 [13][0] = "UTCL2", 107 [19][0] = "TLS", 108 [26][0] = "OSS", 109 [27][0] = "SDMA0", 110 [0][1] = "MP1", 111 [1][1] = "MP0", 112 [2][1] = "VCN", 113 [3][1] = "VCNU", 114 [4][1] = "HDP", 115 [5][1] = "XDP", 116 [6][1] = "DBGU0", 117 [7][1] = "DCE", 118 [8][1] = "DCEDWB0", 119 [9][1] = "DCEDWB1", 120 [26][1] = "OSS", 121 [27][1] = "SDMA0", 122 }; 123 124 static const char *mmhub_client_ids_renoir[][2] = { 125 [0][0] = "MP1", 126 [1][0] = "MP0", 127 [2][0] = "HDP", 128 [4][0] = "DCEDMC", 129 [5][0] = "DCEVGA", 130 [13][0] = "UTCL2", 131 [19][0] = "TLS", 132 [26][0] = "OSS", 133 [27][0] = "SDMA0", 134 [28][0] = "VCN", 135 [29][0] = "VCNU", 136 [30][0] = "JPEG", 137 [0][1] = "MP1", 138 [1][1] = "MP0", 139 [2][1] = "HDP", 140 [3][1] = "XDP", 141 [6][1] = "DBGU0", 142 [7][1] = "DCEDMC", 143 [8][1] = "DCEVGA", 144 [9][1] = "DCEDWB", 145 [26][1] = "OSS", 146 [27][1] = "SDMA0", 147 [28][1] = "VCN", 148 [29][1] = "VCNU", 149 [30][1] = "JPEG", 150 }; 151 152 static const char *mmhub_client_ids_vega10[][2] = { 153 [0][0] = "MP0", 154 [1][0] = "UVD", 155 [2][0] = "UVDU", 156 [3][0] = "HDP", 157 [13][0] = "UTCL2", 158 [14][0] = "OSS", 159 [15][0] = "SDMA1", 160 [32+0][0] = "VCE0", 161 [32+1][0] = "VCE0U", 162 [32+2][0] = "XDMA", 163 [32+3][0] = "DCE", 164 [32+4][0] = "MP1", 165 [32+14][0] = "SDMA0", 166 [0][1] = "MP0", 167 [1][1] = "UVD", 168 [2][1] = "UVDU", 169 [3][1] = "DBGU0", 170 [4][1] = "HDP", 171 [5][1] = "XDP", 172 [14][1] = "OSS", 173 [15][1] = "SDMA0", 174 [32+0][1] = "VCE0", 175 [32+1][1] = "VCE0U", 176 [32+2][1] = "XDMA", 177 [32+3][1] = "DCE", 178 [32+4][1] = "DCEDWB", 179 [32+5][1] = "MP1", 180 [32+6][1] = "DBGU1", 181 [32+14][1] = "SDMA1", 182 }; 183 184 static const char *mmhub_client_ids_vega12[][2] = { 185 [0][0] = "MP0", 186 [1][0] = "VCE0", 187 [2][0] = "VCE0U", 188 [3][0] = "HDP", 189 [13][0] = "UTCL2", 190 [14][0] = "OSS", 191 [15][0] = "SDMA1", 192 [32+0][0] = "DCE", 193 [32+1][0] = "XDMA", 194 [32+2][0] = "UVD", 195 [32+3][0] = "UVDU", 196 [32+4][0] = "MP1", 197 [32+15][0] = "SDMA0", 198 [0][1] = "MP0", 199 [1][1] = "VCE0", 200 [2][1] = "VCE0U", 201 [3][1] = "DBGU0", 202 [4][1] = "HDP", 203 [5][1] = "XDP", 204 [14][1] = "OSS", 205 [15][1] = "SDMA0", 206 [32+0][1] = "DCE", 207 [32+1][1] = "DCEDWB", 208 [32+2][1] = "XDMA", 209 [32+3][1] = "UVD", 210 [32+4][1] = "UVDU", 211 [32+5][1] = "MP1", 212 [32+6][1] = "DBGU1", 213 [32+15][1] = "SDMA1", 214 }; 215 216 static const char *mmhub_client_ids_vega20[][2] = { 217 [0][0] = "XDMA", 218 [1][0] = "DCE", 219 [2][0] = "VCE0", 220 [3][0] = "VCE0U", 221 [4][0] = "UVD", 222 [5][0] = "UVD1U", 223 [13][0] = "OSS", 224 [14][0] = "HDP", 225 [15][0] = "SDMA0", 226 [32+0][0] = "UVD", 227 [32+1][0] = "UVDU", 228 [32+2][0] = "MP1", 229 [32+3][0] = "MP0", 230 [32+12][0] = "UTCL2", 231 [32+14][0] = "SDMA1", 232 [0][1] = "XDMA", 233 [1][1] = "DCE", 234 [2][1] = "DCEDWB", 235 [3][1] = "VCE0", 236 [4][1] = "VCE0U", 237 [5][1] = "UVD1", 238 [6][1] = "UVD1U", 239 [7][1] = "DBGU0", 240 [8][1] = "XDP", 241 [13][1] = "OSS", 242 [14][1] = "HDP", 243 [15][1] = "SDMA0", 244 [32+0][1] = "UVD", 245 [32+1][1] = "UVDU", 246 [32+2][1] = "DBGU1", 247 [32+3][1] = "MP1", 248 [32+4][1] = "MP0", 249 [32+14][1] = "SDMA1", 250 }; 251 252 static const char *mmhub_client_ids_arcturus[][2] = { 253 [0][0] = "DBGU1", 254 [1][0] = "XDP", 255 [2][0] = "MP1", 256 [14][0] = "HDP", 257 [171][0] = "JPEG", 258 [172][0] = "VCN", 259 [173][0] = "VCNU", 260 [203][0] = "JPEG1", 261 [204][0] = "VCN1", 262 [205][0] = "VCN1U", 263 [256][0] = "SDMA0", 264 [257][0] = "SDMA1", 265 [258][0] = "SDMA2", 266 [259][0] = "SDMA3", 267 [260][0] = "SDMA4", 268 [261][0] = "SDMA5", 269 [262][0] = "SDMA6", 270 [263][0] = "SDMA7", 271 [384][0] = "OSS", 272 [0][1] = "DBGU1", 273 [1][1] = "XDP", 274 [2][1] = "MP1", 275 [14][1] = "HDP", 276 [171][1] = "JPEG", 277 [172][1] = "VCN", 278 [173][1] = "VCNU", 279 [203][1] = "JPEG1", 280 [204][1] = "VCN1", 281 [205][1] = "VCN1U", 282 [256][1] = "SDMA0", 283 [257][1] = "SDMA1", 284 [258][1] = "SDMA2", 285 [259][1] = "SDMA3", 286 [260][1] = "SDMA4", 287 [261][1] = "SDMA5", 288 [262][1] = "SDMA6", 289 [263][1] = "SDMA7", 290 [384][1] = "OSS", 291 }; 292 293 static const char *mmhub_client_ids_aldebaran[][2] = { 294 [2][0] = "MP1", 295 [3][0] = "MP0", 296 [32+1][0] = "DBGU_IO0", 297 [32+2][0] = "DBGU_IO2", 298 [32+4][0] = "MPIO", 299 [96+11][0] = "JPEG0", 300 [96+12][0] = "VCN0", 301 [96+13][0] = "VCNU0", 302 [128+11][0] = "JPEG1", 303 [128+12][0] = "VCN1", 304 [128+13][0] = "VCNU1", 305 [160+1][0] = "XDP", 306 [160+14][0] = "HDP", 307 [256+0][0] = "SDMA0", 308 [256+1][0] = "SDMA1", 309 [256+2][0] = "SDMA2", 310 [256+3][0] = "SDMA3", 311 [256+4][0] = "SDMA4", 312 [384+0][0] = "OSS", 313 [2][1] = "MP1", 314 [3][1] = "MP0", 315 [32+1][1] = "DBGU_IO0", 316 [32+2][1] = "DBGU_IO2", 317 [32+4][1] = "MPIO", 318 [96+11][1] = "JPEG0", 319 [96+12][1] = "VCN0", 320 [96+13][1] = "VCNU0", 321 [128+11][1] = "JPEG1", 322 [128+12][1] = "VCN1", 323 [128+13][1] = "VCNU1", 324 [160+1][1] = "XDP", 325 [160+14][1] = "HDP", 326 [256+0][1] = "SDMA0", 327 [256+1][1] = "SDMA1", 328 [256+2][1] = "SDMA2", 329 [256+3][1] = "SDMA3", 330 [256+4][1] = "SDMA4", 331 [384+0][1] = "OSS", 332 }; 333 334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = { 335 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa), 336 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565) 337 }; 338 339 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = { 340 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800), 341 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008) 342 }; 343 344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = { 345 (0x000143c0 + 0x00000000), 346 (0x000143c0 + 0x00000800), 347 (0x000143c0 + 0x00001000), 348 (0x000143c0 + 0x00001800), 349 (0x000543c0 + 0x00000000), 350 (0x000543c0 + 0x00000800), 351 (0x000543c0 + 0x00001000), 352 (0x000543c0 + 0x00001800), 353 (0x000943c0 + 0x00000000), 354 (0x000943c0 + 0x00000800), 355 (0x000943c0 + 0x00001000), 356 (0x000943c0 + 0x00001800), 357 (0x000d43c0 + 0x00000000), 358 (0x000d43c0 + 0x00000800), 359 (0x000d43c0 + 0x00001000), 360 (0x000d43c0 + 0x00001800), 361 (0x001143c0 + 0x00000000), 362 (0x001143c0 + 0x00000800), 363 (0x001143c0 + 0x00001000), 364 (0x001143c0 + 0x00001800), 365 (0x001543c0 + 0x00000000), 366 (0x001543c0 + 0x00000800), 367 (0x001543c0 + 0x00001000), 368 (0x001543c0 + 0x00001800), 369 (0x001943c0 + 0x00000000), 370 (0x001943c0 + 0x00000800), 371 (0x001943c0 + 0x00001000), 372 (0x001943c0 + 0x00001800), 373 (0x001d43c0 + 0x00000000), 374 (0x001d43c0 + 0x00000800), 375 (0x001d43c0 + 0x00001000), 376 (0x001d43c0 + 0x00001800), 377 }; 378 379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = { 380 (0x000143e0 + 0x00000000), 381 (0x000143e0 + 0x00000800), 382 (0x000143e0 + 0x00001000), 383 (0x000143e0 + 0x00001800), 384 (0x000543e0 + 0x00000000), 385 (0x000543e0 + 0x00000800), 386 (0x000543e0 + 0x00001000), 387 (0x000543e0 + 0x00001800), 388 (0x000943e0 + 0x00000000), 389 (0x000943e0 + 0x00000800), 390 (0x000943e0 + 0x00001000), 391 (0x000943e0 + 0x00001800), 392 (0x000d43e0 + 0x00000000), 393 (0x000d43e0 + 0x00000800), 394 (0x000d43e0 + 0x00001000), 395 (0x000d43e0 + 0x00001800), 396 (0x001143e0 + 0x00000000), 397 (0x001143e0 + 0x00000800), 398 (0x001143e0 + 0x00001000), 399 (0x001143e0 + 0x00001800), 400 (0x001543e0 + 0x00000000), 401 (0x001543e0 + 0x00000800), 402 (0x001543e0 + 0x00001000), 403 (0x001543e0 + 0x00001800), 404 (0x001943e0 + 0x00000000), 405 (0x001943e0 + 0x00000800), 406 (0x001943e0 + 0x00001000), 407 (0x001943e0 + 0x00001800), 408 (0x001d43e0 + 0x00000000), 409 (0x001d43e0 + 0x00000800), 410 (0x001d43e0 + 0x00001000), 411 (0x001d43e0 + 0x00001800), 412 }; 413 414 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, 415 struct amdgpu_irq_src *src, 416 unsigned int type, 417 enum amdgpu_interrupt_state state) 418 { 419 u32 bits, i, tmp, reg; 420 421 /* Devices newer then VEGA10/12 shall have these programming 422 * sequences performed by PSP BL 423 */ 424 if (adev->asic_type >= CHIP_VEGA20) 425 return 0; 426 427 bits = 0x7f; 428 429 switch (state) { 430 case AMDGPU_IRQ_STATE_DISABLE: 431 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 432 reg = ecc_umc_mcumc_ctrl_addrs[i]; 433 tmp = RREG32(reg); 434 tmp &= ~bits; 435 WREG32(reg, tmp); 436 } 437 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 438 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 439 tmp = RREG32(reg); 440 tmp &= ~bits; 441 WREG32(reg, tmp); 442 } 443 break; 444 case AMDGPU_IRQ_STATE_ENABLE: 445 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) { 446 reg = ecc_umc_mcumc_ctrl_addrs[i]; 447 tmp = RREG32(reg); 448 tmp |= bits; 449 WREG32(reg, tmp); 450 } 451 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) { 452 reg = ecc_umc_mcumc_ctrl_mask_addrs[i]; 453 tmp = RREG32(reg); 454 tmp |= bits; 455 WREG32(reg, tmp); 456 } 457 break; 458 default: 459 break; 460 } 461 462 return 0; 463 } 464 465 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 466 struct amdgpu_irq_src *src, 467 unsigned int type, 468 enum amdgpu_interrupt_state state) 469 { 470 struct amdgpu_vmhub *hub; 471 u32 tmp, reg, bits, i, j; 472 473 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 474 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 475 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 476 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 477 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 478 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 479 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 480 481 switch (state) { 482 case AMDGPU_IRQ_STATE_DISABLE: 483 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 484 hub = &adev->vmhub[j]; 485 for (i = 0; i < 16; i++) { 486 reg = hub->vm_context0_cntl + i; 487 488 /* This works because this interrupt is only 489 * enabled at init/resume and disabled in 490 * fini/suspend, so the overall state doesn't 491 * change over the course of suspend/resume. 492 */ 493 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 494 continue; 495 496 if (j >= AMDGPU_MMHUB0(0)) 497 tmp = RREG32_SOC15_IP(MMHUB, reg); 498 else 499 tmp = RREG32_XCC(reg, j); 500 501 tmp &= ~bits; 502 503 if (j >= AMDGPU_MMHUB0(0)) 504 WREG32_SOC15_IP(MMHUB, reg, tmp); 505 else 506 WREG32_XCC(reg, tmp, j); 507 } 508 } 509 break; 510 case AMDGPU_IRQ_STATE_ENABLE: 511 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 512 hub = &adev->vmhub[j]; 513 for (i = 0; i < 16; i++) { 514 reg = hub->vm_context0_cntl + i; 515 516 /* This works because this interrupt is only 517 * enabled at init/resume and disabled in 518 * fini/suspend, so the overall state doesn't 519 * change over the course of suspend/resume. 520 */ 521 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 522 continue; 523 524 if (j >= AMDGPU_MMHUB0(0)) 525 tmp = RREG32_SOC15_IP(MMHUB, reg); 526 else 527 tmp = RREG32_XCC(reg, j); 528 529 tmp |= bits; 530 531 if (j >= AMDGPU_MMHUB0(0)) 532 WREG32_SOC15_IP(MMHUB, reg, tmp); 533 else 534 WREG32_XCC(reg, tmp, j); 535 } 536 } 537 break; 538 default: 539 break; 540 } 541 542 return 0; 543 } 544 545 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, 546 struct amdgpu_irq_src *source, 547 struct amdgpu_iv_entry *entry) 548 { 549 bool retry_fault = !!(entry->src_data[1] & 0x80); 550 bool write_fault = !!(entry->src_data[1] & 0x20); 551 uint32_t status = 0, cid = 0, rw = 0, fed = 0; 552 struct amdgpu_task_info *task_info; 553 struct amdgpu_vmhub *hub; 554 const char *mmhub_cid; 555 const char *hub_name; 556 unsigned int vmhub; 557 u64 addr; 558 uint32_t cam_index = 0; 559 int ret, xcc_id = 0; 560 uint32_t node_id; 561 562 node_id = entry->node_id; 563 564 addr = (u64)entry->src_data[0] << 12; 565 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 566 567 if (entry->client_id == SOC15_IH_CLIENTID_VMC) { 568 hub_name = "mmhub0"; 569 vmhub = AMDGPU_MMHUB0(node_id / 4); 570 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) { 571 hub_name = "mmhub1"; 572 vmhub = AMDGPU_MMHUB1(0); 573 } else { 574 hub_name = "gfxhub0"; 575 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 577 node_id); 578 if (xcc_id < 0) 579 xcc_id = 0; 580 } 581 vmhub = xcc_id; 582 } 583 hub = &adev->vmhub[vmhub]; 584 585 if (retry_fault) { 586 if (adev->irq.retry_cam_enabled) { 587 /* Delegate it to a different ring if the hardware hasn't 588 * already done it. 589 */ 590 if (entry->ih == &adev->irq.ih) { 591 amdgpu_irq_delegate(adev, entry, 8); 592 return 1; 593 } 594 595 cam_index = entry->src_data[2] & 0x3ff; 596 597 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 598 addr, write_fault); 599 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 600 if (ret) 601 return 1; 602 } else { 603 /* Process it onyl if it's the first fault for this address */ 604 if (entry->ih != &adev->irq.ih_soft && 605 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 606 entry->timestamp)) 607 return 1; 608 609 /* Delegate it to a different ring if the hardware hasn't 610 * already done it. 611 */ 612 if (entry->ih == &adev->irq.ih) { 613 amdgpu_irq_delegate(adev, entry, 8); 614 return 1; 615 } 616 617 /* Try to handle the recoverable page faults by filling page 618 * tables 619 */ 620 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 621 addr, write_fault)) 622 return 1; 623 } 624 } 625 626 if (!printk_ratelimit()) 627 return 0; 628 629 dev_err(adev->dev, 630 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name, 631 retry_fault ? "retry" : "no-retry", 632 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 633 634 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 635 if (task_info) { 636 dev_err(adev->dev, 637 " for process %s pid %d thread %s pid %d)\n", 638 task_info->process_name, task_info->tgid, 639 task_info->task_name, task_info->pid); 640 amdgpu_vm_put_task_info(task_info); 641 } 642 643 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n", 644 addr, entry->client_id, 645 soc15_ih_clientid_name[entry->client_id]); 646 647 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 648 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 649 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n", 650 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4, 651 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : ""); 652 653 if (amdgpu_sriov_vf(adev)) 654 return 0; 655 656 /* 657 * Issue a dummy read to wait for the status register to 658 * be updated to avoid reading an incorrect value due to 659 * the new fast GRBM interface. 660 */ 661 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 662 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 663 RREG32(hub->vm_l2_pro_fault_status); 664 665 status = RREG32(hub->vm_l2_pro_fault_status); 666 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID); 667 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW); 668 fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED); 669 670 /* for fed error, kfd will handle it, return directly */ 671 if (fed && amdgpu_ras_is_poison_mode_supported(adev) && 672 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2))) 673 return 0; 674 675 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 676 677 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub); 678 679 dev_err(adev->dev, 680 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 681 status); 682 if (entry->vmid_src == AMDGPU_GFXHUB(0)) { 683 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 684 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : 685 gfxhub_client_ids[cid], 686 cid); 687 } else { 688 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 689 case IP_VERSION(9, 0, 0): 690 mmhub_cid = mmhub_client_ids_vega10[cid][rw]; 691 break; 692 case IP_VERSION(9, 3, 0): 693 mmhub_cid = mmhub_client_ids_vega12[cid][rw]; 694 break; 695 case IP_VERSION(9, 4, 0): 696 mmhub_cid = mmhub_client_ids_vega20[cid][rw]; 697 break; 698 case IP_VERSION(9, 4, 1): 699 mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; 700 break; 701 case IP_VERSION(9, 1, 0): 702 case IP_VERSION(9, 2, 0): 703 mmhub_cid = mmhub_client_ids_raven[cid][rw]; 704 break; 705 case IP_VERSION(1, 5, 0): 706 case IP_VERSION(2, 4, 0): 707 mmhub_cid = mmhub_client_ids_renoir[cid][rw]; 708 break; 709 case IP_VERSION(1, 8, 0): 710 case IP_VERSION(9, 4, 2): 711 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; 712 break; 713 default: 714 mmhub_cid = NULL; 715 break; 716 } 717 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 718 mmhub_cid ? mmhub_cid : "unknown", cid); 719 } 720 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 721 REG_GET_FIELD(status, 722 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 723 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 724 REG_GET_FIELD(status, 725 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 726 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 727 REG_GET_FIELD(status, 728 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 729 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 730 REG_GET_FIELD(status, 731 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 732 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 733 return 0; 734 } 735 736 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { 737 .set = gmc_v9_0_vm_fault_interrupt_state, 738 .process = gmc_v9_0_process_interrupt, 739 }; 740 741 742 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = { 743 .set = gmc_v9_0_ecc_interrupt_state, 744 .process = amdgpu_umc_process_ecc_irq, 745 }; 746 747 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) 748 { 749 adev->gmc.vm_fault.num_types = 1; 750 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; 751 752 if (!amdgpu_sriov_vf(adev) && 753 !adev->gmc.xgmi.connected_to_cpu && 754 !adev->gmc.is_app_apu) { 755 adev->gmc.ecc_irq.num_types = 1; 756 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; 757 } 758 } 759 760 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid, 761 uint32_t flush_type) 762 { 763 u32 req = 0; 764 765 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 766 PER_VMID_INVALIDATE_REQ, 1 << vmid); 767 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 768 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 769 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 770 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 771 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 772 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 773 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, 774 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 775 776 return req; 777 } 778 779 /** 780 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore 781 * 782 * @adev: amdgpu_device pointer 783 * @vmhub: vmhub type 784 * 785 */ 786 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev, 787 uint32_t vmhub) 788 { 789 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 790 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 791 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 792 return false; 793 794 return ((vmhub == AMDGPU_MMHUB0(0) || 795 vmhub == AMDGPU_MMHUB1(0)) && 796 (!amdgpu_sriov_vf(adev)) && 797 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) && 798 (adev->apu_flags & AMD_APU_IS_PICASSO)))); 799 } 800 801 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 802 uint8_t vmid, uint16_t *p_pasid) 803 { 804 uint32_t value; 805 806 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 807 + vmid); 808 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 809 810 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 811 } 812 813 /* 814 * GART 815 * VMID 0 is the physical GPU addresses as used by the kernel. 816 * VMIDs 1-15 are used for userspace clients and are handled 817 * by the amdgpu vm/hsa code. 818 */ 819 820 /** 821 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type 822 * 823 * @adev: amdgpu_device pointer 824 * @vmid: vm instance to flush 825 * @vmhub: which hub to flush 826 * @flush_type: the flush type 827 * 828 * Flush the TLB for the requested page table using certain type. 829 */ 830 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 831 uint32_t vmhub, uint32_t flush_type) 832 { 833 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub); 834 u32 j, inv_req, tmp, sem, req, ack, inst; 835 const unsigned int eng = 17; 836 struct amdgpu_vmhub *hub; 837 838 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS); 839 840 hub = &adev->vmhub[vmhub]; 841 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type); 842 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 843 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 844 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 845 846 if (vmhub >= AMDGPU_MMHUB0(0)) 847 inst = 0; 848 else 849 inst = vmhub; 850 851 /* This is necessary for SRIOV as well as for GFXOFF to function 852 * properly under bare metal 853 */ 854 if (adev->gfx.kiq[inst].ring.sched.ready && 855 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 856 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 857 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 858 859 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 860 1 << vmid, inst); 861 return; 862 } 863 864 /* This path is needed before KIQ/MES/GFXOFF are set up */ 865 spin_lock(&adev->gmc.invalidate_lock); 866 867 /* 868 * It may lose gpuvm invalidate acknowldege state across power-gating 869 * off cycle, add semaphore acquire before invalidation and semaphore 870 * release after invalidation to avoid entering power gated state 871 * to WA the Issue 872 */ 873 874 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 875 if (use_semaphore) { 876 for (j = 0; j < adev->usec_timeout; j++) { 877 /* a read return value of 1 means semaphore acquire */ 878 if (vmhub >= AMDGPU_MMHUB0(0)) 879 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst)); 880 else 881 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst)); 882 if (tmp & 0x1) 883 break; 884 udelay(1); 885 } 886 887 if (j >= adev->usec_timeout) 888 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 889 } 890 891 if (vmhub >= AMDGPU_MMHUB0(0)) 892 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst)); 893 else 894 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst)); 895 896 /* 897 * Issue a dummy read to wait for the ACK register to 898 * be cleared to avoid a false ACK due to the new fast 899 * GRBM interface. 900 */ 901 if ((vmhub == AMDGPU_GFXHUB(0)) && 902 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) 903 RREG32_NO_KIQ(req); 904 905 for (j = 0; j < adev->usec_timeout; j++) { 906 if (vmhub >= AMDGPU_MMHUB0(0)) 907 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst)); 908 else 909 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst)); 910 if (tmp & (1 << vmid)) 911 break; 912 udelay(1); 913 } 914 915 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 916 if (use_semaphore) { 917 /* 918 * add semaphore release after invalidation, 919 * write with 0 means semaphore release 920 */ 921 if (vmhub >= AMDGPU_MMHUB0(0)) 922 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst)); 923 else 924 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst)); 925 } 926 927 spin_unlock(&adev->gmc.invalidate_lock); 928 929 if (j < adev->usec_timeout) 930 return; 931 932 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 933 } 934 935 /** 936 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid 937 * 938 * @adev: amdgpu_device pointer 939 * @pasid: pasid to be flush 940 * @flush_type: the flush type 941 * @all_hub: flush all hubs 942 * @inst: is used to select which instance of KIQ to use for the invalidation 943 * 944 * Flush the TLB for the requested pasid. 945 */ 946 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 947 uint16_t pasid, uint32_t flush_type, 948 bool all_hub, uint32_t inst) 949 { 950 uint16_t queried; 951 int i, vmid; 952 953 for (vmid = 1; vmid < 16; vmid++) { 954 bool valid; 955 956 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 957 &queried); 958 if (!valid || queried != pasid) 959 continue; 960 961 if (all_hub) { 962 for_each_set_bit(i, adev->vmhubs_mask, 963 AMDGPU_MAX_VMHUBS) 964 gmc_v9_0_flush_gpu_tlb(adev, vmid, i, 965 flush_type); 966 } else { 967 gmc_v9_0_flush_gpu_tlb(adev, vmid, 968 AMDGPU_GFXHUB(0), 969 flush_type); 970 } 971 } 972 } 973 974 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 975 unsigned int vmid, uint64_t pd_addr) 976 { 977 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 978 struct amdgpu_device *adev = ring->adev; 979 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub]; 980 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0); 981 unsigned int eng = ring->vm_inv_eng; 982 983 /* 984 * It may lose gpuvm invalidate acknowldege state across power-gating 985 * off cycle, add semaphore acquire before invalidation and semaphore 986 * release after invalidation to avoid entering power gated state 987 * to WA the Issue 988 */ 989 990 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 991 if (use_semaphore) 992 /* a read return value of 1 means semaphore acuqire */ 993 amdgpu_ring_emit_reg_wait(ring, 994 hub->vm_inv_eng0_sem + 995 hub->eng_distance * eng, 0x1, 0x1); 996 997 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 998 (hub->ctx_addr_distance * vmid), 999 lower_32_bits(pd_addr)); 1000 1001 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1002 (hub->ctx_addr_distance * vmid), 1003 upper_32_bits(pd_addr)); 1004 1005 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 1006 hub->eng_distance * eng, 1007 hub->vm_inv_eng0_ack + 1008 hub->eng_distance * eng, 1009 req, 1 << vmid); 1010 1011 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 1012 if (use_semaphore) 1013 /* 1014 * add semaphore release after invalidation, 1015 * write with 0 means semaphore release 1016 */ 1017 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 1018 hub->eng_distance * eng, 0); 1019 1020 return pd_addr; 1021 } 1022 1023 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 1024 unsigned int pasid) 1025 { 1026 struct amdgpu_device *adev = ring->adev; 1027 uint32_t reg; 1028 1029 /* Do nothing because there's no lut register for mmhub1. */ 1030 if (ring->vm_hub == AMDGPU_MMHUB1(0)) 1031 return; 1032 1033 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 1034 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 1035 else 1036 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 1037 1038 amdgpu_ring_emit_wreg(ring, reg, pasid); 1039 } 1040 1041 /* 1042 * PTE format on VEGA 10: 1043 * 63:59 reserved 1044 * 58:57 mtype 1045 * 56 F 1046 * 55 L 1047 * 54 P 1048 * 53 SW 1049 * 52 T 1050 * 50:48 reserved 1051 * 47:12 4k physical page base address 1052 * 11:7 fragment 1053 * 6 write 1054 * 5 read 1055 * 4 exe 1056 * 3 Z 1057 * 2 snooped 1058 * 1 system 1059 * 0 valid 1060 * 1061 * PDE format on VEGA 10: 1062 * 63:59 block fragment size 1063 * 58:55 reserved 1064 * 54 P 1065 * 53:48 reserved 1066 * 47:6 physical base address of PD or PTE 1067 * 5:3 reserved 1068 * 2 C 1069 * 1 system 1070 * 0 valid 1071 */ 1072 1073 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 1074 1075 { 1076 switch (flags) { 1077 case AMDGPU_VM_MTYPE_DEFAULT: 1078 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1079 case AMDGPU_VM_MTYPE_NC: 1080 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1081 case AMDGPU_VM_MTYPE_WC: 1082 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_WC); 1083 case AMDGPU_VM_MTYPE_RW: 1084 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_RW); 1085 case AMDGPU_VM_MTYPE_CC: 1086 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_CC); 1087 case AMDGPU_VM_MTYPE_UC: 1088 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC); 1089 default: 1090 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC); 1091 } 1092 } 1093 1094 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, 1095 uint64_t *addr, uint64_t *flags) 1096 { 1097 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 1098 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 1099 BUG_ON(*addr & 0xFFFF00000000003FULL); 1100 1101 if (!adev->gmc.translate_further) 1102 return; 1103 1104 if (level == AMDGPU_VM_PDB1) { 1105 /* Set the block fragment size */ 1106 if (!(*flags & AMDGPU_PDE_PTE)) 1107 *flags |= AMDGPU_PDE_BFS(0x9); 1108 1109 } else if (level == AMDGPU_VM_PDB0) { 1110 if (*flags & AMDGPU_PDE_PTE) { 1111 *flags &= ~AMDGPU_PDE_PTE; 1112 if (!(*flags & AMDGPU_PTE_VALID)) 1113 *addr |= 1 << PAGE_SHIFT; 1114 } else { 1115 *flags |= AMDGPU_PTE_TF; 1116 } 1117 } 1118 } 1119 1120 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, 1121 struct amdgpu_bo *bo, 1122 struct amdgpu_bo_va_mapping *mapping, 1123 uint64_t *flags) 1124 { 1125 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 1126 bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM; 1127 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | AMDGPU_GEM_CREATE_EXT_COHERENT); 1128 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; 1129 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 1130 struct amdgpu_vm *vm = mapping->bo_va->base.vm; 1131 unsigned int mtype_local, mtype; 1132 bool snoop = false; 1133 bool is_local; 1134 1135 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1136 case IP_VERSION(9, 4, 1): 1137 case IP_VERSION(9, 4, 2): 1138 if (is_vram) { 1139 if (bo_adev == adev) { 1140 if (uncached) 1141 mtype = MTYPE_UC; 1142 else if (coherent) 1143 mtype = MTYPE_CC; 1144 else 1145 mtype = MTYPE_RW; 1146 /* FIXME: is this still needed? Or does 1147 * amdgpu_ttm_tt_pde_flags already handle this? 1148 */ 1149 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == 1150 IP_VERSION(9, 4, 2) || 1151 amdgpu_ip_version(adev, GC_HWIP, 0) == 1152 IP_VERSION(9, 4, 3)) && 1153 adev->gmc.xgmi.connected_to_cpu) 1154 snoop = true; 1155 } else { 1156 if (uncached || coherent) 1157 mtype = MTYPE_UC; 1158 else 1159 mtype = MTYPE_NC; 1160 if (mapping->bo_va->is_xgmi) 1161 snoop = true; 1162 } 1163 } else { 1164 if (uncached || coherent) 1165 mtype = MTYPE_UC; 1166 else 1167 mtype = MTYPE_NC; 1168 /* FIXME: is this still needed? Or does 1169 * amdgpu_ttm_tt_pde_flags already handle this? 1170 */ 1171 snoop = true; 1172 } 1173 break; 1174 case IP_VERSION(9, 4, 3): 1175 case IP_VERSION(9, 4, 4): 1176 /* Only local VRAM BOs or system memory on non-NUMA APUs 1177 * can be assumed to be local in their entirety. Choose 1178 * MTYPE_NC as safe fallback for all system memory BOs on 1179 * NUMA systems. Their MTYPE can be overridden per-page in 1180 * gmc_v9_0_override_vm_pte_flags. 1181 */ 1182 mtype_local = MTYPE_RW; 1183 if (amdgpu_mtype_local == 1) { 1184 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); 1185 mtype_local = MTYPE_NC; 1186 } else if (amdgpu_mtype_local == 2) { 1187 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n"); 1188 mtype_local = MTYPE_CC; 1189 } else { 1190 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); 1191 } 1192 is_local = (!is_vram && (adev->flags & AMD_IS_APU) && 1193 num_possible_nodes() <= 1) || 1194 (is_vram && adev == bo_adev && 1195 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id); 1196 snoop = true; 1197 if (uncached) { 1198 mtype = MTYPE_UC; 1199 } else if (ext_coherent) { 1200 if (adev->rev_id) 1201 mtype = is_local ? MTYPE_CC : MTYPE_UC; 1202 else 1203 mtype = MTYPE_UC; 1204 } else if (adev->flags & AMD_IS_APU) { 1205 mtype = is_local ? mtype_local : MTYPE_NC; 1206 } else { 1207 /* dGPU */ 1208 if (is_local) 1209 mtype = mtype_local; 1210 else if (is_vram) 1211 mtype = MTYPE_NC; 1212 else 1213 mtype = MTYPE_UC; 1214 } 1215 1216 break; 1217 default: 1218 if (uncached || coherent) 1219 mtype = MTYPE_UC; 1220 else 1221 mtype = MTYPE_NC; 1222 1223 /* FIXME: is this still needed? Or does 1224 * amdgpu_ttm_tt_pde_flags already handle this? 1225 */ 1226 if (!is_vram) 1227 snoop = true; 1228 } 1229 1230 if (mtype != MTYPE_NC) 1231 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype); 1232 1233 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 1234 } 1235 1236 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev, 1237 struct amdgpu_bo_va_mapping *mapping, 1238 uint64_t *flags) 1239 { 1240 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 1241 1242 *flags &= ~AMDGPU_PTE_EXECUTABLE; 1243 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 1244 1245 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 1246 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK; 1247 1248 if (mapping->flags & AMDGPU_PTE_PRT) { 1249 *flags |= AMDGPU_PTE_PRT; 1250 *flags &= ~AMDGPU_PTE_VALID; 1251 } 1252 1253 if (bo && bo->tbo.resource) 1254 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo, 1255 mapping, flags); 1256 } 1257 1258 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev, 1259 struct amdgpu_vm *vm, 1260 uint64_t addr, uint64_t *flags) 1261 { 1262 int local_node, nid; 1263 1264 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system 1265 * memory can use more efficient MTYPEs. 1266 */ 1267 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3) && 1268 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) 1269 return; 1270 1271 /* Only direct-mapped memory allows us to determine the NUMA node from 1272 * the DMA address. 1273 */ 1274 if (!adev->ram_is_direct_mapped) { 1275 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n"); 1276 return; 1277 } 1278 1279 /* MTYPE_NC is the same default and can be overridden. 1280 * MTYPE_UC will be present if the memory is extended-coherent 1281 * and can also be overridden. 1282 */ 1283 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1284 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC) && 1285 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) != 1286 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC)) { 1287 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n"); 1288 return; 1289 } 1290 1291 /* FIXME: Only supported on native mode for now. For carve-out, the 1292 * NUMA affinity of the GPU/VM needs to come from the PCI info because 1293 * memory partitions are not associated with different NUMA nodes. 1294 */ 1295 if (adev->gmc.is_app_apu && vm->mem_id >= 0) { 1296 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node; 1297 } else { 1298 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n"); 1299 return; 1300 } 1301 1302 /* Only handle real RAM. Mappings of PCIe resources don't have struct 1303 * page or NUMA nodes. 1304 */ 1305 if (!page_is_ram(addr >> PAGE_SHIFT)) { 1306 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n"); 1307 return; 1308 } 1309 nid = pfn_to_nid(addr >> PAGE_SHIFT); 1310 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n", 1311 vm->mem_id, local_node, nid); 1312 if (nid == local_node) { 1313 uint64_t old_flags = *flags; 1314 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) == 1315 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC)) { 1316 unsigned int mtype_local = MTYPE_RW; 1317 1318 if (amdgpu_mtype_local == 1) 1319 mtype_local = MTYPE_NC; 1320 else if (amdgpu_mtype_local == 2) 1321 mtype_local = MTYPE_CC; 1322 1323 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype_local); 1324 } else if (adev->rev_id) { 1325 /* MTYPE_UC case */ 1326 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC); 1327 } 1328 1329 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n", 1330 old_flags, *flags); 1331 } 1332 } 1333 1334 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev) 1335 { 1336 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 1337 unsigned int size; 1338 1339 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */ 1340 1341 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1342 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1343 } else { 1344 u32 viewport; 1345 1346 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 1347 case IP_VERSION(1, 0, 0): 1348 case IP_VERSION(1, 0, 1): 1349 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 1350 size = (REG_GET_FIELD(viewport, 1351 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1352 REG_GET_FIELD(viewport, 1353 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1354 4); 1355 break; 1356 case IP_VERSION(2, 1, 0): 1357 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2); 1358 size = (REG_GET_FIELD(viewport, 1359 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 1360 REG_GET_FIELD(viewport, 1361 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) * 1362 4); 1363 break; 1364 default: 1365 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE); 1366 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1367 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1368 4); 1369 break; 1370 } 1371 } 1372 1373 return size; 1374 } 1375 1376 static enum amdgpu_memory_partition 1377 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes) 1378 { 1379 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE; 1380 1381 if (adev->nbio.funcs->get_memory_partition_mode) 1382 mode = adev->nbio.funcs->get_memory_partition_mode(adev, 1383 supp_modes); 1384 1385 return mode; 1386 } 1387 1388 static enum amdgpu_memory_partition 1389 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev) 1390 { 1391 if (amdgpu_sriov_vf(adev)) 1392 return AMDGPU_NPS1_PARTITION_MODE; 1393 1394 return gmc_v9_0_get_memory_partition(adev, NULL); 1395 } 1396 1397 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { 1398 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, 1399 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, 1400 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb, 1401 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping, 1402 .map_mtype = gmc_v9_0_map_mtype, 1403 .get_vm_pde = gmc_v9_0_get_vm_pde, 1404 .get_vm_pte = gmc_v9_0_get_vm_pte, 1405 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, 1406 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, 1407 .query_mem_partition_mode = &gmc_v9_0_query_memory_partition, 1408 }; 1409 1410 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) 1411 { 1412 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; 1413 } 1414 1415 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) 1416 { 1417 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1418 case IP_VERSION(6, 0, 0): 1419 adev->umc.funcs = &umc_v6_0_funcs; 1420 break; 1421 case IP_VERSION(6, 1, 1): 1422 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1423 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1424 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1425 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; 1426 adev->umc.retire_unit = 1; 1427 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1428 adev->umc.ras = &umc_v6_1_ras; 1429 break; 1430 case IP_VERSION(6, 1, 2): 1431 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; 1432 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; 1433 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; 1434 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT; 1435 adev->umc.retire_unit = 1; 1436 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; 1437 adev->umc.ras = &umc_v6_1_ras; 1438 break; 1439 case IP_VERSION(6, 7, 0): 1440 adev->umc.max_ras_err_cnt_per_query = 1441 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL; 1442 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM; 1443 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM; 1444 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET; 1445 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2); 1446 if (!adev->gmc.xgmi.connected_to_cpu) 1447 adev->umc.ras = &umc_v6_7_ras; 1448 if (1 & adev->smuio.funcs->get_die_id(adev)) 1449 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0]; 1450 else 1451 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0]; 1452 break; 1453 case IP_VERSION(12, 0, 0): 1454 adev->umc.max_ras_err_cnt_per_query = 1455 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1456 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM; 1457 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM; 1458 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM; 1459 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET; 1460 adev->umc.active_mask = adev->aid_mask; 1461 adev->umc.retire_unit = UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; 1462 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) 1463 adev->umc.ras = &umc_v12_0_ras; 1464 break; 1465 default: 1466 break; 1467 } 1468 } 1469 1470 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) 1471 { 1472 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1473 case IP_VERSION(9, 4, 1): 1474 adev->mmhub.funcs = &mmhub_v9_4_funcs; 1475 break; 1476 case IP_VERSION(9, 4, 2): 1477 adev->mmhub.funcs = &mmhub_v1_7_funcs; 1478 break; 1479 case IP_VERSION(1, 8, 0): 1480 adev->mmhub.funcs = &mmhub_v1_8_funcs; 1481 break; 1482 default: 1483 adev->mmhub.funcs = &mmhub_v1_0_funcs; 1484 break; 1485 } 1486 } 1487 1488 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) 1489 { 1490 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 1491 case IP_VERSION(9, 4, 0): 1492 adev->mmhub.ras = &mmhub_v1_0_ras; 1493 break; 1494 case IP_VERSION(9, 4, 1): 1495 adev->mmhub.ras = &mmhub_v9_4_ras; 1496 break; 1497 case IP_VERSION(9, 4, 2): 1498 adev->mmhub.ras = &mmhub_v1_7_ras; 1499 break; 1500 case IP_VERSION(1, 8, 0): 1501 adev->mmhub.ras = &mmhub_v1_8_ras; 1502 break; 1503 default: 1504 /* mmhub ras is not available */ 1505 break; 1506 } 1507 } 1508 1509 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) 1510 { 1511 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1512 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 1513 adev->gfxhub.funcs = &gfxhub_v1_2_funcs; 1514 else 1515 adev->gfxhub.funcs = &gfxhub_v1_0_funcs; 1516 } 1517 1518 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev) 1519 { 1520 adev->hdp.ras = &hdp_v4_0_ras; 1521 } 1522 1523 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev) 1524 { 1525 struct amdgpu_mca *mca = &adev->mca; 1526 1527 /* is UMC the right IP to check for MCA? Maybe DF? */ 1528 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 1529 case IP_VERSION(6, 7, 0): 1530 if (!adev->gmc.xgmi.connected_to_cpu) { 1531 mca->mp0.ras = &mca_v3_0_mp0_ras; 1532 mca->mp1.ras = &mca_v3_0_mp1_ras; 1533 mca->mpio.ras = &mca_v3_0_mpio_ras; 1534 } 1535 break; 1536 default: 1537 break; 1538 } 1539 } 1540 1541 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) 1542 { 1543 if (!adev->gmc.xgmi.connected_to_cpu) 1544 adev->gmc.xgmi.ras = &xgmi_ras; 1545 } 1546 1547 static int gmc_v9_0_early_init(void *handle) 1548 { 1549 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1550 1551 /* 1552 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined 1553 * in their IP discovery tables 1554 */ 1555 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) || 1556 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 1557 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1558 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 1559 adev->gmc.xgmi.supported = true; 1560 1561 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) { 1562 adev->gmc.xgmi.supported = true; 1563 adev->gmc.xgmi.connected_to_cpu = 1564 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); 1565 } 1566 1567 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 1568 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { 1569 enum amdgpu_pkg_type pkg_type = 1570 adev->smuio.funcs->get_pkg_type(adev); 1571 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present 1572 * and the APU, can be in used two possible modes: 1573 * - carveout mode 1574 * - native APU mode 1575 * "is_app_apu" can be used to identify the APU in the native 1576 * mode. 1577 */ 1578 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU && 1579 !pci_resource_len(adev->pdev, 0)); 1580 } 1581 1582 gmc_v9_0_set_gmc_funcs(adev); 1583 gmc_v9_0_set_irq_funcs(adev); 1584 gmc_v9_0_set_umc_funcs(adev); 1585 gmc_v9_0_set_mmhub_funcs(adev); 1586 gmc_v9_0_set_mmhub_ras_funcs(adev); 1587 gmc_v9_0_set_gfxhub_funcs(adev); 1588 gmc_v9_0_set_hdp_ras_funcs(adev); 1589 gmc_v9_0_set_mca_ras_funcs(adev); 1590 gmc_v9_0_set_xgmi_ras_funcs(adev); 1591 1592 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1593 adev->gmc.shared_aperture_end = 1594 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1595 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 1596 adev->gmc.private_aperture_end = 1597 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1598 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1599 1600 return 0; 1601 } 1602 1603 static int gmc_v9_0_late_init(void *handle) 1604 { 1605 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1606 int r; 1607 1608 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 1609 if (r) 1610 return r; 1611 1612 /* 1613 * Workaround performance drop issue with VBIOS enables partial 1614 * writes, while disables HBM ECC for vega10. 1615 */ 1616 if (!amdgpu_sriov_vf(adev) && 1617 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) { 1618 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) { 1619 if (adev->df.funcs && 1620 adev->df.funcs->enable_ecc_force_par_wr_rmw) 1621 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false); 1622 } 1623 } 1624 1625 if (!amdgpu_persistent_edc_harvesting_supported(adev)) { 1626 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB); 1627 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP); 1628 } 1629 1630 r = amdgpu_gmc_ras_late_init(adev); 1631 if (r) 1632 return r; 1633 1634 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1635 } 1636 1637 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, 1638 struct amdgpu_gmc *mc) 1639 { 1640 u64 base = adev->mmhub.funcs->get_fb_location(adev); 1641 1642 amdgpu_gmc_set_agp_default(adev, mc); 1643 1644 /* add the xgmi offset of the physical node */ 1645 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1646 if (adev->gmc.xgmi.connected_to_cpu) { 1647 amdgpu_gmc_sysvm_location(adev, mc); 1648 } else { 1649 amdgpu_gmc_vram_location(adev, mc, base); 1650 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 1651 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 1652 amdgpu_gmc_agp_location(adev, mc); 1653 } 1654 /* base offset of vram pages */ 1655 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 1656 1657 /* XXX: add the xgmi offset of the physical node? */ 1658 adev->vm_manager.vram_base_offset += 1659 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 1660 } 1661 1662 /** 1663 * gmc_v9_0_mc_init - initialize the memory controller driver params 1664 * 1665 * @adev: amdgpu_device pointer 1666 * 1667 * Look up the amount of vram, vram width, and decide how to place 1668 * vram and gart within the GPU's physical address space. 1669 * Returns 0 for success. 1670 */ 1671 static int gmc_v9_0_mc_init(struct amdgpu_device *adev) 1672 { 1673 int r; 1674 1675 /* size in MB on si */ 1676 if (!adev->gmc.is_app_apu) { 1677 adev->gmc.mc_vram_size = 1678 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 1679 } else { 1680 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n"); 1681 adev->gmc.mc_vram_size = 0; 1682 } 1683 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 1684 1685 if (!(adev->flags & AMD_IS_APU) && 1686 !adev->gmc.xgmi.connected_to_cpu) { 1687 r = amdgpu_device_resize_fb_bar(adev); 1688 if (r) 1689 return r; 1690 } 1691 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 1692 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 1693 1694 #ifdef CONFIG_X86_64 1695 /* 1696 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi 1697 * interface can use VRAM through here as it appears system reserved 1698 * memory in host address space. 1699 * 1700 * For APUs, VRAM is just the stolen system memory and can be accessed 1701 * directly. 1702 * 1703 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR. 1704 */ 1705 1706 /* check whether both host-gpu and gpu-gpu xgmi links exist */ 1707 if ((!amdgpu_sriov_vf(adev) && 1708 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || 1709 (adev->gmc.xgmi.supported && 1710 adev->gmc.xgmi.connected_to_cpu)) { 1711 adev->gmc.aper_base = 1712 adev->gfxhub.funcs->get_mc_fb_offset(adev) + 1713 adev->gmc.xgmi.physical_node_id * 1714 adev->gmc.xgmi.node_segment_size; 1715 adev->gmc.aper_size = adev->gmc.real_vram_size; 1716 } 1717 1718 #endif 1719 adev->gmc.visible_vram_size = adev->gmc.aper_size; 1720 1721 /* set the gart size */ 1722 if (amdgpu_gart_size == -1) { 1723 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1724 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */ 1725 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */ 1726 case IP_VERSION(9, 4, 0): 1727 case IP_VERSION(9, 4, 1): 1728 case IP_VERSION(9, 4, 2): 1729 case IP_VERSION(9, 4, 3): 1730 case IP_VERSION(9, 4, 4): 1731 default: 1732 adev->gmc.gart_size = 512ULL << 20; 1733 break; 1734 case IP_VERSION(9, 1, 0): /* DCE SG support */ 1735 case IP_VERSION(9, 2, 2): /* DCE SG support */ 1736 case IP_VERSION(9, 3, 0): 1737 adev->gmc.gart_size = 1024ULL << 20; 1738 break; 1739 } 1740 } else { 1741 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 1742 } 1743 1744 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 1745 1746 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); 1747 1748 return 0; 1749 } 1750 1751 static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 1752 { 1753 int r; 1754 1755 if (adev->gart.bo) { 1756 WARN(1, "VEGA10 PCIE GART already initialized\n"); 1757 return 0; 1758 } 1759 1760 if (adev->gmc.xgmi.connected_to_cpu) { 1761 adev->gmc.vmid0_page_table_depth = 1; 1762 adev->gmc.vmid0_page_table_block_size = 12; 1763 } else { 1764 adev->gmc.vmid0_page_table_depth = 0; 1765 adev->gmc.vmid0_page_table_block_size = 0; 1766 } 1767 1768 /* Initialize common gart structure */ 1769 r = amdgpu_gart_init(adev); 1770 if (r) 1771 return r; 1772 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 1773 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC) | 1774 AMDGPU_PTE_EXECUTABLE; 1775 1776 if (!adev->gmc.real_vram_size) { 1777 dev_info(adev->dev, "Put GART in system memory for APU\n"); 1778 r = amdgpu_gart_table_ram_alloc(adev); 1779 if (r) 1780 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); 1781 } else { 1782 r = amdgpu_gart_table_vram_alloc(adev); 1783 if (r) 1784 return r; 1785 1786 if (adev->gmc.xgmi.connected_to_cpu) 1787 r = amdgpu_gmc_pdb0_alloc(adev); 1788 } 1789 1790 return r; 1791 } 1792 1793 /** 1794 * gmc_v9_0_save_registers - saves regs 1795 * 1796 * @adev: amdgpu_device pointer 1797 * 1798 * This saves potential register values that should be 1799 * restored upon resume 1800 */ 1801 static void gmc_v9_0_save_registers(struct amdgpu_device *adev) 1802 { 1803 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 1804 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) 1805 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); 1806 } 1807 1808 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev) 1809 { 1810 enum amdgpu_memory_partition mode; 1811 u32 supp_modes; 1812 bool valid; 1813 1814 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes); 1815 1816 /* Mode detected by hardware not present in supported modes */ 1817 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && 1818 !(BIT(mode - 1) & supp_modes)) 1819 return false; 1820 1821 switch (mode) { 1822 case UNKNOWN_MEMORY_PARTITION_MODE: 1823 case AMDGPU_NPS1_PARTITION_MODE: 1824 valid = (adev->gmc.num_mem_partitions == 1); 1825 break; 1826 case AMDGPU_NPS2_PARTITION_MODE: 1827 valid = (adev->gmc.num_mem_partitions == 2); 1828 break; 1829 case AMDGPU_NPS4_PARTITION_MODE: 1830 valid = (adev->gmc.num_mem_partitions == 3 || 1831 adev->gmc.num_mem_partitions == 4); 1832 break; 1833 default: 1834 valid = false; 1835 } 1836 1837 return valid; 1838 } 1839 1840 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid) 1841 { 1842 int i; 1843 1844 /* Check if node with id 'nid' is present in 'node_ids' array */ 1845 for (i = 0; i < num_ids; ++i) 1846 if (node_ids[i] == nid) 1847 return true; 1848 1849 return false; 1850 } 1851 1852 static void 1853 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev, 1854 struct amdgpu_mem_partition_info *mem_ranges) 1855 { 1856 struct amdgpu_numa_info numa_info; 1857 int node_ids[MAX_MEM_RANGES]; 1858 int num_ranges = 0, ret; 1859 int num_xcc, xcc_id; 1860 uint32_t xcc_mask; 1861 1862 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1863 xcc_mask = (1U << num_xcc) - 1; 1864 1865 for_each_inst(xcc_id, xcc_mask) { 1866 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 1867 if (ret) 1868 continue; 1869 1870 if (numa_info.nid == NUMA_NO_NODE) { 1871 mem_ranges[0].size = numa_info.size; 1872 mem_ranges[0].numa.node = numa_info.nid; 1873 num_ranges = 1; 1874 break; 1875 } 1876 1877 if (gmc_v9_0_is_node_present(node_ids, num_ranges, 1878 numa_info.nid)) 1879 continue; 1880 1881 node_ids[num_ranges] = numa_info.nid; 1882 mem_ranges[num_ranges].numa.node = numa_info.nid; 1883 mem_ranges[num_ranges].size = numa_info.size; 1884 ++num_ranges; 1885 } 1886 1887 adev->gmc.num_mem_partitions = num_ranges; 1888 } 1889 1890 static void 1891 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, 1892 struct amdgpu_mem_partition_info *mem_ranges) 1893 { 1894 enum amdgpu_memory_partition mode; 1895 u32 start_addr = 0, size; 1896 int i, r, l; 1897 1898 mode = gmc_v9_0_query_memory_partition(adev); 1899 1900 switch (mode) { 1901 case UNKNOWN_MEMORY_PARTITION_MODE: 1902 case AMDGPU_NPS1_PARTITION_MODE: 1903 adev->gmc.num_mem_partitions = 1; 1904 break; 1905 case AMDGPU_NPS2_PARTITION_MODE: 1906 adev->gmc.num_mem_partitions = 2; 1907 break; 1908 case AMDGPU_NPS4_PARTITION_MODE: 1909 if (adev->flags & AMD_IS_APU) 1910 adev->gmc.num_mem_partitions = 3; 1911 else 1912 adev->gmc.num_mem_partitions = 4; 1913 break; 1914 default: 1915 adev->gmc.num_mem_partitions = 1; 1916 break; 1917 } 1918 1919 /* Use NPS range info, if populated */ 1920 r = amdgpu_gmc_get_nps_memranges(adev, mem_ranges, 1921 adev->gmc.num_mem_partitions); 1922 if (!r) { 1923 l = 0; 1924 for (i = 1; i < adev->gmc.num_mem_partitions; ++i) { 1925 if (mem_ranges[i].range.lpfn > 1926 mem_ranges[i - 1].range.lpfn) 1927 l = i; 1928 } 1929 1930 } else { 1931 /* Fallback to sw based calculation */ 1932 size = (adev->gmc.real_vram_size + SZ_16M) >> AMDGPU_GPU_PAGE_SHIFT; 1933 size /= adev->gmc.num_mem_partitions; 1934 1935 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 1936 mem_ranges[i].range.fpfn = start_addr; 1937 mem_ranges[i].size = 1938 ((u64)size << AMDGPU_GPU_PAGE_SHIFT); 1939 mem_ranges[i].range.lpfn = start_addr + size - 1; 1940 start_addr += size; 1941 } 1942 1943 l = adev->gmc.num_mem_partitions - 1; 1944 } 1945 1946 /* Adjust the last one */ 1947 mem_ranges[l].range.lpfn = 1948 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1; 1949 mem_ranges[l].size = 1950 adev->gmc.real_vram_size - 1951 ((u64)mem_ranges[l].range.fpfn << AMDGPU_GPU_PAGE_SHIFT); 1952 } 1953 1954 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev) 1955 { 1956 bool valid; 1957 1958 adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES, 1959 sizeof(struct amdgpu_mem_partition_info), 1960 GFP_KERNEL); 1961 if (!adev->gmc.mem_partitions) 1962 return -ENOMEM; 1963 1964 /* TODO : Get the range from PSP/Discovery for dGPU */ 1965 if (adev->gmc.is_app_apu) 1966 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions); 1967 else 1968 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); 1969 1970 if (amdgpu_sriov_vf(adev)) 1971 valid = true; 1972 else 1973 valid = gmc_v9_0_validate_partition_info(adev); 1974 if (!valid) { 1975 /* TODO: handle invalid case */ 1976 dev_WARN(adev->dev, 1977 "Mem ranges not matching with hardware config"); 1978 } 1979 1980 return 0; 1981 } 1982 1983 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) 1984 { 1985 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 1986 adev->gmc.vram_width = 128 * 64; 1987 } 1988 1989 static int gmc_v9_0_sw_init(void *handle) 1990 { 1991 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; 1992 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1993 unsigned long inst_mask = adev->aid_mask; 1994 1995 adev->gfxhub.funcs->init(adev); 1996 1997 adev->mmhub.funcs->init(adev); 1998 1999 spin_lock_init(&adev->gmc.invalidate_lock); 2000 2001 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2002 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { 2003 gmc_v9_4_3_init_vram_info(adev); 2004 } else if (!adev->bios) { 2005 if (adev->flags & AMD_IS_APU) { 2006 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 2007 adev->gmc.vram_width = 64 * 64; 2008 } else { 2009 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; 2010 adev->gmc.vram_width = 128 * 64; 2011 } 2012 } else { 2013 r = amdgpu_atomfirmware_get_vram_info(adev, 2014 &vram_width, &vram_type, &vram_vendor); 2015 if (amdgpu_sriov_vf(adev)) 2016 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, 2017 * and DF related registers is not readable, seems hardcord is the 2018 * only way to set the correct vram_width 2019 */ 2020 adev->gmc.vram_width = 2048; 2021 else if (amdgpu_emu_mode != 1) 2022 adev->gmc.vram_width = vram_width; 2023 2024 if (!adev->gmc.vram_width) { 2025 int chansize, numchan; 2026 2027 /* hbm memory channel size */ 2028 if (adev->flags & AMD_IS_APU) 2029 chansize = 64; 2030 else 2031 chansize = 128; 2032 if (adev->df.funcs && 2033 adev->df.funcs->get_hbm_channel_number) { 2034 numchan = adev->df.funcs->get_hbm_channel_number(adev); 2035 adev->gmc.vram_width = numchan * chansize; 2036 } 2037 } 2038 2039 adev->gmc.vram_type = vram_type; 2040 adev->gmc.vram_vendor = vram_vendor; 2041 } 2042 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2043 case IP_VERSION(9, 1, 0): 2044 case IP_VERSION(9, 2, 2): 2045 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2046 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2047 2048 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { 2049 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2050 } else { 2051 /* vm_size is 128TB + 512GB for legacy 3-level page support */ 2052 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); 2053 adev->gmc.translate_further = 2054 adev->vm_manager.num_level > 1; 2055 } 2056 break; 2057 case IP_VERSION(9, 0, 1): 2058 case IP_VERSION(9, 2, 1): 2059 case IP_VERSION(9, 4, 0): 2060 case IP_VERSION(9, 3, 0): 2061 case IP_VERSION(9, 4, 2): 2062 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2063 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2064 2065 /* 2066 * To fulfill 4-level page support, 2067 * vm size is 256TB (48bit), maximum size of Vega10, 2068 * block size 512 (9bit) 2069 */ 2070 2071 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2072 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) 2073 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2074 break; 2075 case IP_VERSION(9, 4, 1): 2076 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 2077 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 2078 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask); 2079 2080 /* Keep the vm size same with Vega20 */ 2081 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2082 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2083 break; 2084 case IP_VERSION(9, 4, 3): 2085 case IP_VERSION(9, 4, 4): 2086 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), 2087 NUM_XCC(adev->gfx.xcc_mask)); 2088 2089 inst_mask <<= AMDGPU_MMHUB0(0); 2090 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); 2091 2092 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 2093 adev->gmc.translate_further = adev->vm_manager.num_level > 1; 2094 break; 2095 default: 2096 break; 2097 } 2098 2099 /* This interrupt is VMC page fault.*/ 2100 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT, 2101 &adev->gmc.vm_fault); 2102 if (r) 2103 return r; 2104 2105 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) { 2106 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT, 2107 &adev->gmc.vm_fault); 2108 if (r) 2109 return r; 2110 } 2111 2112 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT, 2113 &adev->gmc.vm_fault); 2114 2115 if (r) 2116 return r; 2117 2118 if (!amdgpu_sriov_vf(adev) && 2119 !adev->gmc.xgmi.connected_to_cpu && 2120 !adev->gmc.is_app_apu) { 2121 /* interrupt sent to DF. */ 2122 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 2123 &adev->gmc.ecc_irq); 2124 if (r) 2125 return r; 2126 } 2127 2128 /* Set the internal MC address mask 2129 * This is the max address of the GPU's 2130 * internal address space. 2131 */ 2132 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 2133 2134 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >= 2135 IP_VERSION(9, 4, 2) ? 2136 48 : 2137 44; 2138 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); 2139 if (r) { 2140 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 2141 return r; 2142 } 2143 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); 2144 2145 r = gmc_v9_0_mc_init(adev); 2146 if (r) 2147 return r; 2148 2149 amdgpu_gmc_get_vbios_allocations(adev); 2150 2151 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2152 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { 2153 r = gmc_v9_0_init_mem_ranges(adev); 2154 if (r) 2155 return r; 2156 } 2157 2158 /* Memory manager */ 2159 r = amdgpu_bo_init(adev); 2160 if (r) 2161 return r; 2162 2163 r = gmc_v9_0_gart_init(adev); 2164 if (r) 2165 return r; 2166 2167 /* 2168 * number of VMs 2169 * VMID 0 is reserved for System 2170 * amdgpu graphics/compute will use VMIDs 1..n-1 2171 * amdkfd will use VMIDs n..15 2172 * 2173 * The first KFD VMID is 8 for GPUs with graphics, 3 for 2174 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs 2175 * for video processing. 2176 */ 2177 adev->vm_manager.first_kfd_vmid = 2178 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || 2179 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || 2180 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2181 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) ? 2182 3 : 2183 8; 2184 2185 amdgpu_vm_manager_init(adev); 2186 2187 gmc_v9_0_save_registers(adev); 2188 2189 r = amdgpu_gmc_ras_sw_init(adev); 2190 if (r) 2191 return r; 2192 2193 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2194 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 2195 amdgpu_gmc_sysfs_init(adev); 2196 2197 return 0; 2198 } 2199 2200 static int gmc_v9_0_sw_fini(void *handle) 2201 { 2202 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2203 2204 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || 2205 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) 2206 amdgpu_gmc_sysfs_fini(adev); 2207 2208 amdgpu_gmc_ras_fini(adev); 2209 amdgpu_gem_force_release(adev); 2210 amdgpu_vm_manager_fini(adev); 2211 if (!adev->gmc.real_vram_size) { 2212 dev_info(adev->dev, "Put GART in system memory for APU free\n"); 2213 amdgpu_gart_table_ram_free(adev); 2214 } else { 2215 amdgpu_gart_table_vram_free(adev); 2216 } 2217 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); 2218 amdgpu_bo_fini(adev); 2219 2220 adev->gmc.num_mem_partitions = 0; 2221 kfree(adev->gmc.mem_partitions); 2222 2223 return 0; 2224 } 2225 2226 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) 2227 { 2228 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 2229 case IP_VERSION(9, 0, 0): 2230 if (amdgpu_sriov_vf(adev)) 2231 break; 2232 fallthrough; 2233 case IP_VERSION(9, 4, 0): 2234 soc15_program_register_sequence(adev, 2235 golden_settings_mmhub_1_0_0, 2236 ARRAY_SIZE(golden_settings_mmhub_1_0_0)); 2237 soc15_program_register_sequence(adev, 2238 golden_settings_athub_1_0_0, 2239 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2240 break; 2241 case IP_VERSION(9, 1, 0): 2242 case IP_VERSION(9, 2, 0): 2243 /* TODO for renoir */ 2244 soc15_program_register_sequence(adev, 2245 golden_settings_athub_1_0_0, 2246 ARRAY_SIZE(golden_settings_athub_1_0_0)); 2247 break; 2248 default: 2249 break; 2250 } 2251 } 2252 2253 /** 2254 * gmc_v9_0_restore_registers - restores regs 2255 * 2256 * @adev: amdgpu_device pointer 2257 * 2258 * This restores register values, saved at suspend. 2259 */ 2260 void gmc_v9_0_restore_registers(struct amdgpu_device *adev) 2261 { 2262 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || 2263 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) { 2264 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); 2265 WARN_ON(adev->gmc.sdpif_register != 2266 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0)); 2267 } 2268 } 2269 2270 /** 2271 * gmc_v9_0_gart_enable - gart enable 2272 * 2273 * @adev: amdgpu_device pointer 2274 */ 2275 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) 2276 { 2277 int r; 2278 2279 if (adev->gmc.xgmi.connected_to_cpu) 2280 amdgpu_gmc_init_pdb0(adev); 2281 2282 if (adev->gart.bo == NULL) { 2283 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 2284 return -EINVAL; 2285 } 2286 2287 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 2288 2289 if (!adev->in_s0ix) { 2290 r = adev->gfxhub.funcs->gart_enable(adev); 2291 if (r) 2292 return r; 2293 } 2294 2295 r = adev->mmhub.funcs->gart_enable(adev); 2296 if (r) 2297 return r; 2298 2299 DRM_INFO("PCIE GART of %uM enabled.\n", 2300 (unsigned int)(adev->gmc.gart_size >> 20)); 2301 if (adev->gmc.pdb0_bo) 2302 DRM_INFO("PDB0 located at 0x%016llX\n", 2303 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); 2304 DRM_INFO("PTB located at 0x%016llX\n", 2305 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 2306 2307 return 0; 2308 } 2309 2310 static int gmc_v9_0_hw_init(void *handle) 2311 { 2312 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2313 bool value; 2314 int i, r; 2315 2316 adev->gmc.flush_pasid_uses_kiq = true; 2317 2318 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush 2319 * (type 2), which flushes both. Due to a race condition with 2320 * concurrent memory accesses using the same TLB cache line, we still 2321 * need a second TLB flush after this. 2322 */ 2323 adev->gmc.flush_tlb_needs_extra_type_2 = 2324 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) && 2325 adev->gmc.xgmi.num_physical_nodes; 2326 /* 2327 * TODO: This workaround is badly documented and had a buggy 2328 * implementation. We should probably verify what we do here. 2329 */ 2330 adev->gmc.flush_tlb_needs_extra_type_0 = 2331 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 2332 adev->rev_id == 0; 2333 2334 /* The sequence of these two function calls matters.*/ 2335 gmc_v9_0_init_golden_registers(adev); 2336 2337 if (adev->mode_info.num_crtc) { 2338 /* Lockout access through VGA aperture*/ 2339 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 2340 /* disable VGA render */ 2341 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 2342 } 2343 2344 if (adev->mmhub.funcs->update_power_gating) 2345 adev->mmhub.funcs->update_power_gating(adev, true); 2346 2347 adev->hdp.funcs->init_registers(adev); 2348 2349 /* After HDP is initialized, flush HDP.*/ 2350 adev->hdp.funcs->flush_hdp(adev, NULL); 2351 2352 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 2353 value = false; 2354 else 2355 value = true; 2356 2357 if (!amdgpu_sriov_vf(adev)) { 2358 if (!adev->in_s0ix) 2359 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2360 adev->mmhub.funcs->set_fault_enable_default(adev, value); 2361 } 2362 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2363 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0))) 2364 continue; 2365 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0); 2366 } 2367 2368 if (adev->umc.funcs && adev->umc.funcs->init_registers) 2369 adev->umc.funcs->init_registers(adev); 2370 2371 r = gmc_v9_0_gart_enable(adev); 2372 if (r) 2373 return r; 2374 2375 if (amdgpu_emu_mode == 1) 2376 return amdgpu_gmc_vram_checking(adev); 2377 2378 return 0; 2379 } 2380 2381 /** 2382 * gmc_v9_0_gart_disable - gart disable 2383 * 2384 * @adev: amdgpu_device pointer 2385 * 2386 * This disables all VM page table. 2387 */ 2388 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) 2389 { 2390 if (!adev->in_s0ix) 2391 adev->gfxhub.funcs->gart_disable(adev); 2392 adev->mmhub.funcs->gart_disable(adev); 2393 } 2394 2395 static int gmc_v9_0_hw_fini(void *handle) 2396 { 2397 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2398 2399 gmc_v9_0_gart_disable(adev); 2400 2401 if (amdgpu_sriov_vf(adev)) { 2402 /* full access mode, so don't touch any GMC register */ 2403 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 2404 return 0; 2405 } 2406 2407 /* 2408 * Pair the operations did in gmc_v9_0_hw_init and thus maintain 2409 * a correct cached state for GMC. Otherwise, the "gate" again 2410 * operation on S3 resuming will fail due to wrong cached state. 2411 */ 2412 if (adev->mmhub.funcs->update_power_gating) 2413 adev->mmhub.funcs->update_power_gating(adev, false); 2414 2415 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 2416 2417 if (adev->gmc.ecc_irq.funcs && 2418 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 2419 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 2420 2421 return 0; 2422 } 2423 2424 static int gmc_v9_0_suspend(void *handle) 2425 { 2426 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2427 2428 return gmc_v9_0_hw_fini(adev); 2429 } 2430 2431 static int gmc_v9_0_resume(void *handle) 2432 { 2433 int r; 2434 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2435 2436 r = gmc_v9_0_hw_init(adev); 2437 if (r) 2438 return r; 2439 2440 amdgpu_vmid_reset_all(adev); 2441 2442 return 0; 2443 } 2444 2445 static bool gmc_v9_0_is_idle(void *handle) 2446 { 2447 /* MC is always ready in GMC v9.*/ 2448 return true; 2449 } 2450 2451 static int gmc_v9_0_wait_for_idle(void *handle) 2452 { 2453 /* There is no need to wait for MC idle in GMC v9.*/ 2454 return 0; 2455 } 2456 2457 static int gmc_v9_0_soft_reset(void *handle) 2458 { 2459 /* XXX for emulation.*/ 2460 return 0; 2461 } 2462 2463 static int gmc_v9_0_set_clockgating_state(void *handle, 2464 enum amd_clockgating_state state) 2465 { 2466 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2467 2468 adev->mmhub.funcs->set_clockgating(adev, state); 2469 2470 athub_v1_0_set_clockgating(adev, state); 2471 2472 return 0; 2473 } 2474 2475 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags) 2476 { 2477 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2478 2479 adev->mmhub.funcs->get_clockgating(adev, flags); 2480 2481 athub_v1_0_get_clockgating(adev, flags); 2482 } 2483 2484 static int gmc_v9_0_set_powergating_state(void *handle, 2485 enum amd_powergating_state state) 2486 { 2487 return 0; 2488 } 2489 2490 const struct amd_ip_funcs gmc_v9_0_ip_funcs = { 2491 .name = "gmc_v9_0", 2492 .early_init = gmc_v9_0_early_init, 2493 .late_init = gmc_v9_0_late_init, 2494 .sw_init = gmc_v9_0_sw_init, 2495 .sw_fini = gmc_v9_0_sw_fini, 2496 .hw_init = gmc_v9_0_hw_init, 2497 .hw_fini = gmc_v9_0_hw_fini, 2498 .suspend = gmc_v9_0_suspend, 2499 .resume = gmc_v9_0_resume, 2500 .is_idle = gmc_v9_0_is_idle, 2501 .wait_for_idle = gmc_v9_0_wait_for_idle, 2502 .soft_reset = gmc_v9_0_soft_reset, 2503 .set_clockgating_state = gmc_v9_0_set_clockgating_state, 2504 .set_powergating_state = gmc_v9_0_set_powergating_state, 2505 .get_clockgating_state = gmc_v9_0_get_clockgating_state, 2506 }; 2507 2508 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = { 2509 .type = AMD_IP_BLOCK_TYPE_GMC, 2510 .major = 9, 2511 .minor = 0, 2512 .rev = 0, 2513 .funcs = &gmc_v9_0_ip_funcs, 2514 }; 2515