1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/drm_cache.h> 29 #include "amdgpu.h" 30 #include "gmc_v8_0.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_amdkfd.h" 33 #include "amdgpu_gem.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "bif/bif_5_0_d.h" 39 #include "bif/bif_5_0_sh_mask.h" 40 41 #include "oss/oss_3_0_d.h" 42 #include "oss/oss_3_0_sh_mask.h" 43 44 #include "dce/dce_10_0_d.h" 45 #include "dce/dce_10_0_sh_mask.h" 46 47 #include "vid.h" 48 #include "vi.h" 49 50 #include "amdgpu_atombios.h" 51 52 #include "ivsrcid/ivsrcid_vislands30.h" 53 54 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev); 55 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 56 static int gmc_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block); 57 58 MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 59 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 60 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 61 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); 62 MODULE_FIRMWARE("amdgpu/polaris12_32_mc.bin"); 63 MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin"); 65 MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin"); 66 67 static const u32 golden_settings_tonga_a11[] = { 68 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 69 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 70 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 71 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 72 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 73 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 74 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 75 }; 76 77 static const u32 tonga_mgcg_cgcg_init[] = { 78 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 79 }; 80 81 static const u32 golden_settings_fiji_a10[] = { 82 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 83 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 84 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 85 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 86 }; 87 88 static const u32 fiji_mgcg_cgcg_init[] = { 89 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 90 }; 91 92 static const u32 golden_settings_polaris11_a11[] = { 93 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 94 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 95 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 96 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 97 }; 98 99 static const u32 golden_settings_polaris10_a11[] = { 100 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 101 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 102 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 103 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 104 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 105 }; 106 107 static const u32 cz_mgcg_cgcg_init[] = { 108 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 109 }; 110 111 static const u32 stoney_mgcg_cgcg_init[] = { 112 mmATC_MISC_CG, 0xffffffff, 0x000c0200, 113 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 114 }; 115 116 static const u32 golden_settings_stoney_common[] = { 117 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004, 118 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000 119 }; 120 121 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 122 { 123 switch (adev->asic_type) { 124 case CHIP_FIJI: 125 amdgpu_device_program_register_sequence(adev, 126 fiji_mgcg_cgcg_init, 127 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 128 amdgpu_device_program_register_sequence(adev, 129 golden_settings_fiji_a10, 130 ARRAY_SIZE(golden_settings_fiji_a10)); 131 break; 132 case CHIP_TONGA: 133 amdgpu_device_program_register_sequence(adev, 134 tonga_mgcg_cgcg_init, 135 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 136 amdgpu_device_program_register_sequence(adev, 137 golden_settings_tonga_a11, 138 ARRAY_SIZE(golden_settings_tonga_a11)); 139 break; 140 case CHIP_POLARIS11: 141 case CHIP_POLARIS12: 142 case CHIP_VEGAM: 143 amdgpu_device_program_register_sequence(adev, 144 golden_settings_polaris11_a11, 145 ARRAY_SIZE(golden_settings_polaris11_a11)); 146 break; 147 case CHIP_POLARIS10: 148 amdgpu_device_program_register_sequence(adev, 149 golden_settings_polaris10_a11, 150 ARRAY_SIZE(golden_settings_polaris10_a11)); 151 break; 152 case CHIP_CARRIZO: 153 amdgpu_device_program_register_sequence(adev, 154 cz_mgcg_cgcg_init, 155 ARRAY_SIZE(cz_mgcg_cgcg_init)); 156 break; 157 case CHIP_STONEY: 158 amdgpu_device_program_register_sequence(adev, 159 stoney_mgcg_cgcg_init, 160 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 161 amdgpu_device_program_register_sequence(adev, 162 golden_settings_stoney_common, 163 ARRAY_SIZE(golden_settings_stoney_common)); 164 break; 165 default: 166 break; 167 } 168 } 169 170 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev) 171 { 172 u32 blackout; 173 struct amdgpu_ip_block *ip_block; 174 175 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC); 176 if (!ip_block) 177 return; 178 179 gmc_v8_0_wait_for_idle(ip_block); 180 181 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 182 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 183 /* Block CPU access */ 184 WREG32(mmBIF_FB_EN, 0); 185 /* blackout the MC */ 186 blackout = REG_SET_FIELD(blackout, 187 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 188 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 189 } 190 /* wait for the MC to settle */ 191 udelay(100); 192 } 193 194 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev) 195 { 196 u32 tmp; 197 198 /* unblackout the MC */ 199 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 200 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 201 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 202 /* allow CPU access */ 203 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 204 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 205 WREG32(mmBIF_FB_EN, tmp); 206 } 207 208 /** 209 * gmc_v8_0_init_microcode - load ucode images from disk 210 * 211 * @adev: amdgpu_device pointer 212 * 213 * Use the firmware interface to load the ucode images into 214 * the driver (not loaded into hw). 215 * Returns 0 on success, error on failure. 216 */ 217 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 218 { 219 const char *chip_name; 220 int err; 221 222 DRM_DEBUG("\n"); 223 224 switch (adev->asic_type) { 225 case CHIP_TONGA: 226 chip_name = "tonga"; 227 break; 228 case CHIP_POLARIS11: 229 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) || 230 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) 231 chip_name = "polaris11_k"; 232 else 233 chip_name = "polaris11"; 234 break; 235 case CHIP_POLARIS10: 236 if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) 237 chip_name = "polaris10_k"; 238 else 239 chip_name = "polaris10"; 240 break; 241 case CHIP_POLARIS12: 242 if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) { 243 chip_name = "polaris12_k"; 244 } else { 245 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159); 246 /* Polaris12 32bit ASIC needs a special MC firmware */ 247 if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40) 248 chip_name = "polaris12_32"; 249 else 250 chip_name = "polaris12"; 251 } 252 break; 253 case CHIP_FIJI: 254 case CHIP_CARRIZO: 255 case CHIP_STONEY: 256 case CHIP_VEGAM: 257 return 0; 258 default: 259 return -EINVAL; 260 } 261 262 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, 263 "amdgpu/%s_mc.bin", chip_name); 264 if (err) { 265 pr_err("mc: Failed to load firmware \"%s_mc.bin\"\n", chip_name); 266 amdgpu_ucode_release(&adev->gmc.fw); 267 } 268 return err; 269 } 270 271 /** 272 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw 273 * 274 * @adev: amdgpu_device pointer 275 * 276 * Load the GDDR MC ucode into the hw (VI). 277 * Returns 0 on success, error on failure. 278 */ 279 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) 280 { 281 const struct mc_firmware_header_v1_0 *hdr; 282 const __le32 *fw_data = NULL; 283 const __le32 *io_mc_regs = NULL; 284 u32 running; 285 int i, ucode_size, regs_size; 286 287 /* Skip MC ucode loading on SR-IOV capable boards. 288 * vbios does this for us in asic_init in that case. 289 * Skip MC ucode loading on VF, because hypervisor will do that 290 * for this adaptor. 291 */ 292 if (amdgpu_sriov_bios(adev)) 293 return 0; 294 295 if (!adev->gmc.fw) 296 return -EINVAL; 297 298 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 299 amdgpu_ucode_print_mc_hdr(&hdr->header); 300 301 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 302 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 303 io_mc_regs = (const __le32 *) 304 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 305 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 306 fw_data = (const __le32 *) 307 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 308 309 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 310 311 if (running == 0) { 312 /* reset the engine and set to writable */ 313 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 314 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 315 316 /* load mc io regs */ 317 for (i = 0; i < regs_size; i++) { 318 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 319 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 320 } 321 /* load the MC ucode */ 322 for (i = 0; i < ucode_size; i++) 323 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 324 325 /* put the engine back into the active state */ 326 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 327 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 328 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 329 330 /* wait for training to complete */ 331 for (i = 0; i < adev->usec_timeout; i++) { 332 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 333 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 334 break; 335 udelay(1); 336 } 337 for (i = 0; i < adev->usec_timeout; i++) { 338 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 339 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 340 break; 341 udelay(1); 342 } 343 } 344 345 return 0; 346 } 347 348 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) 349 { 350 const struct mc_firmware_header_v1_0 *hdr; 351 const __le32 *fw_data = NULL; 352 const __le32 *io_mc_regs = NULL; 353 u32 data; 354 int i, ucode_size, regs_size; 355 356 /* Skip MC ucode loading on SR-IOV capable boards. 357 * vbios does this for us in asic_init in that case. 358 * Skip MC ucode loading on VF, because hypervisor will do that 359 * for this adaptor. 360 */ 361 if (amdgpu_sriov_bios(adev)) 362 return 0; 363 364 if (!adev->gmc.fw) 365 return -EINVAL; 366 367 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 368 amdgpu_ucode_print_mc_hdr(&hdr->header); 369 370 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 371 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 372 io_mc_regs = (const __le32 *) 373 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 374 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 375 fw_data = (const __le32 *) 376 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 377 378 data = RREG32(mmMC_SEQ_MISC0); 379 data &= ~(0x40); 380 WREG32(mmMC_SEQ_MISC0, data); 381 382 /* load mc io regs */ 383 for (i = 0; i < regs_size; i++) { 384 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 385 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 386 } 387 388 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 389 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 390 391 /* load the MC ucode */ 392 for (i = 0; i < ucode_size; i++) 393 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 394 395 /* put the engine back into the active state */ 396 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 397 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 398 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 399 400 /* wait for training to complete */ 401 for (i = 0; i < adev->usec_timeout; i++) { 402 data = RREG32(mmMC_SEQ_MISC0); 403 if (data & 0x80) 404 break; 405 udelay(1); 406 } 407 408 return 0; 409 } 410 411 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 412 struct amdgpu_gmc *mc) 413 { 414 u64 base = 0; 415 416 if (!amdgpu_sriov_vf(adev)) 417 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 418 base <<= 24; 419 420 amdgpu_gmc_set_agp_default(adev, mc); 421 amdgpu_gmc_vram_location(adev, mc, base); 422 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 423 } 424 425 /** 426 * gmc_v8_0_mc_program - program the GPU memory controller 427 * 428 * @adev: amdgpu_device pointer 429 * 430 * Set the location of vram, gart, and AGP in the GPU's 431 * physical address space (VI). 432 */ 433 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 434 { 435 struct amdgpu_ip_block *ip_block; 436 u32 tmp; 437 int i, j; 438 439 /* Initialize HDP */ 440 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 441 WREG32((0xb05 + j), 0x00000000); 442 WREG32((0xb06 + j), 0x00000000); 443 WREG32((0xb07 + j), 0x00000000); 444 WREG32((0xb08 + j), 0x00000000); 445 WREG32((0xb09 + j), 0x00000000); 446 } 447 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 448 449 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC); 450 if (!ip_block) 451 return; 452 453 if (gmc_v8_0_wait_for_idle(ip_block)) 454 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 455 456 if (adev->mode_info.num_crtc) { 457 /* Lockout access through VGA aperture*/ 458 tmp = RREG32(mmVGA_HDP_CONTROL); 459 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 460 WREG32(mmVGA_HDP_CONTROL, tmp); 461 462 /* disable VGA render */ 463 tmp = RREG32(mmVGA_RENDER_CONTROL); 464 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 465 WREG32(mmVGA_RENDER_CONTROL, tmp); 466 } 467 /* Update configuration */ 468 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 469 adev->gmc.vram_start >> 12); 470 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 471 adev->gmc.vram_end >> 12); 472 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 473 adev->mem_scratch.gpu_addr >> 12); 474 475 if (amdgpu_sriov_vf(adev)) { 476 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; 477 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); 478 WREG32(mmMC_VM_FB_LOCATION, tmp); 479 /* XXX double check these! */ 480 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 481 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 482 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 483 } 484 485 WREG32(mmMC_VM_AGP_BASE, 0); 486 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22); 487 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22); 488 if (gmc_v8_0_wait_for_idle(ip_block)) 489 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 490 491 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 492 493 tmp = RREG32(mmHDP_MISC_CNTL); 494 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 495 WREG32(mmHDP_MISC_CNTL, tmp); 496 497 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 498 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 499 } 500 501 /** 502 * gmc_v8_0_mc_init - initialize the memory controller driver params 503 * 504 * @adev: amdgpu_device pointer 505 * 506 * Look up the amount of vram, vram width, and decide how to place 507 * vram and gart within the GPU's physical address space (VI). 508 * Returns 0 for success. 509 */ 510 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 511 { 512 int r; 513 u32 tmp; 514 515 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 516 if (!adev->gmc.vram_width) { 517 int chansize, numchan; 518 519 /* Get VRAM informations */ 520 tmp = RREG32(mmMC_ARB_RAMCFG); 521 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) 522 chansize = 64; 523 else 524 chansize = 32; 525 526 tmp = RREG32(mmMC_SHARED_CHMAP); 527 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 528 case 0: 529 default: 530 numchan = 1; 531 break; 532 case 1: 533 numchan = 2; 534 break; 535 case 2: 536 numchan = 4; 537 break; 538 case 3: 539 numchan = 8; 540 break; 541 case 4: 542 numchan = 3; 543 break; 544 case 5: 545 numchan = 6; 546 break; 547 case 6: 548 numchan = 10; 549 break; 550 case 7: 551 numchan = 12; 552 break; 553 case 8: 554 numchan = 16; 555 break; 556 } 557 adev->gmc.vram_width = numchan * chansize; 558 } 559 /* size in MB on si */ 560 tmp = RREG32(mmCONFIG_MEMSIZE); 561 /* some boards may have garbage in the upper 16 bits */ 562 if (tmp & 0xffff0000) { 563 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp); 564 if (tmp & 0xffff) 565 tmp &= 0xffff; 566 } 567 adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL; 568 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 569 570 if (!(adev->flags & AMD_IS_APU)) { 571 r = amdgpu_device_resize_fb_bar(adev); 572 if (r) 573 return r; 574 } 575 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 576 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 577 578 #ifdef CONFIG_X86_64 579 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 580 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 581 adev->gmc.aper_size = adev->gmc.real_vram_size; 582 } 583 #endif 584 585 adev->gmc.visible_vram_size = adev->gmc.aper_size; 586 587 /* set the gart size */ 588 if (amdgpu_gart_size == -1) { 589 switch (adev->asic_type) { 590 case CHIP_POLARIS10: /* all engines support GPUVM */ 591 case CHIP_POLARIS11: /* all engines support GPUVM */ 592 case CHIP_POLARIS12: /* all engines support GPUVM */ 593 case CHIP_VEGAM: /* all engines support GPUVM */ 594 default: 595 adev->gmc.gart_size = 256ULL << 20; 596 break; 597 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ 598 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ 599 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ 600 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ 601 adev->gmc.gart_size = 1024ULL << 20; 602 break; 603 } 604 } else { 605 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 606 } 607 608 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 609 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); 610 611 return 0; 612 } 613 614 /** 615 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid 616 * 617 * @adev: amdgpu_device pointer 618 * @pasid: pasid to be flush 619 * @flush_type: type of flush 620 * @all_hub: flush all hubs 621 * @inst: is used to select which instance of KIQ to use for the invalidation 622 * 623 * Flush the TLB for the requested pasid. 624 */ 625 static void gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 626 uint16_t pasid, uint32_t flush_type, 627 bool all_hub, uint32_t inst) 628 { 629 u32 mask = 0x0; 630 int vmid; 631 632 for (vmid = 1; vmid < 16; vmid++) { 633 u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 634 635 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && 636 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) 637 mask |= 1 << vmid; 638 } 639 640 WREG32(mmVM_INVALIDATE_REQUEST, mask); 641 RREG32(mmVM_INVALIDATE_RESPONSE); 642 } 643 644 /* 645 * GART 646 * VMID 0 is the physical GPU addresses as used by the kernel. 647 * VMIDs 1-15 are used for userspace clients and are handled 648 * by the amdgpu vm/hsa code. 649 */ 650 651 /** 652 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback 653 * 654 * @adev: amdgpu_device pointer 655 * @vmid: vm instance to flush 656 * @vmhub: which hub to flush 657 * @flush_type: type of flush 658 * 659 * Flush the TLB for the requested page table (VI). 660 */ 661 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 662 uint32_t vmhub, uint32_t flush_type) 663 { 664 /* bits 0-15 are the VM contexts0-15 */ 665 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 666 } 667 668 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 669 unsigned int vmid, uint64_t pd_addr) 670 { 671 uint32_t reg; 672 673 if (vmid < 8) 674 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 675 else 676 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 677 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 678 679 /* bits 0-15 are the VM contexts0-15 */ 680 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 681 682 return pd_addr; 683 } 684 685 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 686 unsigned int pasid) 687 { 688 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 689 } 690 691 /* 692 * PTE format on VI: 693 * 63:40 reserved 694 * 39:12 4k physical page base address 695 * 11:7 fragment 696 * 6 write 697 * 5 read 698 * 4 exe 699 * 3 reserved 700 * 2 snooped 701 * 1 system 702 * 0 valid 703 * 704 * PDE format on VI: 705 * 63:59 block fragment size 706 * 58:40 reserved 707 * 39:1 physical base address of PTE 708 * bits 5:1 must be 0. 709 * 0 valid 710 */ 711 712 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, 713 uint64_t *addr, uint64_t *flags) 714 { 715 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 716 } 717 718 static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev, 719 struct amdgpu_bo_va_mapping *mapping, 720 uint64_t *flags) 721 { 722 *flags &= ~AMDGPU_PTE_EXECUTABLE; 723 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 724 *flags &= ~AMDGPU_PTE_PRT; 725 } 726 727 /** 728 * gmc_v8_0_set_fault_enable_default - update VM fault handling 729 * 730 * @adev: amdgpu_device pointer 731 * @value: true redirects VM faults to the default page 732 */ 733 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 734 bool value) 735 { 736 u32 tmp; 737 738 tmp = RREG32(mmVM_CONTEXT1_CNTL); 739 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 740 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 741 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 742 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 743 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 744 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 745 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 746 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 747 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 748 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 749 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 750 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 751 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 752 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 753 WREG32(mmVM_CONTEXT1_CNTL, tmp); 754 } 755 756 /** 757 * gmc_v8_0_set_prt() - set PRT VM fault 758 * 759 * @adev: amdgpu_device pointer 760 * @enable: enable/disable VM fault handling for PRT 761 */ 762 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) 763 { 764 u32 tmp; 765 766 if (enable && !adev->gmc.prt_warning) { 767 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 768 adev->gmc.prt_warning = true; 769 } 770 771 tmp = RREG32(mmVM_PRT_CNTL); 772 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 773 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 774 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 775 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 776 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 777 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 778 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 779 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 780 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 781 L2_CACHE_STORE_INVALID_ENTRIES, enable); 782 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 783 L1_TLB_STORE_INVALID_ENTRIES, enable); 784 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 785 MASK_PDE0_FAULT, enable); 786 WREG32(mmVM_PRT_CNTL, tmp); 787 788 if (enable) { 789 uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >> 790 AMDGPU_GPU_PAGE_SHIFT; 791 uint32_t high = adev->vm_manager.max_pfn - 792 (AMDGPU_VA_RESERVED_TOP >> AMDGPU_GPU_PAGE_SHIFT); 793 794 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 795 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 796 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 797 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 798 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 799 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 800 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 801 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 802 } else { 803 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 804 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 805 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 806 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 807 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 808 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 809 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 810 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 811 } 812 } 813 814 /** 815 * gmc_v8_0_gart_enable - gart enable 816 * 817 * @adev: amdgpu_device pointer 818 * 819 * This sets up the TLBs, programs the page tables for VMID0, 820 * sets up the hw for VMIDs 1-15 which are allocated on 821 * demand, and sets up the global locations for the LDS, GDS, 822 * and GPUVM for FSA64 clients (VI). 823 * Returns 0 for success, errors for failure. 824 */ 825 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 826 { 827 uint64_t table_addr; 828 u32 tmp, field; 829 int i; 830 831 if (adev->gart.bo == NULL) { 832 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 833 return -EINVAL; 834 } 835 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 836 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 837 838 /* Setup TLB control */ 839 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 840 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 841 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 842 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 843 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 844 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 845 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 846 /* Setup L2 cache */ 847 tmp = RREG32(mmVM_L2_CNTL); 848 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 849 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 850 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 851 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 852 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 853 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 854 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 855 WREG32(mmVM_L2_CNTL, tmp); 856 tmp = RREG32(mmVM_L2_CNTL2); 857 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 858 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 859 WREG32(mmVM_L2_CNTL2, tmp); 860 861 field = adev->vm_manager.fragment_size; 862 tmp = RREG32(mmVM_L2_CNTL3); 863 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 864 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 865 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 866 WREG32(mmVM_L2_CNTL3, tmp); 867 /* XXX: set to enable PTE/PDE in system memory */ 868 tmp = RREG32(mmVM_L2_CNTL4); 869 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 870 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 871 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 872 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 873 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 874 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 875 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 876 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 877 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 878 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 879 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 880 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 881 WREG32(mmVM_L2_CNTL4, tmp); 882 /* setup context0 */ 883 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 884 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 885 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 886 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 887 (u32)(adev->dummy_page_addr >> 12)); 888 WREG32(mmVM_CONTEXT0_CNTL2, 0); 889 tmp = RREG32(mmVM_CONTEXT0_CNTL); 890 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 891 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 892 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 893 WREG32(mmVM_CONTEXT0_CNTL, tmp); 894 895 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 896 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 897 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 898 899 /* empty context1-15 */ 900 /* FIXME start with 4G, once using 2 level pt switch to full 901 * vm size space 902 */ 903 /* set vm size, must be a multiple of 4 */ 904 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 905 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 906 for (i = 1; i < AMDGPU_NUM_VMID; i++) { 907 if (i < 8) 908 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 909 table_addr >> 12); 910 else 911 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 912 table_addr >> 12); 913 } 914 915 /* enable context1-15 */ 916 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 917 (u32)(adev->dummy_page_addr >> 12)); 918 WREG32(mmVM_CONTEXT1_CNTL2, 4); 919 tmp = RREG32(mmVM_CONTEXT1_CNTL); 920 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 921 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 922 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 923 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 924 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 925 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 926 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 927 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 928 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 929 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 930 adev->vm_manager.block_size - 9); 931 WREG32(mmVM_CONTEXT1_CNTL, tmp); 932 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 933 gmc_v8_0_set_fault_enable_default(adev, false); 934 else 935 gmc_v8_0_set_fault_enable_default(adev, true); 936 937 gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0); 938 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 939 (unsigned int)(adev->gmc.gart_size >> 20), 940 (unsigned long long)table_addr); 941 return 0; 942 } 943 944 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 945 { 946 int r; 947 948 if (adev->gart.bo) { 949 WARN(1, "R600 PCIE GART already initialized\n"); 950 return 0; 951 } 952 /* Initialize common gart structure */ 953 r = amdgpu_gart_init(adev); 954 if (r) 955 return r; 956 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 957 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; 958 return amdgpu_gart_table_vram_alloc(adev); 959 } 960 961 /** 962 * gmc_v8_0_gart_disable - gart disable 963 * 964 * @adev: amdgpu_device pointer 965 * 966 * This disables all VM page table (VI). 967 */ 968 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 969 { 970 u32 tmp; 971 972 /* Disable all tables */ 973 WREG32(mmVM_CONTEXT0_CNTL, 0); 974 WREG32(mmVM_CONTEXT1_CNTL, 0); 975 /* Setup TLB control */ 976 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 977 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 978 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 979 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 980 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 981 /* Setup L2 cache */ 982 tmp = RREG32(mmVM_L2_CNTL); 983 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 984 WREG32(mmVM_L2_CNTL, tmp); 985 WREG32(mmVM_L2_CNTL2, 0); 986 } 987 988 /** 989 * gmc_v8_0_vm_decode_fault - print human readable fault info 990 * 991 * @adev: amdgpu_device pointer 992 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 993 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 994 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value 995 * @pasid: debug logging only - no functional use 996 * 997 * Print human readable fault information (VI). 998 */ 999 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 1000 u32 addr, u32 mc_client, unsigned int pasid) 1001 { 1002 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 1003 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1004 PROTECTIONS); 1005 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 1006 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 1007 u32 mc_id; 1008 1009 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1010 MEMORY_CLIENT_ID); 1011 1012 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 1013 protections, vmid, pasid, addr, 1014 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1015 MEMORY_CLIENT_RW) ? 1016 "write" : "read", block, mc_client, mc_id); 1017 } 1018 1019 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 1020 { 1021 switch (mc_seq_vram_type) { 1022 case MC_SEQ_MISC0__MT__GDDR1: 1023 return AMDGPU_VRAM_TYPE_GDDR1; 1024 case MC_SEQ_MISC0__MT__DDR2: 1025 return AMDGPU_VRAM_TYPE_DDR2; 1026 case MC_SEQ_MISC0__MT__GDDR3: 1027 return AMDGPU_VRAM_TYPE_GDDR3; 1028 case MC_SEQ_MISC0__MT__GDDR4: 1029 return AMDGPU_VRAM_TYPE_GDDR4; 1030 case MC_SEQ_MISC0__MT__GDDR5: 1031 return AMDGPU_VRAM_TYPE_GDDR5; 1032 case MC_SEQ_MISC0__MT__HBM: 1033 return AMDGPU_VRAM_TYPE_HBM; 1034 case MC_SEQ_MISC0__MT__DDR3: 1035 return AMDGPU_VRAM_TYPE_DDR3; 1036 default: 1037 return AMDGPU_VRAM_TYPE_UNKNOWN; 1038 } 1039 } 1040 1041 static int gmc_v8_0_early_init(struct amdgpu_ip_block *ip_block) 1042 { 1043 struct amdgpu_device *adev = ip_block->adev; 1044 1045 gmc_v8_0_set_gmc_funcs(adev); 1046 gmc_v8_0_set_irq_funcs(adev); 1047 1048 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1049 adev->gmc.shared_aperture_end = 1050 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1051 adev->gmc.private_aperture_start = 1052 adev->gmc.shared_aperture_end + 1; 1053 adev->gmc.private_aperture_end = 1054 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1055 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1056 1057 return 0; 1058 } 1059 1060 static int gmc_v8_0_late_init(struct amdgpu_ip_block *ip_block) 1061 { 1062 struct amdgpu_device *adev = ip_block->adev; 1063 1064 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 1065 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1066 else 1067 return 0; 1068 } 1069 1070 static unsigned int gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev) 1071 { 1072 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 1073 unsigned int size; 1074 1075 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1076 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1077 } else { 1078 u32 viewport = RREG32(mmVIEWPORT_SIZE); 1079 1080 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1081 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1082 4); 1083 } 1084 1085 return size; 1086 } 1087 1088 #define mmMC_SEQ_MISC0_FIJI 0xA71 1089 1090 static int gmc_v8_0_sw_init(struct amdgpu_ip_block *ip_block) 1091 { 1092 int r; 1093 struct amdgpu_device *adev = ip_block->adev; 1094 1095 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1096 1097 if (adev->flags & AMD_IS_APU) { 1098 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 1099 } else { 1100 u32 tmp; 1101 1102 if ((adev->asic_type == CHIP_FIJI) || 1103 (adev->asic_type == CHIP_VEGAM)) 1104 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 1105 else 1106 tmp = RREG32(mmMC_SEQ_MISC0); 1107 tmp &= MC_SEQ_MISC0__MT__MASK; 1108 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); 1109 } 1110 1111 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 1112 if (r) 1113 return r; 1114 1115 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 1116 if (r) 1117 return r; 1118 1119 /* Adjust VM size here. 1120 * Currently set to 4GB ((1 << 20) 4k pages). 1121 * Max GPUVM size for cayman and SI is 40 bits. 1122 */ 1123 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1124 1125 /* Set the internal MC address mask 1126 * This is the max address of the GPU's 1127 * internal address space. 1128 */ 1129 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1130 1131 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); 1132 if (r) { 1133 pr_warn("No suitable DMA available\n"); 1134 return r; 1135 } 1136 adev->need_swiotlb = drm_need_swiotlb(40); 1137 1138 r = gmc_v8_0_init_microcode(adev); 1139 if (r) { 1140 DRM_ERROR("Failed to load mc firmware!\n"); 1141 return r; 1142 } 1143 1144 r = gmc_v8_0_mc_init(adev); 1145 if (r) 1146 return r; 1147 1148 amdgpu_gmc_get_vbios_allocations(adev); 1149 1150 /* Memory manager */ 1151 r = amdgpu_bo_init(adev); 1152 if (r) 1153 return r; 1154 1155 r = gmc_v8_0_gart_init(adev); 1156 if (r) 1157 return r; 1158 1159 /* 1160 * number of VMs 1161 * VMID 0 is reserved for System 1162 * amdgpu graphics/compute will use VMIDs 1-7 1163 * amdkfd will use VMIDs 8-15 1164 */ 1165 adev->vm_manager.first_kfd_vmid = 8; 1166 amdgpu_vm_manager_init(adev); 1167 1168 /* base offset of vram pages */ 1169 if (adev->flags & AMD_IS_APU) { 1170 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1171 1172 tmp <<= 22; 1173 adev->vm_manager.vram_base_offset = tmp; 1174 } else { 1175 adev->vm_manager.vram_base_offset = 0; 1176 } 1177 1178 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1179 GFP_KERNEL); 1180 if (!adev->gmc.vm_fault_info) 1181 return -ENOMEM; 1182 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1183 1184 return 0; 1185 } 1186 1187 static int gmc_v8_0_sw_fini(struct amdgpu_ip_block *ip_block) 1188 { 1189 struct amdgpu_device *adev = ip_block->adev; 1190 1191 amdgpu_gem_force_release(adev); 1192 amdgpu_vm_manager_fini(adev); 1193 kfree(adev->gmc.vm_fault_info); 1194 amdgpu_gart_table_vram_free(adev); 1195 amdgpu_bo_fini(adev); 1196 amdgpu_ucode_release(&adev->gmc.fw); 1197 1198 return 0; 1199 } 1200 1201 static int gmc_v8_0_hw_init(struct amdgpu_ip_block *ip_block) 1202 { 1203 int r; 1204 struct amdgpu_device *adev = ip_block->adev; 1205 1206 gmc_v8_0_init_golden_registers(adev); 1207 1208 gmc_v8_0_mc_program(adev); 1209 1210 if (adev->asic_type == CHIP_TONGA) { 1211 r = gmc_v8_0_tonga_mc_load_microcode(adev); 1212 if (r) { 1213 DRM_ERROR("Failed to load MC firmware!\n"); 1214 return r; 1215 } 1216 } else if (adev->asic_type == CHIP_POLARIS11 || 1217 adev->asic_type == CHIP_POLARIS10 || 1218 adev->asic_type == CHIP_POLARIS12) { 1219 r = gmc_v8_0_polaris_mc_load_microcode(adev); 1220 if (r) { 1221 DRM_ERROR("Failed to load MC firmware!\n"); 1222 return r; 1223 } 1224 } 1225 1226 r = gmc_v8_0_gart_enable(adev); 1227 if (r) 1228 return r; 1229 1230 if (amdgpu_emu_mode == 1) 1231 return amdgpu_gmc_vram_checking(adev); 1232 1233 return 0; 1234 } 1235 1236 static int gmc_v8_0_hw_fini(struct amdgpu_ip_block *ip_block) 1237 { 1238 struct amdgpu_device *adev = ip_block->adev; 1239 1240 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1241 gmc_v8_0_gart_disable(adev); 1242 1243 return 0; 1244 } 1245 1246 static int gmc_v8_0_suspend(struct amdgpu_ip_block *ip_block) 1247 { 1248 gmc_v8_0_hw_fini(ip_block); 1249 1250 return 0; 1251 } 1252 1253 static int gmc_v8_0_resume(struct amdgpu_ip_block *ip_block) 1254 { 1255 int r; 1256 1257 r = gmc_v8_0_hw_init(ip_block); 1258 if (r) 1259 return r; 1260 1261 amdgpu_vmid_reset_all(ip_block->adev); 1262 1263 return 0; 1264 } 1265 1266 static bool gmc_v8_0_is_idle(void *handle) 1267 { 1268 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1269 u32 tmp = RREG32(mmSRBM_STATUS); 1270 1271 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1272 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1273 return false; 1274 1275 return true; 1276 } 1277 1278 static int gmc_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1279 { 1280 unsigned int i; 1281 u32 tmp; 1282 struct amdgpu_device *adev = ip_block->adev; 1283 1284 for (i = 0; i < adev->usec_timeout; i++) { 1285 /* read MC_STATUS */ 1286 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1287 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1288 SRBM_STATUS__MCC_BUSY_MASK | 1289 SRBM_STATUS__MCD_BUSY_MASK | 1290 SRBM_STATUS__VMC_BUSY_MASK | 1291 SRBM_STATUS__VMC1_BUSY_MASK); 1292 if (!tmp) 1293 return 0; 1294 udelay(1); 1295 } 1296 return -ETIMEDOUT; 1297 1298 } 1299 1300 static bool gmc_v8_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 1301 { 1302 u32 srbm_soft_reset = 0; 1303 struct amdgpu_device *adev = ip_block->adev; 1304 u32 tmp = RREG32(mmSRBM_STATUS); 1305 1306 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1307 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1308 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1309 1310 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1311 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1312 if (!(adev->flags & AMD_IS_APU)) 1313 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1314 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1315 } 1316 1317 if (srbm_soft_reset) { 1318 adev->gmc.srbm_soft_reset = srbm_soft_reset; 1319 return true; 1320 } 1321 1322 adev->gmc.srbm_soft_reset = 0; 1323 1324 return false; 1325 } 1326 1327 static int gmc_v8_0_pre_soft_reset(struct amdgpu_ip_block *ip_block) 1328 { 1329 struct amdgpu_device *adev = ip_block->adev; 1330 1331 if (!adev->gmc.srbm_soft_reset) 1332 return 0; 1333 1334 gmc_v8_0_mc_stop(adev); 1335 if (gmc_v8_0_wait_for_idle(ip_block)) 1336 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1337 1338 return 0; 1339 } 1340 1341 static int gmc_v8_0_soft_reset(struct amdgpu_ip_block *ip_block) 1342 { 1343 struct amdgpu_device *adev = ip_block->adev; 1344 u32 srbm_soft_reset; 1345 1346 if (!adev->gmc.srbm_soft_reset) 1347 return 0; 1348 srbm_soft_reset = adev->gmc.srbm_soft_reset; 1349 1350 if (srbm_soft_reset) { 1351 u32 tmp; 1352 1353 tmp = RREG32(mmSRBM_SOFT_RESET); 1354 tmp |= srbm_soft_reset; 1355 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1356 WREG32(mmSRBM_SOFT_RESET, tmp); 1357 tmp = RREG32(mmSRBM_SOFT_RESET); 1358 1359 udelay(50); 1360 1361 tmp &= ~srbm_soft_reset; 1362 WREG32(mmSRBM_SOFT_RESET, tmp); 1363 tmp = RREG32(mmSRBM_SOFT_RESET); 1364 1365 /* Wait a little for things to settle down */ 1366 udelay(50); 1367 } 1368 1369 return 0; 1370 } 1371 1372 static int gmc_v8_0_post_soft_reset(struct amdgpu_ip_block *ip_block) 1373 { 1374 struct amdgpu_device *adev = ip_block->adev; 1375 1376 if (!adev->gmc.srbm_soft_reset) 1377 return 0; 1378 1379 gmc_v8_0_mc_resume(adev); 1380 return 0; 1381 } 1382 1383 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1384 struct amdgpu_irq_src *src, 1385 unsigned int type, 1386 enum amdgpu_interrupt_state state) 1387 { 1388 u32 tmp; 1389 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1390 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1391 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1392 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1393 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1394 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1395 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1396 1397 switch (state) { 1398 case AMDGPU_IRQ_STATE_DISABLE: 1399 /* system context */ 1400 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1401 tmp &= ~bits; 1402 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1403 /* VMs */ 1404 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1405 tmp &= ~bits; 1406 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1407 break; 1408 case AMDGPU_IRQ_STATE_ENABLE: 1409 /* system context */ 1410 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1411 tmp |= bits; 1412 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1413 /* VMs */ 1414 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1415 tmp |= bits; 1416 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1417 break; 1418 default: 1419 break; 1420 } 1421 1422 return 0; 1423 } 1424 1425 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1426 struct amdgpu_irq_src *source, 1427 struct amdgpu_iv_entry *entry) 1428 { 1429 u32 addr, status, mc_client, vmid; 1430 1431 if (amdgpu_sriov_vf(adev)) { 1432 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1433 entry->src_id, entry->src_data[0]); 1434 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); 1435 return 0; 1436 } 1437 1438 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1439 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1440 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1441 /* reset addr and status */ 1442 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1443 1444 if (!addr && !status) 1445 return 0; 1446 1447 amdgpu_vm_update_fault_cache(adev, entry->pasid, 1448 ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); 1449 1450 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1451 gmc_v8_0_set_fault_enable_default(adev, false); 1452 1453 if (printk_ratelimit()) { 1454 struct amdgpu_task_info *task_info; 1455 1456 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1457 entry->src_id, entry->src_data[0]); 1458 1459 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 1460 if (task_info) { 1461 dev_err(adev->dev, " for process %s pid %d thread %s pid %d\n", 1462 task_info->process_name, task_info->tgid, 1463 task_info->task_name, task_info->pid); 1464 amdgpu_vm_put_task_info(task_info); 1465 } 1466 1467 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1468 addr); 1469 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1470 status); 1471 1472 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client, 1473 entry->pasid); 1474 } 1475 1476 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1477 VMID); 1478 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1479 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1480 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1481 u32 protections = REG_GET_FIELD(status, 1482 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1483 PROTECTIONS); 1484 1485 info->vmid = vmid; 1486 info->mc_id = REG_GET_FIELD(status, 1487 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1488 MEMORY_CLIENT_ID); 1489 info->status = status; 1490 info->page_addr = addr; 1491 info->prot_valid = protections & 0x7 ? true : false; 1492 info->prot_read = protections & 0x8 ? true : false; 1493 info->prot_write = protections & 0x10 ? true : false; 1494 info->prot_exec = protections & 0x20 ? true : false; 1495 mb(); 1496 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1497 } 1498 1499 return 0; 1500 } 1501 1502 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1503 bool enable) 1504 { 1505 uint32_t data; 1506 1507 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1508 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1509 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1510 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1511 1512 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1513 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1514 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1515 1516 data = RREG32(mmMC_HUB_MISC_VM_CG); 1517 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1518 WREG32(mmMC_HUB_MISC_VM_CG, data); 1519 1520 data = RREG32(mmMC_XPB_CLK_GAT); 1521 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1522 WREG32(mmMC_XPB_CLK_GAT, data); 1523 1524 data = RREG32(mmATC_MISC_CG); 1525 data |= ATC_MISC_CG__ENABLE_MASK; 1526 WREG32(mmATC_MISC_CG, data); 1527 1528 data = RREG32(mmMC_CITF_MISC_WR_CG); 1529 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1530 WREG32(mmMC_CITF_MISC_WR_CG, data); 1531 1532 data = RREG32(mmMC_CITF_MISC_RD_CG); 1533 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1534 WREG32(mmMC_CITF_MISC_RD_CG, data); 1535 1536 data = RREG32(mmMC_CITF_MISC_VM_CG); 1537 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1538 WREG32(mmMC_CITF_MISC_VM_CG, data); 1539 1540 data = RREG32(mmVM_L2_CG); 1541 data |= VM_L2_CG__ENABLE_MASK; 1542 WREG32(mmVM_L2_CG, data); 1543 } else { 1544 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1545 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1546 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1547 1548 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1549 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1550 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1551 1552 data = RREG32(mmMC_HUB_MISC_VM_CG); 1553 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1554 WREG32(mmMC_HUB_MISC_VM_CG, data); 1555 1556 data = RREG32(mmMC_XPB_CLK_GAT); 1557 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1558 WREG32(mmMC_XPB_CLK_GAT, data); 1559 1560 data = RREG32(mmATC_MISC_CG); 1561 data &= ~ATC_MISC_CG__ENABLE_MASK; 1562 WREG32(mmATC_MISC_CG, data); 1563 1564 data = RREG32(mmMC_CITF_MISC_WR_CG); 1565 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1566 WREG32(mmMC_CITF_MISC_WR_CG, data); 1567 1568 data = RREG32(mmMC_CITF_MISC_RD_CG); 1569 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1570 WREG32(mmMC_CITF_MISC_RD_CG, data); 1571 1572 data = RREG32(mmMC_CITF_MISC_VM_CG); 1573 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1574 WREG32(mmMC_CITF_MISC_VM_CG, data); 1575 1576 data = RREG32(mmVM_L2_CG); 1577 data &= ~VM_L2_CG__ENABLE_MASK; 1578 WREG32(mmVM_L2_CG, data); 1579 } 1580 } 1581 1582 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1583 bool enable) 1584 { 1585 uint32_t data; 1586 1587 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1588 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1589 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1590 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1591 1592 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1593 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1594 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1595 1596 data = RREG32(mmMC_HUB_MISC_VM_CG); 1597 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1598 WREG32(mmMC_HUB_MISC_VM_CG, data); 1599 1600 data = RREG32(mmMC_XPB_CLK_GAT); 1601 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1602 WREG32(mmMC_XPB_CLK_GAT, data); 1603 1604 data = RREG32(mmATC_MISC_CG); 1605 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1606 WREG32(mmATC_MISC_CG, data); 1607 1608 data = RREG32(mmMC_CITF_MISC_WR_CG); 1609 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1610 WREG32(mmMC_CITF_MISC_WR_CG, data); 1611 1612 data = RREG32(mmMC_CITF_MISC_RD_CG); 1613 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1614 WREG32(mmMC_CITF_MISC_RD_CG, data); 1615 1616 data = RREG32(mmMC_CITF_MISC_VM_CG); 1617 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1618 WREG32(mmMC_CITF_MISC_VM_CG, data); 1619 1620 data = RREG32(mmVM_L2_CG); 1621 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1622 WREG32(mmVM_L2_CG, data); 1623 } else { 1624 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1625 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1626 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1627 1628 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1629 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1630 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1631 1632 data = RREG32(mmMC_HUB_MISC_VM_CG); 1633 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1634 WREG32(mmMC_HUB_MISC_VM_CG, data); 1635 1636 data = RREG32(mmMC_XPB_CLK_GAT); 1637 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1638 WREG32(mmMC_XPB_CLK_GAT, data); 1639 1640 data = RREG32(mmATC_MISC_CG); 1641 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1642 WREG32(mmATC_MISC_CG, data); 1643 1644 data = RREG32(mmMC_CITF_MISC_WR_CG); 1645 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1646 WREG32(mmMC_CITF_MISC_WR_CG, data); 1647 1648 data = RREG32(mmMC_CITF_MISC_RD_CG); 1649 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1650 WREG32(mmMC_CITF_MISC_RD_CG, data); 1651 1652 data = RREG32(mmMC_CITF_MISC_VM_CG); 1653 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1654 WREG32(mmMC_CITF_MISC_VM_CG, data); 1655 1656 data = RREG32(mmVM_L2_CG); 1657 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1658 WREG32(mmVM_L2_CG, data); 1659 } 1660 } 1661 1662 static int gmc_v8_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1663 enum amd_clockgating_state state) 1664 { 1665 struct amdgpu_device *adev = ip_block->adev; 1666 1667 if (amdgpu_sriov_vf(adev)) 1668 return 0; 1669 1670 switch (adev->asic_type) { 1671 case CHIP_FIJI: 1672 fiji_update_mc_medium_grain_clock_gating(adev, 1673 state == AMD_CG_STATE_GATE); 1674 fiji_update_mc_light_sleep(adev, 1675 state == AMD_CG_STATE_GATE); 1676 break; 1677 default: 1678 break; 1679 } 1680 return 0; 1681 } 1682 1683 static int gmc_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1684 enum amd_powergating_state state) 1685 { 1686 return 0; 1687 } 1688 1689 static void gmc_v8_0_get_clockgating_state(void *handle, u64 *flags) 1690 { 1691 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1692 int data; 1693 1694 if (amdgpu_sriov_vf(adev)) 1695 *flags = 0; 1696 1697 /* AMD_CG_SUPPORT_MC_MGCG */ 1698 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1699 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) 1700 *flags |= AMD_CG_SUPPORT_MC_MGCG; 1701 1702 /* AMD_CG_SUPPORT_MC_LS */ 1703 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK) 1704 *flags |= AMD_CG_SUPPORT_MC_LS; 1705 } 1706 1707 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1708 .name = "gmc_v8_0", 1709 .early_init = gmc_v8_0_early_init, 1710 .late_init = gmc_v8_0_late_init, 1711 .sw_init = gmc_v8_0_sw_init, 1712 .sw_fini = gmc_v8_0_sw_fini, 1713 .hw_init = gmc_v8_0_hw_init, 1714 .hw_fini = gmc_v8_0_hw_fini, 1715 .suspend = gmc_v8_0_suspend, 1716 .resume = gmc_v8_0_resume, 1717 .is_idle = gmc_v8_0_is_idle, 1718 .wait_for_idle = gmc_v8_0_wait_for_idle, 1719 .check_soft_reset = gmc_v8_0_check_soft_reset, 1720 .pre_soft_reset = gmc_v8_0_pre_soft_reset, 1721 .soft_reset = gmc_v8_0_soft_reset, 1722 .post_soft_reset = gmc_v8_0_post_soft_reset, 1723 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1724 .set_powergating_state = gmc_v8_0_set_powergating_state, 1725 .get_clockgating_state = gmc_v8_0_get_clockgating_state, 1726 }; 1727 1728 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = { 1729 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb, 1730 .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid, 1731 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb, 1732 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping, 1733 .set_prt = gmc_v8_0_set_prt, 1734 .get_vm_pde = gmc_v8_0_get_vm_pde, 1735 .get_vm_pte = gmc_v8_0_get_vm_pte, 1736 .get_vbios_fb_size = gmc_v8_0_get_vbios_fb_size, 1737 }; 1738 1739 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1740 .set = gmc_v8_0_vm_fault_interrupt_state, 1741 .process = gmc_v8_0_process_interrupt, 1742 }; 1743 1744 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev) 1745 { 1746 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; 1747 } 1748 1749 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1750 { 1751 adev->gmc.vm_fault.num_types = 1; 1752 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1753 } 1754 1755 const struct amdgpu_ip_block_version gmc_v8_0_ip_block = { 1756 .type = AMD_IP_BLOCK_TYPE_GMC, 1757 .major = 8, 1758 .minor = 0, 1759 .rev = 0, 1760 .funcs = &gmc_v8_0_ip_funcs, 1761 }; 1762 1763 const struct amdgpu_ip_block_version gmc_v8_1_ip_block = { 1764 .type = AMD_IP_BLOCK_TYPE_GMC, 1765 .major = 8, 1766 .minor = 1, 1767 .rev = 0, 1768 .funcs = &gmc_v8_0_ip_funcs, 1769 }; 1770 1771 const struct amdgpu_ip_block_version gmc_v8_5_ip_block = { 1772 .type = AMD_IP_BLOCK_TYPE_GMC, 1773 .major = 8, 1774 .minor = 5, 1775 .rev = 0, 1776 .funcs = &gmc_v8_0_ip_funcs, 1777 }; 1778